def analyzer():
analyzer = LiteScopeAnalyzerDriver(wb_amc.regs, "analyzer", config_csv="../sayma_amc/analyzer.csv", debug=True)
analyzer.configure_group(groups["wishbone"])
analyzer.configure_trigger(cond={"wishbone_access" : 1})
analyzer.run(offset=32, length=128)
write_pattern(32)
errors = check_pattern(32, debug=True)
print("errors: {:d}".format(errors))
analyzer.wait_done()
analyzer.upload()
analyzer.save("dump.vcd")
def analyzer():
groups = {
"dfi_phase0": 0,
"dfi_phase1": 1,
"dfi_phase2": 2,
"dfi_phase3": 3
}
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
analyzer.configure_group(groups["dfi_phase0"])
analyzer.configure_trigger(cond={})
write_test(0x00000000, 1024*MB, False)
read_test(0x00000000, 1024*MB, False)
analyzer.run(offset=32, length=64)
analyzer.wait_done()
analyzer.upload()
analyzer.save("dump.vcd")
from litex.soc.tools.remote import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver
wb = RemoteClient()
wb.open()
# # #
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
analyzer.configure_trigger(cond={"s7pciephy_sink_valid": 1})
#analyzer.configure_trigger(cond={})
analyzer.configure_subsampler(1)
analyzer.run(offset=16, length=64)
analyzer.wait_done()
analyzer.upload()
analyzer.save("dump.vcd")
# # #
wb.close()
#!/usr/bin/env python3
from litex.soc.tools.remote import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver
wb = RemoteClient("192.168.1.50", 1234, csr_data_width=8)
wb.open()
# # #
logic_analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
cond = {}
logic_analyzer.configure_trigger(cond=cond)
logic_analyzer.run(offset=256, length=2048)
while not logic_analyzer.done():
pass
logic_analyzer.upload()
logic_analyzer.save("dump.vcd")
# # #
wb.close()
regs.generator_reset.write(1)
regs.generator_reset.write(0)
regs.generator_base.write(0)
regs.generator_length.write((test_size*8)//128)
regs.generator_start.write(1)
while(not regs.generator_done.read()):
pass
regs.checker_reset.write(1)
regs.checker_reset.write(0)
regs.checker_base.write(0)
regs.checker_length.write((test_size*8)//128)
regs.checker_start.write(1)
while(not regs.checker_done.read()):
pass
print("errors: {:d}".format(regs.checker_err_count.read()))
if run_analyzer:
while not analyzer.done():
pass
analyzer.upload()
analyzer.save("dump.vcd")
# # #
wb.close()
from litex.soc.tools.remote import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver
wb = RemoteClient()
wb.open()
# # #
dumps = {0: "dump.vcd", 1: "dump.sr"}
for group, filename in dumps.items():
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
analyzer.configure_trigger()
analyzer.configure_subsampler(1)
analyzer.configure_group(group)
analyzer.run(offset=128, length=512)
analyzer.wait_done()
analyzer.upload()
analyzer.save(filename)
# # #
wb.close()
def main():
args, wb = connect("LiteX Etherbone Memtest BIST", target='memtest')
print_memmap(wb)
print()
main_ram = wb.mems.main_ram
print("DDR at 0x{:x} -- {} Megabytes".format(
main_ram.base, int(main_ram.size / (1024 * 1024))))
print()
# init
print("Reset")
wb.regs.generator_reset.write(1)
wb.regs.checker_reset.write(1)
wb.regs.generator_reset.write(0)
wb.regs.checker_reset.write(0)
assert not wb.regs.checker_scope_error.read()
print()
analyzer = LiteScopeAnalyzerDriver(wb.regs,
"analyzer",
config_csv='{}/analyzer.csv'.format(
make_testdir(args)),
debug=True)
print("Init analyzer")
#analyzer.configure_trigger(cond={'checker_core_data_error': 1})
analyzer.configure_trigger(cond={'data_error': 1})
analyzer.configure_trigger(cond={})
analyzer.configure_subsampler(1)
analyzer.run(offset=16, length=1024)
assert not analyzer.done()
print()
base = int(512e3)
#length = int((main_ram.size-base)*8/16) # 64e6 == 64 megabytes
#length = int(2e6)
length = int(1)
# write
print("Write")
write_and_check(wb.regs.generator_base, base)
write_and_check(wb.regs.generator_length, length)
assert not wb.regs.generator_done.read()
wb.regs.generator_start.write(1)
print("Waiting", end=' ')
while wb.regs.generator_done.read() == 0:
print(".", end='', flush=True)
time.sleep(0.1)
assert wb.regs.generator_done.read() == 1
print()
# read
assert wb.regs.checker_err_count.read() == 0
print("Read")
write_and_check(wb.regs.checker_base, base)
write_and_check(wb.regs.checker_length, length)
assert not wb.regs.checker_done.read()
assert not analyzer.done()
wb.regs.checker_start.write(1)
print("Waiting")
while wb.regs.checker_done.read() == 0:
print(" Errors:", wb.regs.checker_err_count.read())
time.sleep(0.1)
assert wb.regs.checker_done.read() == 1
print("Final errors:", wb.regs.checker_err_count.read())
errors = wb.regs.checker_err_count.read()
if errors != 0:
# Check litescope
assert analyzer.done()
analyzer.upload()
analyzer.save('sim.vcd')
data = {v.name: v for v in analyzer.dump().variables}
okay = set()
errors = {}
for i in range(0, len(data['clk'].values)):
address = hex(data['data_address'].values[i])
if data['data_error'].values[i] != 1:
okay.add(address)
continue
expected = data['data_expected'].values[i]
actual = data['data_actual'].values[i]
r = MemError(address, hex(expected), hex(actual))
if address in errors:
assert errors[address] == r
else:
errors[address] = r
import pprint
print(len(errors))
pprint.pprint(errors)
from IPython import embed
embed()
#print("Error @ {} - {:x} != {:x}".format(addr, expect, actual))
print("Done!")
wb.close()