class Platform(XilinxPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9 / 50e6
# these resources conflict with daughterboard resources
# so they are only used if the daughterboard is not present
core_resources = [
("user_led", 0, Pins("E6"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("K5"), IOStandard("LVCMOS33")),
]
def __init__(self, toolchain="vivado", with_daughterboard=False):
device = "xc7a35tftg256-1"
io = _io
connectors = _connectors
if with_daughterboard:
from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard
daughterboard = QMTechDaughterboard(IOStandard("LVCMOS33"))
io += daughterboard.io
connectors += daughterboard.connectors
else:
io += self.core_resources
XilinxPlatform.__init__(self,
device,
io,
connectors,
toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command(
"set_property INTERNAL_VREF 0.675 [get_iobanks 15]")
self.add_platform_command("set_property CFGBVS VCCO [current_design]")
self.add_platform_command(
"set_property CONFIG_VOLTAGE 3.3 [current_design]")
self.toolchain.symbiflow_device = device
def create_programmer(self):
bscan_spi = "bscan_spi_xc7a35t.bit"
return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
from litex.build.xilinx import symbiflow
self.add_period_constraint(self.lookup_request("clk50", loose=True),
1e9 / 50e6)
def __init__(self, toolchain="vivado", with_daughterboard=False):
device = "xc7a35tftg256-1"
io = _io
connectors = _connectors
if with_daughterboard:
from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard
daughterboard = QMTechDaughterboard(IOStandard("LVCMOS33"))
io += daughterboard.io
connectors += daughterboard.connectors
else:
io += self.core_resources
XilinxPlatform.__init__(self,
device,
io,
connectors,
toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command(
"set_property INTERNAL_VREF 0.675 [get_iobanks 15]")
self.add_platform_command("set_property CFGBVS VCCO [current_design]")
self.add_platform_command(
"set_property CONFIG_VOLTAGE 3.3 [current_design]")
self.toolchain.symbiflow_device = device
def _add_extentions(self, platform):
platform.add_extension([
("serial_wb", 1, Subsignal("rx", Pins("E9")),
Subsignal("tx", Pins("D9")), IOStandard("LVCMOS33")),
("debug_pins", 1, Subsignal("dbg1", Pins("B6")),
Subsignal("dbg2", Pins("C9")), Subsignal("dbg3", Pins("D10")),
IOStandard("LVCMOS33")),
(
"adc_data",
0,
Subsignal("da0", Pins("A4")), # INVERTED
Subsignal("da1", Pins("B5")), # INVERTED
Subsignal("db0", Pins("E4")), # INVERTED
Subsignal("db1", Pins("C3")), # INVERTED
Subsignal("fclk", Pins("A3")), # INVERTED
Subsignal("sysref", Pins("E5")), # INVERTED
IOStandard("LVDS")),
("adc_spi", 1, Subsignal("clk", Pins("C6")),
Subsignal("mosi", Pins("C7")), Subsignal("cs_n", Pins("E8")),
Subsignal("miso", Pins("D8")), IOStandard("LVCMOS33")),
("adc_ctrl", 0, Subsignal("en_pwr", Pins("A7")),
Subsignal("pdn", Pins("C8")), Subsignal("reset", Pins("B8")),
IOStandard("LVCMOS33")),
(
"adc_clks",
0,
Subsignal("dclk", Pins("C4")), # INVERTED...
Subsignal("sclk", Pins("F4")), # INVERTED
IOStandard("LVDS")),
("hyperram", 0, Subsignal("clk", Pins("B13")),
Subsignal("rst_n", Pins("C15")),
Subsignal("dq", Pins("D11 C12 E11 B12 E12 C13 D13 D12")),
Subsignal("cs_n", Pins("B15")), Subsignal("rwds", Pins("B20")),
IOStandard("LVCMOS33")),
])
def diff_clk(name, id, pin_n, pin_p, iostandard=None, freq_hz=None):
_r = [name, id, Subsignal("n", Pins(pin_n)), Subsignal("p", Pins(pin_p))]
if iostandard is not None:
_r += [IOStandard(iostandard)]
if freq_hz is not None:
_r += [PlatformInfo({"freq_hz": freq_hz})]
return tuple(_r)
def __init__(self, sys_clk_freq, **kwargs):
platform = Platform()
kwargs["cpu_type"] = None
kwargs["with_uart"] = False
kwargs["with_timer"] = False
kwargs["with_ctrl"] = True
# We don't have RAM or ROM
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
kwargs["csr_data_width"] = 32
SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
self.submodules.crg = CRG(platform, sys_clk_freq)
# SPI to wishbone bridge
spi_pads = platform.request("spi_slave")
self.submodules.bridge = SPIBridge(spi_pads)
self.bus.add_master(name="bridge", master=self.bridge.wishbone)
ps2_ext = [(
"ps2",
0,
Subsignal("dat", Pins("25"), IOStandard("LVCMOS33")), # PB1
Subsignal("clk", Pins("26"), IOStandard("LVCMOS33")), # PB0
)]
platform.add_extension(ps2_ext)
ps2 = platform.request("ps2")
self.submodules.ps2 = PS2Controller(ps2.dat, ps2.clk, sys_clk_freq)
self.add_csr("ps2")
if hasattr(self.cpu, "interrupt"):
self.add_interrupt("ps2")
irq = platform.request("irq")
self.sync += irq.eq(self.ps2.ev.irq)
# Suppress yosys output
assert hasattr(self.platform.toolchain, "build_template")
if self.platform.toolchain.build_template[0].startswith("yosys "):
self.platform.toolchain.build_template[0] =\
self.platform.toolchain.build_template[0].replace("yosys ", "yosys -q ")
def build_platform():
# by default, LiteX uses Lattice's closed-source toolchain.
# ULX3S has 4 FPGA size variants, set 'device' accordingly
plat = Platform(toolchain="trellis", device="LFE5U-12F")
# these IOs should probably be defined by default in litex, but since it's not we have to do it
plat.add_extension([
("user_button", 0, Pins("D6"),
IOStandard("LVCMOS33")), # BTN_PWRn (inverted logic)
("user_button", 1, Pins("R1"), IOStandard("LVCMOS33")), # FIRE1
("user_button", 2, Pins("T1"), IOStandard("LVCMOS33")), # FIRE2
("user_button", 3, Pins("R18"), IOStandard("LVCMOS33")), # UP
("user_button", 4, Pins("V1"), IOStandard("LVCMOS33")), # DOWN
("user_button", 5, Pins("U1"), IOStandard("LVCMOS33")), # LEFT
("user_button", 6, Pins("H16"), IOStandard("LVCMOS33")), # RIGHT
])
return plat
#
# Copyright (c) 2020 David Shah <*****@*****.**>
# Copyright (c) 2020 Florent Kermarrec <*****@*****.**>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# clk
(
"clk300",
0,
Subsignal("n", Pins("AY38"), IOStandard("DIFF_SSTL12")),
Subsignal("p", Pins("AY37"), IOStandard("DIFF_SSTL12")),
),
# led
("user_led", 0, Pins("BC21"), IOStandard("LVCMOS12")),
("user_led", 1, Pins("BB21"), IOStandard("LVCMOS12")),
("user_led", 2, Pins("BA20"), IOStandard("LVCMOS12")),
# serial
(
"serial",
0,
Subsignal("rx", Pins("BF18"), IOStandard("LVCMOS12")),
Subsignal("tx", Pins("BB20"), IOStandard("LVCMOS12")),
),
#
# Copyright (c) 2021 Sergiu Mosanu <*****@*****.**>
#
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs -----------------------------------------------------------------------------------------------
_io = [
# 100MHz Clk / Rst
(
"sysclk",
0,
Subsignal("n", Pins("BJ44"), IOStandard("DIFF_SSTL12")),
Subsignal("p", Pins("BJ43"), IOStandard("DIFF_SSTL12")),
),
(
"sysclk",
1,
Subsignal("n", Pins("BJ6"), IOStandard("DIFF_SSTL12")),
Subsignal("p", Pins("BH6"), IOStandard("DIFF_SSTL12")),
),
("cpu_reset", 0, Pins("L30"), IOStandard("LVCMOS18")),
# Leds
("gpio_led", 0, Pins("C32"), IOStandard("LVCMOS18")),
("gpio_led", 1, Pins("D32"), IOStandard("LVCMOS18")),
("gpio_led", 2, Pins("D31"), IOStandard("LVCMOS18")),
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018 William D. Jones <*****@*****.**>
# Copyright (c) 2020 Staf Verhaegen <*****@*****.**>
# Copyright (c) 2021 Michael T. Mayers <*****@*****.**>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk50", 0, Pins("N14"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("M1"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("A14"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("A13"), IOStandard("LVCMOS33")),
# Serial
(
"serial",
0,
Subsignal("tx", Pins("N11")), # BDBUS1
Subsignal("rx", Pins("E11")), # BDBUS0
IOStandard("LVCMOS33")),
# SRAM
"""Small SoC definition for zephyr to run on"""
import logging
import os
from litescope import LiteScopeAnalyzer
from litex.build.generic_platform import IOStandard, Pins, Subsignal
from litex.soc.cores.gpio import GPIOIn, GPIOOut
from litex_boards.targets.c10lprefkit import BaseSoC
pmod1_uart_ios = [(
"pmod1_uart",
0,
Subsignal("rx", Pins("P4")),
Subsignal("tx", Pins("P6")),
IOStandard("3.3-V LVTTL"),
)]
class ZephyrSoC(BaseSoC):
def __init__(self, sys_clk_freq, output_dir, *args, **kwargs):
self._logger = logging.getLogger("ZephyrSoC")
super().__init__(
cpu_type="vexriscv",
cpu_variant="full",
csr_data_width=8,
integrated_rom_size=0x8000,
*args,
**kwargs,
) # TODO: Test if we actually need "full" for ecall
# QSFP GTY reference clock
diff_clk("qsfp0_refclk156m", 0, "m10", "m11"),
diff_clk("qsfp0_refclk1", 0, "k10", "k11"),
diff_clk("qsfp1_refclk156m", 0, "T10", "T11"),
diff_clk("qsfp1_refclk1", 0, "P10", "P11"),
# QSFP GTY reference clock select
# fs[1:0] 01 10
# qsfpn_refclk1 156 MHz 161 MHz
(
"qsfp_fs",
0,
Subsignal("fs", Pins("AT20 AU22")),
Subsignal("rst", Pins("AT22")),
IOStandard("LVCMOS12"),
),
(
"qsfp_fs",
1,
Subsignal("fs", Pins("AR22 AU20")),
Subsignal("rst", Pins("AR21")),
IOStandard("LVCMOS12"),
),
# QSFP sideband
(
"qsfp_ls",
0,
Subsignal("MODSELL", Pins("BE16")),
Subsignal("RESETL", Pins("BE17")),
# This file is Copyright (c) 2019 Michael Betz <*****@*****.**>
# License: BSD
from litex.build.generic_platform import Pins, IOStandard, Subsignal
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
_io = [
# 8 LEDs above DIP switches (Bank 33)
("user_led", 0, Pins("T22"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("T21"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("U22"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("U21"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("V22"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("W22"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("U19"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("U14"), IOStandard("LVCMOS33")),
# UG-2832HSWEG04 (ssd1306)
(
"zed_oled",
0,
Subsignal("clk", Pins("AB12")),
Subsignal("mosi", Pins("AA12")),
# OLED does not have a MISO pin :(
Subsignal("reset_n", Pins("U9")),
Subsignal("dc", Pins("U10")),
Subsignal("vbat_n", Pins("U11")),
Subsignal("vdd_n", Pins("U12")),
IOStandard("LVCMOS33")),
def __init__(self,
variant="a7-35",
toolchain="vivado",
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
ident_version=True,
analyzer_csv="analyzer.csv",
**kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
kwargs["integrated_rom_size"] = 0x10000 if with_etherbone else 0x8000
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Arty A7",
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
_dws1000_ardu_io = [
("dw1000_spi", 0,
Subsignal("clk", Pins("ck_io:ck_io13")),
Subsignal("mosi", Pins("ck_io:ck_io11")),
Subsignal("cs_n", Pins("ck_io:ck_io10")),
Subsignal("miso", Pins("ck_io:ck_io12")),
Subsignal("pha", Pins("ck_io:ck_io0"), Misc("PULLDOWN True")),
Subsignal("pol", Pins("ck_io:ck_io1"), Misc("PULLDOWN True")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
("dw1000_led", 0, Pins("ck_io:ck_io3"), IOStandard("LVCMOS33")), # TX LED on the DWS1000 module
("dw1000_led", 1, Pins("ck_io:ck_io4"), IOStandard("LVCMOS33")), # RX LED on the DWS1000 module
("dw1000_info", 0,
Subsignal("exton", Pins("ck_io:ck_a0")),
Subsignal("wakeup", Pins("ck_io:ck_io9")),
Subsignal("irq", Pins("ck_io:ck_io8")),
IOStandard("LVCMOS33"),
),
("dw1000_rstn", 0,
Pins("ck_io:ck_io7"),
IOStandard("LVCMOS33"),
),
]
platform.add_extension(_dws1000_ardu_io)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("dw1000_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
self.submodules.dw1000_rstn = GPIOTristate(platform.request("dw1000_rstn", 0))
self.add_csr("dw1000_rstn")
self.submodules.dw1000_info = GPIOIn(platform.request("dw1000_info"))
self.add_csr("dw1000_info")
# SPI with LiteScope
self.add_spi_master()
print(dir(self.cpu.ibus))
analyzer_signals = [
self.spi_master._control.storage,
self.spi_master._status.status,
self.spi_master._cs.storage,
self.spi_master.mosi,
self.spi_master.miso,
self.spi_master.pads.clk,
self.spi_master.pads.cs_n,
self.spi_master.pads.mosi,
self.spi_master.pads.miso,
self.dw1000_rstn._oe.storage,
self.dw1000_rstn._in.status,
self.dw1000_rstn._out.storage,
self.dw1000_info._in.status,
self.cpu.ibus.adr,
self.cpu.ibus.stb,
self.cpu.ibus.dat_w,
self.cpu.ibus.dat_r
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth=1024,
clock_domain="sys",
csr_csv=analyzer_csv
)
self.add_csr("analyzer")
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 Hans Baier <*****@*****.**>
#
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
from litex.build.generic_platform import Pins, IOStandard, Subsignal, Misc
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk
("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")),
# Leds
("user_led", 0, Pins("AF10"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("AD10"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("AE11"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("AD7"), IOStandard("3.3-V LVTTL")),
# Buttons
("user_btn", 0, Pins("AE9"), IOStandard("3.3-V LVTTL")),
("user_btn", 1, Pins("AE12"), IOStandard("3.3-V LVTTL")),
("user_btn", 2, Pins("AD9"), IOStandard("3.3-V LVTTL")),
("user_btn", 3, Pins("AD11"), IOStandard("3.3-V LVTTL")),
# Switches
("user_sw", 0, Pins("W25"), IOStandard("3.3-V LVTTL")),
from valentyusb.usbcore.cpu.eptri import TriEndpointInterface
from valentyusb.usbcore import io as usbio
from rtl.crg import _CRG
from rtl.lcdif import LCDIF
from rtl.messible import Messible
from rtl.reboot import Reboot
from rtl.spi_ram import SpiRamQuad
from rtl.spi_ram_dual import SpiRamDualQuad
from rtl.version import Version
from rtl.picorvspi import PicoRVSpi
import lxsocdoc
_io = [
("clk8", 0, Pins("U18"), IOStandard("LVCMOS33")),
("programn", 0, Pins("R1"), IOStandard("LVCMOS33")),
(
"serial",
0,
Subsignal("rx", Pins("U2"), IOStandard("LVCMOS33"),
Misc("PULLMODE=UP")),
Subsignal("tx", Pins("U1"), IOStandard("LVCMOS33")),
),
("led", 0, Pins("E3 D3 C3 C4 C2 B1 B20 B19 A18 K20 K19"),
IOStandard("LVCMOS33")), # Anodes
("led", 1, Pins("P19 L18 K18"),
IOStandard("LVCMOS33")), # Cathodes via FET
("usb", 0, Subsignal("d_p", Pins("F3")), Subsignal("d_n", Pins("G3")),
Subsignal("pullup",
Pins("E4")), Subsignal("vbusdet",
# SPDX-License-Identifier: BSD-2-Clause
# Note: This platform should also be applicable to the Alveo U200, VCU1525, BCU1525 and other
# 1525 variants.
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs (initially auto-generated by extract_xdc_pins.py) ---------------------------------------------
_io = [
# clk / rst
(
"clk300",
0,
Subsignal("n", Pins("AY38"), IOStandard("DIFF_SSTL12")),
Subsignal("p", Pins("AY37"), IOStandard("DIFF_SSTL12")),
),
(
"clk300",
1,
Subsignal("n", Pins("AW19"), IOStandard("DIFF_SSTL12")),
Subsignal("p", Pins("AW20"), IOStandard("DIFF_SSTL12")),
),
(
"clk300",
2,
Subsignal("n", Pins("E32"), IOStandard("DIFF_SSTL12")),
Subsignal("p", Pins("F32"), IOStandard("DIFF_SSTL12")),
),
(
#
# Copyright (c) 2021 Sergiu Mosanu <*****@*****.**>
#
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs -----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
(
"sysclk",
0,
Subsignal("n", Pins("BJ44"), IOStandard("LVDS")),
Subsignal("p", Pins("BJ43"), IOStandard("LVDS")),
),
(
"sysclk",
1,
Subsignal("n", Pins("BJ6"), IOStandard("LVDS")),
Subsignal("p", Pins("BH6"), IOStandard("LVDS")),
),
("cpu_reset", 0, Pins("L30"), IOStandard("LVCMOS18")),
# Leds
("gpio_led", 0, Pins("C32"), IOStandard("LVCMOS18")),
("gpio_led", 1, Pins("D32"), IOStandard("LVCMOS18")),
("gpio_led", 2, Pins("D31"), IOStandard("LVCMOS18")),
from sys import argv, exit
from litex.soc.integration.builder import Builder
from litex import RemoteClient
from os import system
from struct import pack, unpack
# from numpy import *
# from matplotlib.pyplot import *
# from scipy.signal import *
from migen import *
from litex.build.generic_platform import Subsignal, Pins, IOStandard, Misc
ltc_pads = [
("LTC_SPI", 0, Subsignal("cs_n", Pins("LPC:LA14_P")),
Subsignal("miso", Pins("LPC:LA14_N"),
Misc("PULLUP TRUE")), Subsignal("mosi", Pins("LPC:LA27_P")),
Subsignal("clk", Pins("LPC:LA27_N")), IOStandard("LVCMOS25")),
(
"LTC_OUT",
0, # Bank 0
Subsignal("a_p", Pins("LPC:LA03_P")),
Subsignal("a_n", Pins("LPC:LA03_N")),
Subsignal("b_p", Pins("LPC:LA08_P")),
Subsignal("b_n", Pins("LPC:LA08_N")),
IOStandard("LVDS_25"),
Misc("DIFF_TERM=TRUE")),
(
"LTC_OUT",
1, # Bank 0
Subsignal("a_p", Pins("LPC:LA12_P")),
Subsignal("a_n", Pins("LPC:LA12_N")),
Subsignal("b_p", Pins("LPC:LA16_P")),
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018 William D. Jones <*****@*****.**>
# Copyright (c) 2020 Staf Verhaegen <*****@*****.**>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk100", 0, Pins("R2"), IOStandard("SSTL135")),
("cpu_reset", 0, Pins("C18"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("E18"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("F13"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("E13"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("H15"), IOStandard("LVCMOS33")),
("rgb_led", 0, Subsignal("r", Pins("J15")), Subsignal("g", Pins("G17")),
Subsignal("b", Pins("F15")), IOStandard("LVCMOS33")),
("rgb_led", 1, Subsignal("r", Pins("E15")), Subsignal("g", Pins("F18")),
Subsignal("b", Pins("E14")), IOStandard("LVCMOS33")),
# Switches
("user_sw", 0, Pins("H14"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("H18"), IOStandard("LVCMOS33")),
def __init__(self, flash_offset, sys_clk_freq, **kwargs):
"""Create a basic SoC for iCEBreaker.
Returns:
Newly-constructed SoC
"""
platform = Platform()
# Use SERV CPU buy default
if "cpu_type" not in kwargs:
kwargs["cpu_type"] = "serv"
kwargs["cpu_variant"] = "standard"
else:
if kwargs["cpu_type"] == "vexriscv" and ("cpu_variant"
not in kwargs):
kwargs["cpu_variant"] = "minimal"
# Force the SRAM size to 0, because we add our own SRAM with SPRAM
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
# Set CPU reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + flash_offset
# SoCCore
SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
# Use this as CPU RAM.
spram_size = 128 * 1024
self.submodules.spram = Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus,
spram_size)
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spiflash_size = 16 * 1024 * 1024
self.submodules.spiflash = SpiFlash(platform.request("spiflash4x"),
dummy=6,
endianness="little")
self.add_csr("spiflash")
# SPI flash cache
l2_cache_size = 8192
if l2_cache_size != 0:
self.submodules.l2_cache = wishbone.Cache(
cachesize=l2_cache_size // 4,
master=wishbone.Interface(32),
slave=self.spiflash.bus,
)
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.l2_cache.master,
size=spiflash_size)
else:
self.register_mem("spiflash",
self.mem_map["spiflash"],
self.spiflash.bus,
size=spiflash_size)
# Add ROM linker region
self.add_memory_region("rom",
self.mem_map["spiflash"] + flash_offset,
spiflash_size - flash_offset,
type="cached+linker")
# User button as reset
reset_btn = platform.request("user_btn_n")
self.comb += self.crg.reset.eq(~reset_btn)
# Clock peripheral holds the actual sys_clk frequency
self.submodules.clock = ClockPeripheral(sys_clk_freq)
self.add_csr("clock")
# GPIO peripheral
pin_names = ["PMOD1A:%d" % i for i in range(8)] +\
["PMOD1B:%d" % i for i in range(8)] +\
["PMOD2:%d" % i for i in range(8)]
gpio_extension = [("gpio", i, Pins(name), IOStandard("LVCMOS33"))
for i, name in enumerate(pin_names)]
platform.add_extension(gpio_extension)
gpio = []
for i in range(len(pin_names)):
gpio.append(platform.request("gpio"))
self.submodules.gpio = GPIOPeripheral(gpio + [
platform.request("user_ledr_n"),
platform.request("user_ledg_n"),
])
self.add_csr("gpio")
# Suppress synthesis output
assert hasattr(self.platform.toolchain, "build_template")
if self.platform.toolchain.build_template[0].startswith("yosys "):
self.platform.toolchain.build_template[0] = \
self.platform.toolchain.build_template[0].replace("yosys ", "yosys -q ")
# This file is Copyright (c) 2019 Michael Betz <*****@*****.**>
# License: BSD
from litex.build.generic_platform import Pins, IOStandard, Subsignal
from litex.build.xilinx import XilinxPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk125", 0, Pins("H16"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("R14"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("P14"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("N16"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("M14"), IOStandard("LVCMOS33")),
(
"rgb_led",
0,
Subsignal("r", Pins("N15")),
Subsignal("g", Pins("G17")),
Subsignal("b", Pins("L15")),
IOStandard("LVCMOS33"),
),
(
"rgb_led",
1,
Subsignal("r", Pins("M15")),
Subsignal("g", Pins("L14")),
from gateware import spi_flash
from targets.utils import csr_map_update
from platforms import icebreaker
# Alternate serial port, using the second 6-pin PMOD port. Follows Digilent
# PMOD Specification Type 4, so e.g. PMOD USBUART can be used.
pmod_serial = [
(
"serial",
0,
Subsignal("rx", Pins("PMOD:6")),
Subsignal("tx", Pins("PMOD:5")),
Subsignal("rts", Pins("PMOD:4")),
Subsignal("cts", Pins("PMOD:7")),
IOStandard("LVCMOS33"),
),
]
class _CRG(Module):
def __init__(self, platform):
clk12 = platform.request("clk12")
self.clock_domains.cd_sys = ClockDomain()
self.reset = Signal()
# FIXME: Use PLL, increase system clock to 32 MHz, pending nextpnr
# fixes.
self.comb += self.cd_sys.clk.eq(clk12)
# Generated by gen_marble.py (git 4a42959)
# https://github.com/yetifrisstlama/litex_test_project/blob/4a42959/xdc/gen_marble.py
# Pin numbers extracted from a .xdc file, which was auto-generated from
# the Kicad Schematic.
from litex.build.generic_platform import Pins, Subsignal, IOStandard
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
(
"eth",
0,
Subsignal("rst_n", Pins("B9"), IOStandard("LVCMOS25")),
Subsignal("rx_ctl", Pins("J11"), IOStandard("LVCMOS25")),
Subsignal("rx_data", Pins("J10 J8 H8 H9"), IOStandard("LVCMOS25")),
Subsignal("tx_ctl", Pins("C9"), IOStandard("LVCMOS25")),
Subsignal("tx_data", Pins("H11 H12 D8 D9"), IOStandard("LVCMOS25")),
),
(
"eth_clocks",
0,
Subsignal("tx", Pins("F10"), IOStandard("LVCMOS25")),
Subsignal("rx", Pins("E11"), IOStandard("LVCMOS25")),
),
# Tunable VCXO. Warning: Non clock-capable pin
("clk20", 0, Pins("W11"), IOStandard("LVCMOS15")),
# Main system clock. White rabbit compatible
(
# programs.
LX_DEPENDENCIES = ["riscv", "vivado"]
# Import lxbuildenv to integrate the deps/ directory
import lxbuildenv
# Disable pylint's E1101, which breaks completely on migen
#pylint:disable=E1101
from migen import *
from litex.build.xilinx import VivadoProgrammer, XilinxPlatform
from litex.build.generic_platform import Pins, IOStandard
from litex.soc.integration.builder import Builder
_io = [
("clk100", 0, Pins("J19"), IOStandard("LVCMOS33")),
("led", 0, Pins("J20"), IOStandard("LVCMOS33")),
]
class Platform(XilinxPlatform):
def __init__(self, toolchain="vivado", programmer="vivado", part="35"):
part = "xc7a" + part + "t-fgg484-2"
XilinxPlatform.__init__(self, part, _io, toolchain=toolchain)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
class Blink(Module):
def __init__(self, platform, **kwargs):
from gateware.ticktimer import TickTimer
from gateware.spi_ice40 import *
import litex.soc.doc as lxsocdoc
# Ish. It's actually slightly smaller, but this is divisible by 4096 (erase sector size).
GATEWARE_SIZE = 0x1a000
# 1 MB (8 Mb)
SPI_FLASH_SIZE = 1 * 1024 * 1024
io_pvt = [
("serial", 0,
Subsignal("rx", Pins("48")), # MON0
Subsignal("tx", Pins("3")), # MON1
IOStandard("LVCMOS33")
),
# serial is muxed in with these key monitor pins
# ("up5k_keycol0", 0, Pins("48"), IOStandard("LVCMOS33")),
# ("up5k_keycol1", 0, Pins("3"), IOStandard("LVCMOS33")), # this is marking "high"
("up5k_keyrow0", 0, Pins("4"), IOStandard("LVCMOS33")),
("up5k_keyrow1", 0, Pins("2"), IOStandard("LVCMOS33")),
("spiflash", 0,
Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS18")),
Subsignal("clk", Pins("15"), IOStandard("LVCMOS18")),
Subsignal("cipo", Pins("17"), IOStandard("LVCMOS18")),
Subsignal("copi", Pins("14"), IOStandard("LVCMOS18")),
Subsignal("wp", Pins("18"), IOStandard("LVCMOS18")),
Subsignal("hold", Pins("13"), IOStandard("LVCMOS18")),
),
from litex.soc.integration.soc_core import SoCCore
from litex.soc.cores.uart import UARTWishboneBridge
from litex.build.generic_platform import Subsignal
from litex.build.generic_platform import Pins
from litex.build.generic_platform import IOStandard
from litex.soc.cores.clock import *
from litescope import LiteScopeIO, LiteScopeAnalyzer
#
# Use the 8 input on the dual PMOD connector B as input
# Those are the fast and not so well protected pins.
_serdes_io = [(
"serdes_io",
0,
Subsignal("d0", Pins("E15"), IOStandard("LVCMOS33")),
Subsignal("d1", Pins("E16"), IOStandard("LVCMOS33")),
Subsignal("d2", Pins("D15"), IOStandard("LVCMOS33")),
Subsignal("d3", Pins("C15"), IOStandard("LVCMOS33")),
Subsignal("d4", Pins("J17"), IOStandard("LVCMOS33")),
Subsignal("d5", Pins("J18"), IOStandard("LVCMOS33")),
Subsignal("d6", Pins("K15"), IOStandard("LVCMOS33")),
Subsignal("d7", Pins("J15"), IOStandard("LVCMOS33")),
)]
class SerdesInputSignal(Module):
def __init__(self, pad):
self.signals = Signal(8)
#
def __init__(self,
sys_clk_freq=int(75e6),
with_spi_flash=False,
with_ethernet=False,
with_etherbone=False,
with_video_terminal=False,
with_lcd=False,
with_ws2812=False,
**kwargs):
platform = litex_acorn_baseboard.Platform(toolchain="trellis")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on LiteX M2 Baseboard",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_video_pll=with_video_terminal)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.modules import W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x",
module=W25Q128JV(Codes.READ_1_1_4),
with_master=True)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"),
rx_delay=0e-9)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Video ------------------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoHDMIPHY(platform.request("hdmi"),
clock_domain="hdmi",
pn_swap=["g", "b"])
self.add_video_terminal(phy=self.videophy,
timings="800x600@60Hz",
clock_domain="hdmi")
# LCD --------------------------------------------------------------------------------------
if with_lcd:
self.submodules.i2c = I2CMaster(platform.request("lcd"))
# M2 --------------------------------------------------------------------------------------
self.comb += platform.request("m2_devslp").eq(0) # Enable SATA M2.
# WS2812 ----------------------------------------------------------------------------------
if with_ws2812:
from litex.build.generic_platform import Pins, IOStandard
from litex.soc.integration.soc import SoCRegion
from litex.soc.cores.led import WS2812
platform.add_extension([("ws2812", 0, Pins("pmod1:0"),
IOStandard("LVCMOS33"))])
self.submodules.ws2812 = WS2812(platform.request("ws2812"),
nleds=64,
sys_clk_freq=sys_clk_freq)
self.bus.add_slave(name="ws2812",
slave=self.ws2812.bus,
region=SoCRegion(
origin=0x2000_0000,
size=64 * 4,
))
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 Hans Baier <*****@*****.**>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk50", 0, Pins("N11"), IOStandard("LVCMOS33")),
# The core board does not have a USB serial on it,
# so you will have to attach an USB to serial adapter
# on these pins
("gpio_serial", 0, Subsignal("tx", Pins("J2:7")),
Subsignal("rx", Pins("J2:8")), IOStandard("LVCMOS33")),
# SPIFlash
# MT25QL128
(
"spiflash4x",
0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("L12")),
Subsignal("clk", Pins("E8")),
Subsignal("dq", Pins("J13", "J14", "K15", "K16")),
IOStandard("LVCMOS33")),
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018 William D. Jones <*****@*****.**>
# Copyright (c) 2020 Staf Verhaegen <*****@*****.**>
# Copyright (c) 2021 Michael T. Mayers <*****@*****.**>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk12", 0, Pins("L17"), IOStandard("LVCMOS33")),
# Buttons
("cpu_reset", 0, Pins("A18"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("B18"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("A17"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("C16"), IOStandard("LVCMOS33")),
(
"rgb_led",
0,
Subsignal("r", Pins("C17")),
Subsignal("g", Pins("B16")),
Subsignal("b", Pins("B17")),
IOStandard("LVCMOS33"),
# Support for the Fomu
# More information can be found here https://github.com/im-tomu/foboot.git
from litex.build.lattice.platform import LatticePlatform
from litex.build.generic_platform import Pins, IOStandard, Misc, Subsignal
_io_evt = [("serial", 0, Subsignal("rx", Pins("21")),
Subsignal("tx", Pins("13"),
Misc("PULLUP")), IOStandard("LVCMOS33")),
("usb", 0, Subsignal("d_p",
Pins("34")), Subsignal("d_n", Pins("37")),
Subsignal("pullup", Pins("35")), Subsignal("pulldown", Pins("36")),
IOStandard("LVCMOS33")),
(
"touch",
0,
Subsignal("t1", Pins("48"), IOStandard("LVCMOS33")),
Subsignal("t2", Pins("47"), IOStandard("LVCMOS33")),
Subsignal("t3", Pins("46"), IOStandard("LVCMOS33")),
Subsignal("t4", Pins("45"), IOStandard("LVCMOS33")),
),
(
"pmoda",
0,
Subsignal("p1", Pins("28"), IOStandard("LVCMOS33")),
Subsignal("p2", Pins("27"), IOStandard("LVCMOS33")),
Subsignal("p3", Pins("26"), IOStandard("LVCMOS33")),
Subsignal("p4", Pins("23"), IOStandard("LVCMOS33")),
),
(
"pmodb",
