def finalize(self, fragment, *args, **kwargs):
if self.finalized:
raise ConstraintError("Already finalized")
# if none exists, create a default clock domain and drive it
if not fragment.clock_domains:
if not hasattr(self, "default_clk_name"):
raise NotImplementedError(
"No default clock and no clock domain defined")
crg = CRG(self.request(self.default_clk_name))
fragment += crg.get_fragment()
self.do_finalize(fragment, *args, **kwargs)
self.finalized = True
def __init__(self, bios_flash_offset, sys_clk_freq=int(16e6), with_led_chaser=True, **kwargs):
platform = tinyfpga_bx.Platform()
# Disable Integrated ROM since too large for iCE40.
kwargs["integrated_rom_size"] = 0
# Set CPU variant / reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on TinyFPGA BX",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("clk16"))
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import AT25SF081
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="1x", module=AT25SF081(Codes.READ_1_1_1), with_master=False)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region("rom", SoCRegion(
origin = self.mem_map["spiflash"] + bios_flash_offset,
size = 32*kB,
linker = True)
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self,
platform,
with_ethernet=False,
with_led_chaser=True,
**kwargs):
sys_clk_freq = int(1e9 / platform.default_clk_period)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX Simple SoC",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# Leds -------------------------------------------------------------------------------------
try:
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
except:
pass
def __init__(self, bios_flash_offset, sys_clk_freq=int(16e6), **kwargs):
platform = tinyfpga_bx.Platform()
# Disable Integrated ROM since too large for iCE40.
kwargs["integrated_rom_size"] = 0
# Set CPU variant / reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on TinyFPGA BX",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("clk16"))
# SPI Flash --------------------------------------------------------------------------------
self.add_spi_flash(mode="1x", dummy_cycles=8)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region("rom", SoCRegion(
origin = self.mem_map["spiflash"] + bios_flash_offset,
size = 32*kB,
linker = True)
)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def __init__(self, platform, **kwargs):
SoCCore.__init__(self, platform,
clk_freq=int((1/(platform.default_clk_period))*1000000000),
integrated_rom_size=0x8000,
integrated_main_ram_size=16*1024,
with_uart=False,
**kwargs)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
def __init__(self, platform, core_config):
# # PHY --------------------------------------------------------------------------------------
# PHYCore.__init__(self, platform, core_config)
# SoC parameters ---------------------------------------------------------------------------
soc_args = {}
if "soc" in core_config:
soc_config = core_config["soc"]
for arg in soc_config:
if arg in ("csr_map", "interrupt_map", "mem_map"):
getattr(self, arg).update(soc_config[arg])
else:
soc_args[arg] = soc_config[arg]
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
clk_freq=core_config["clk_freq"],
**soc_args)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clock"),
platform.request("sys_reset"))
# PHY ----------------------------------------------------------------------------------
ethphy = LiteEthPHYModel(pads=platform.request("model_eth"))
self.submodules.ethphy = ethphy
self.add_csr("ethphy")
# MAC --------------------------------------------------------------------------------------
self.submodules.ethmac = LiteEthMAC(
phy=self.ethphy,
dw=32,
interface="wishbone",
endianness=core_config["endianness"])
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus)
self.add_memory_region("ethmac",
self.mem_map["ethmac"],
0x2000,
type="io")
self.add_csr("ethmac")
# Wishbone Interface -----------------------------------------------------------------------
class _WishboneBridge(Module):
def __init__(self, interface):
self.wishbone = interface
self.wishbone.data_width = 32
bridge = _WishboneBridge(self.platform.request("wishbone"))
self.submodules += bridge
self.add_wb_master(bridge.wishbone)
# Interrupt Interface ----------------------------------------------------------------------
self.comb += self.platform.request("interrupt_request").eq(
self.ethmac.ev.irq)
def __init__(self, platform, sys_clk_freq=int(10e6), **kwargs):
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("clk"))
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX Test SoC on OS-FPGA",
**kwargs)
def __init__(self,
platform,
clk_freq=int(166e6),
mac_address=0x10e2d5000000,
ip_address="192.168.1.50"):
sys_clk_freq = int((1 / (platform.default_clk_period)) * 1e9)
SoCCore.__init__(self,
platform,
clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="LiteEth Base Design",
with_timer=False)
# Serial Wishbone Bridge
serial_bridge = UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200)
self.submodules += serial_bridge
self.add_wb_master(serial_bridge.wishbone)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# Ethernet PHY and UDP/IP stack
self.submodules.ethphy = ethphy = LiteEthPHY(
clock_pads=platform.request("eth_clocks"),
pads=platform.request("eth"),
clk_freq=clk_freq)
self.add_csr("ethphy")
self.submodules.ethcore = ethcore = LiteEthUDPIPCore(
phy=ethphy,
mac_address=mac_address,
ip_address=ip_address,
clk_freq=clk_freq)
self.add_csr("ethcore")
if isinstance(platform.toolchain, XilinxVivadoToolchain):
self.crg.cd_sys.clk.attr.add("keep")
ethphy.crg.cd_eth_rx.clk.attr.add("keep")
ethphy.crg.cd_eth_tx.clk.attr.add("keep")
platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk,
1e9 / 125e6)
platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk,
1e9 / 125e6)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
ethphy.crg.cd_eth_rx.clk,
ethphy.crg.cd_eth_tx.clk)
def __init__(self, sys_clk_freq, with_ethernet=False, with_led_chaser=True, **kwargs):
platform = zcu102.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident="LiteX SoC on ZCU102",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(sys_clk_freq)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq
)
def __init__(self, platform, with_ethernet=False, **kwargs):
sys_clk_freq = int(1e9/platform.default_clk_period)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHY(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"),
clk_freq = self.clk_freq)
self.add_csr("ethphy")
self.add_ethernet(phy=self.ethphy)
def __init__(self, bios_flash_offset, **kwargs):
platform = tec0117.Platform()
sys_clk_freq = int(1e9 / platform.default_clk_period)
# SoC can have littel a bram, as a treat
kwargs["integrated_sram_size"] = 2048 * 2
kwargs["integrated_rom_size"] = 0
# Set CPU variant / reset address
kwargs[
"cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on TEC0117",
ident_version=True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(
platform.request(platform.default_clk_name),
~platform.request('rst'),
)
# SPI Flash --------------------------------------------------------------------------------
self.add_spi_flash(mode="1x", dummy_cycles=8)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region(
"rom",
SoCRegion(origin=self.mem_map["spiflash"] + bios_flash_offset,
size=8 * mB,
linker=True))
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)
self.add_csr("leds")
def __init__(self, platform):
sys_clk_freq = int((1e9 / platform.default_clk_period))
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(
self,
platform,
sys_clk_freq,
csr_data_width=32,
with_uart=True,
uart_name="bridge",
ident="Litescope example design",
ident_version=True,
)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request(platform.default_clk_name))
# Litescope IO -----------------------------------------------------------------------------
self.submodules.io = LiteScopeIO(8)
self.add_csr("io")
for i in range(8):
try:
self.comb += platform.request("user_led",
i).eq(self.io.output[i])
except:
pass
# Litescope Analyzer -----------------------------------------------------------------------
analyzer_groups = {}
# Counter group
counter = Signal(16, name_override="counter")
zero = Signal(name_override="zero")
self.sync += counter.eq(counter + 1)
self.comb += zero.eq(counter == 0)
analyzer_groups[0] = [
zero,
counter,
]
# Communication group
analyzer_groups[1] = [
platform.lookup_request("serial").tx,
platform.lookup_request("serial").rx,
self.bus.masters["uartbone"],
]
# FSM group
fsm = FSM(reset_state="STATE1")
self.submodules += fsm
fsm.act("STATE1", NextState("STATE2"))
fsm.act("STATE2", NextState("STATE1"))
analyzer_groups[2] = [
fsm,
]
# Analyzer
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_groups, 512, csr_csv="test/analyzer.csv")
self.add_csr("analyzer")