def flash(bios_flash_offset):
from litex.build.lattice.programmer import IceStormProgrammer
prog = IceStormProgrammer()
prog.flash(bios_flash_offset,
"soc_basesoc_icebreaker/software/bios/bios.bin")
prog.flash(0x00000000, "soc_basesoc_icebreaker/gateware/top.bin")
exit()
def flash(bios_flash_offset):
from litex.build.dfu import DFUProg
prog = IceStormProgrammer()
bitstream = open("build/" + target + "/gateware/" + target + ".bin", "rb")
bios = open("build/" + target + "/software/bios/bios.bin", "rb")
image = open("build/" + target + "/image.bin", "wb")
# Copy bitstream at 0x00000000
for i in range(0x00000000, 0x0020000):
b = bitstream.read(1)
if not b:
image.write(0xff.to_bytes(1, "big"))
else:
image.write(b)
# Copy bios at 0x00020000
for i in range(0x00000000, 0x00010000):
b = bios.read(1)
if not b:
image.write(0xff.to_bytes(1, "big"))
else:
image.write(b)
bitstream.close()
bios.close()
image.close()
print("Flashing bitstream (+bios)")
prog.flash(0x0, "build/" + target + "/image.bin")
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--sys-clk-freq", type=float, default=48e6, help="Select system clock frequency")
parser.add_argument("--document-only", action="store_true", help="Do not build a soc. Only generate documentation.")
parser.add_argument("--flash", action="store_true", help="Load bitstream")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
# Create the SOC
soc = BaseSoC(sys_clk_freq=int(args.sys_clk_freq), **soc_core_argdict(args))
# Configure command line parameter defaults
# Don't build software -- we don't include it since we just jump to SPI flash.
builder_kwargs = builder_argdict(args)
builder_kwargs["compile_software"] = False
if args.document_only:
builder_kwargs["compile_gateware"] = False
if builder_kwargs["csr_svd"] is None:
builder_kwargs["csr_svd"] = "../litex-pac/soc.svd"
# Create and run the builder
builder = Builder(soc, **builder_kwargs)
builder.build()
# If requested load the resulting bitstream onto the iCEBreaker
if args.flash:
IceStormProgrammer().flash(0x00000000, "build/icebreaker/gateware/icebreaker.bin")
def main():
parser = argparse.ArgumentParser(description="do the thing")
#parser.add_argument("--load", action="store_true", help="load bitstream")
parser.add_argument("--flash", action="store_true", help="flash bitstream")
parser.add_argument("--sim", action="store_true", help="simulate")
parser.add_argument("--threads", default=1, help="simulate")
parser.add_argument("--trace", action="store_true", help="Enable VCD tracing")
parser.add_argument("--trace-start", default=0, help="Cycle to start VCD tracing")
parser.add_argument("--trace-end", default=-1, help="Cycle to end VCD tracing")
parser.add_argument("--opt-level", default="O3", help="Compilation optimization level")
parser.add_argument("--sdram-init", default=None, help="SDRAM init file")
args = parser.parse_args()
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
build_kwargs = {}
if args.sim:
build_kwargs["threads"] = args.threads
build_kwargs["sim_config"] = sim_config
build_kwargs["opt_level"] = args.opt_level
build_kwargs["trace"] = args.trace
build_kwargs["trace_start"] = int(args.trace_start)
build_kwargs["trace_end"] = int(args.trace_end)
soc = N64SoC(
simulate=args.sim,
sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, "little"),
)
builder = Builder(soc, output_dir="build", csr_csv="scripts/csr.csv")
builder.build(run=not (args.sim or args.flash), **build_kwargs)
if args.flash:
from litex.build.lattice.programmer import IceStormProgrammer
prog = IceStormProgrammer()
#prog.flash(4194304, "sm64_swapped_half.n64")
prog.flash(bios_flash_offset, "build/software/bios/bios.bin")
prog.flash(0x00000000, "build/gateware/litex_platform_n64.bin")
if args.sim:
builder.build(build=False, **build_kwargs)
def main():
parser = argparse.ArgumentParser(
description="LiteICLink SerWB bench on iCEBreaker")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load",
action="store_true",
help="Load bitstream (to SRAM)")
parser.add_argument("--loopback",
action="store_true",
help="Loopback SerWB in FPGA (no IOs)")
args = parser.parse_args()
platform = icebreaker.Platform()
platform.add_extension(icebreaker.break_off_pmod)
platform.add_extension(serwb_io)
soc = SerWBTestSoC(platform)
builder = Builder(soc, csr_csv="csr.csv")
builder.build(run=args.build)
if args.load:
from litex.build.lattice.programmer import IceStormProgrammer
prog = IceStormProgrammer()
prog.flash(0, "build/icebreaker/gateware/icebreaker.bin")
def create_programmer(self):
return IceStormProgrammer()
def flash(build_dir, build_name, bios_flash_offset):
from litex.build.lattice.programmer import IceStormProgrammer
prog = IceStormProgrammer()
prog.flash(bios_flash_offset, f"{build_dir}/software/bios/bios.bin")
prog.flash(0x00000000, f"{build_dir}/gateware/{build_name}.bin")
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--flash-offset",
default=0x40000,
help="Boot offset in SPI Flash")
parser.add_argument("--sys-clk-freq",
type=float,
default=21e6,
help="Select system clock frequency")
parser.add_argument("--nextpnr-seed",
default=0,
help="Select nextpnr pseudo random seed")
parser.add_argument("--nextpnr-placer",
default="heap",
choices=["sa", "heap"],
help="Select nextpnr placer algorithm")
parser.add_argument(
"--debug",
action="store_true",
help=
"Enable debug features. (UART has to be used with the wishbone-tool.)")
parser.add_argument(
"--document-only",
action="store_true",
help="Do not build a soc. Only generate documentation.")
parser.add_argument("--flash", action="store_true", help="Load bitstream")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
# Create the SOC
soc = BaseSoC(debug=args.debug,
flash_offset=args.flash_offset,
sys_clk_freq=int(args.sys_clk_freq),
**soc_core_argdict(args))
soc.set_yosys_nextpnr_settings(nextpnr_seed=args.nextpnr_seed,
nextpnr_placer=args.nextpnr_placer)
# Configure command line parameter defaults
# Don't build software -- we don't include it since we just jump to SPI flash.
builder_kwargs = builder_argdict(args)
builder_kwargs["compile_software"] = False
if args.document_only:
builder_kwargs["compile_gateware"] = False
if builder_kwargs["csr_svd"] is None:
builder_kwargs["csr_svd"] = "../rust/icebesoc-pac/iCEBESOC.svd"
if builder_kwargs["memory_x"] is None:
builder_kwargs["memory_x"] = "../rust/icebesoc-pac/memory.x"
# Create and run the builder
builder = Builder(soc, **builder_kwargs)
builder.build()
lxsocdoc.generate_docs(soc,
"build/documentation/",
project_name="iCEBreaker LiteX Riscv Example SOC",
author="Piotr Esden-Tempski")
# If requested load the resulting bitstream onto the iCEBreaker
if args.flash:
IceStormProgrammer().flash(0x00000000,
"soc_basesoc_icebreaker/gateware/top.bin")