def test_cas_tccd(self):
# Verify tCCD.
def main_generator(dut):
yield from dut.bm_drivers[2].read()
yield from dut.bm_drivers[3].read()
ready = {2: dut.bank_machines[2].cmd.ready, 3: dut.bank_machines[3].cmd.ready}
# Wait for activate
while not ((yield ready[2]) or (yield ready[3])):
yield
# Invalidate command that was ready
if (yield ready[2]):
yield from dut.bm_drivers[2].nop()
else:
yield from dut.bm_drivers[3].nop()
yield
# Wait for the second activate; start from 1 for the previous cycle
cas_time = 1
while not ((yield ready[2]) or (yield ready[3])):
cas_time += 1
yield
self.assertEqual(cas_time, 3)
dut = MultiplexerDUT(timing_settings=dict(tCCD=3))
generators = [
main_generator(dut),
timeout_generator(50),
]
run_simulation(dut, generators)
def test_fsm_anti_starvation(self):
# Check that anti-starvation works according to controller settings.
def main_generator(dut):
yield from dut.bm_drivers[2].read()
yield from dut.bm_drivers[3].write()
# Go to WRITE
# anti starvation does not work for 1st read, as read_time_en already starts as 1
# READ -> RTW -> WRITE
while (yield from dut.fsm_state()) != "WRITE":
yield
# wait for write anti starvation
for _ in range(dut.settings.write_time):
self.assertEqual((yield from dut.fsm_state()), "WRITE")
yield
self.assertEqual((yield from dut.fsm_state()), "WTR")
# WRITE -> WTR -> READ
while (yield from dut.fsm_state()) != "READ":
yield
# Wait for read anti starvation
for _ in range(dut.settings.read_time):
self.assertEqual((yield from dut.fsm_state()), "READ")
yield
self.assertEqual((yield from dut.fsm_state()), "RTW")
dut = MultiplexerDUT()
generators = [
main_generator(dut),
timeout_generator(100),
]
run_simulation(dut, generators)
def test_steer_write_correct_phases(self):
# Check that correct phases are being used during WRITE.
def main_generator(dut):
yield from dut.bm_drivers[2].write()
yield from dut.bm_drivers[3].activate()
while not (yield dut.bank_machines[2].cmd.ready):
yield
yield
# fsm starts in READ
for phase in range(dut.settings.phy.nphases):
if phase == dut.settings.phy.wrphase:
self.assertEqual((yield dut.dfi.phases[phase].bank), 2)
elif phase == dut.settings.phy.wrcmdphase:
self.assertEqual((yield dut.dfi.phases[phase].bank), 3)
else:
self.assertEqual((yield dut.dfi.phases[phase].bank), 0)
dut = MultiplexerDUT()
generators = [
main_generator(dut),
timeout_generator(50),
]
run_simulation(dut, generators)
def test_single_phase_cmd_req(self):
# Verify that, for a single phase, commands are sent sequentially.
def main_generator(dut):
yield from dut.bm_drivers[2].write()
yield from dut.bm_drivers[3].activate()
ready = {2: dut.bank_machines[2].cmd.ready, 3: dut.bank_machines[3].cmd.ready}
# Activate should appear first
while not ((yield ready[2]) or (yield ready[3])):
yield
yield from dut.bm_drivers[3].nop()
yield
self.assertEqual((yield dut.dfi.phases[0].bank), 3)
# Then write
while not (yield ready[2]):
yield
yield from dut.bm_drivers[2].nop()
yield
self.assertEqual((yield dut.dfi.phases[0].bank), 2)
dut = MultiplexerDUT(phy_settings=dict(nphases=1))
generators = [
main_generator(dut),
timeout_generator(50),
]
run_simulation(dut, generators)
def test_fsm_write_to_read_latency(self):
# Verify the timing of WRITE to READ transition.
def main_generator(dut):
write_latency = math.ceil(dut.settings.phy.cwl / dut.settings.phy.nphases)
wtr = dut.settings.timing.tWTR + write_latency + dut.settings.timing.tCCD or 0
expected = "w" + (wtr - 1) * ">" + "r"
states = ""
# Simulate until we are in WRITE
yield from dut.bm_drivers[0].write()
while (yield from dut.fsm_state()) != "WRITE":
yield
# Set read_available=1
yield from dut.bm_drivers[0].read()
yield
for _ in range(len(expected)):
state = (yield from dut.fsm_state())
states += {
"READ": "r",
"WRITE": "w",
}.get(state, ">")
yield
self.assertEqual(states, expected)
dut = MultiplexerDUT()
generators = [
main_generator(dut),
timeout_generator(50),
]
run_simulation(dut, generators)
def test_fsm_read_to_write_latency(self):
# Verify the timing of READ to WRITE transition.
def main_generator(dut):
rtw = dut.settings.phy.read_latency
expected = "r" + (rtw - 1) * ">" + "w"
states = ""
# Set write_available=1
yield from dut.bm_drivers[0].write()
yield
for _ in range(len(expected)):
state = (yield from dut.fsm_state())
# Use ">" for all other states, as FSM.delayed_enter uses anonymous states instead
# of staying in RTW
states += {
"READ": "r",
"WRITE": "w",
}.get(state, ">")
yield
self.assertEqual(states, expected)
dut = MultiplexerDUT()
run_simulation(dut, main_generator(dut))
def test_fsm_start_at_read(self):
# FSM should start at READ state (assumed in some other tests).
def main_generator(dut):
self.assertEqual((yield from dut.fsm_state()), "READ")
dut = MultiplexerDUT()
run_simulation(dut, main_generator(dut))
def wishbone_readback_test(self,
pattern,
mem_expected,
wishbone,
port,
base_address=0):
class DUT(Module):
def __init__(self):
self.port = port
self.wb = wishbone
self.submodules += LiteDRAMWishbone2Native(
wishbone=self.wb,
port=self.port,
base_address=base_address)
self.mem = DRAMMemory(port.data_width, len(mem_expected))
def main_generator(dut):
for adr, data in pattern:
yield from dut.wb.write(adr, data)
data_r = (yield from dut.wb.read(adr))
self.assertEqual(data_r, data)
dut = DUT()
generators = [
main_generator(dut),
dut.mem.write_handler(dut.port),
dut.mem.read_handler(dut.port),
]
run_simulation(dut, generators)
self.assertEqual(dut.mem.mem, mem_expected)
def test_refresh_requires_gnt(self):
# After refresher command request, multiplexer waits for permission from all bank machines.
def main_generator(dut):
def assert_dfi_cmd(cas, ras, we):
p = dut.dfi.phases[0]
cas_n, ras_n, we_n = (yield p.cas_n), (yield p.ras_n), (yield p.we_n)
self.assertEqual((cas_n, ras_n, we_n), (1 - cas, 1 - ras, 1 - we))
for bm in dut.bank_machines:
self.assertEqual((yield bm.refresh_req), 0)
yield from dut.refresh_driver.refresh()
yield
# Bank machines get the request
for bm in dut.bank_machines:
self.assertEqual((yield bm.refresh_req), 1)
# No command yet
yield from assert_dfi_cmd(cas=0, ras=0, we=0)
# Grant permission for refresh
prng = random.Random(42)
delays = [prng.randrange(100) for _ in dut.bank_machines]
for t in range(max(delays) + 1):
# Grant permission
for delay, bm in zip(delays, dut.bank_machines):
if delay == t:
yield bm.refresh_gnt.eq(1)
yield
# Make sure thare is no command yet
yield from assert_dfi_cmd(cas=0, ras=0, we=0)
yield
yield
# Refresh command
yield from assert_dfi_cmd(cas=1, ras=1, we=0)
dut = MultiplexerDUT()
run_simulation(dut, main_generator(dut))
def test_write_datapath(self):
# Verify that data is transmitted from native interface to DFI.
def main_generator(dut):
yield from dut.bm_drivers[2].write()
# 16bits * 2 (DDR) * 1 (phases)
yield dut.interface.wdata.eq(0xbaadf00d)
yield dut.interface.wdata_we.eq(0xf)
while not (yield dut.bank_machines[2].cmd.ready):
yield
yield
self.assertEqual((yield dut.dfi.phases[0].wrdata), 0xbaadf00d)
self.assertEqual((yield dut.dfi.phases[0].wrdata_en), 1)
self.assertEqual((yield dut.dfi.phases[0].address), 2)
self.assertEqual((yield dut.dfi.phases[0].bank), 2)
dut = MultiplexerDUT(phy_settings=dict(nphases=1))
generators = [
main_generator(dut),
timeout_generator(50),
]
run_simulation(dut, generators)
def test_requests_from_multiple_bankmachines(self):
# Check complex communication scenario with requests from multiple bank machines
# The communication is greatly simplified - data path is completely ignored, no responses
# from PHY are simulated. Each bank machine performs a sequence of requests, bank machines
# are ordered randomly and the DFI command data is checked to verify if all the commands
# have been sent if correct per-bank order.
# Tequests sequence on given bank machines
bm_sequences = {
0: "awwwwwwp",
1: "arrrrrrp",
2: "arwrwrwp",
3: "arrrwwwp",
4: "awparpawp",
5: "awwparrrrp",
}
# convert to lists to use .pop()
bm_sequences = {bm_num: list(seq) for bm_num, seq in bm_sequences.items()}
def main_generator(bank_machines, drivers):
# work on a copy
bm_seq = copy.deepcopy(bm_sequences)
def non_empty():
return list(filter(lambda n: len(bm_seq[n]) > 0, bm_seq.keys()))
# Artificially perform the work of LiteDRAMCrossbar by always picking only one request
prng = random.Random(42)
while len(non_empty()) > 0:
# Pick random bank machine
bm_num = prng.choice(non_empty())
# Set given request
request_char = bm_seq[bm_num].pop(0)
yield from drivers[bm_num].request(request_char)
yield
# Wait for ready
while not (yield bank_machines[bm_num].cmd.ready):
yield
# Disable it
yield from drivers[bm_num].nop()
for _ in range(16):
yield
# Gather data on DFI
DFISnapshot = namedtuple("DFICapture",
["cmd", "bank", "address", "wrdata_en", "rddata_en"])
dfi_snapshots = []
@passive
def dfi_monitor(dfi):
while True:
# Capture current state of DFI lines
phases = []
for i, p in enumerate(dfi.phases):
# Transform cas/ras/we to command name
cas_n, ras_n, we_n = (yield p.cas_n), (yield p.ras_n), (yield p.we_n)
captured = {"cmd": dfi_cmd_to_char(cas_n, ras_n, we_n)}
# Capture rest of fields
for field in DFISnapshot._fields:
if field != "cmd":
captured[field] = (yield getattr(p, field))
phases.append(DFISnapshot(**captured))
dfi_snapshots.append(phases)
yield
dut = MultiplexerDUT()
generators = [
main_generator(dut.bank_machines, dut.bm_drivers),
dfi_monitor(dut.dfi),
timeout_generator(200),
]
run_simulation(dut, generators)
# Check captured DFI data with the description
for snap in dfi_snapshots:
for i, phase_snap in enumerate(snap):
if phase_snap.cmd == "_":
continue
# Distinguish bank machines by the bank number
bank = phase_snap.bank
# Find next command for the given bank
cmd = bm_sequences[bank].pop(0)
# Check if the captured data is correct
self.assertEqual(phase_snap.cmd, cmd)
if cmd in ["w", "r"]:
# Addresses are artificially forced to bank numbers in drivers
self.assertEqual(phase_snap.address, bank)
if cmd == "w":
self.assertEqual(phase_snap.wrdata_en, 1)
if cmd == "r":
self.assertEqual(phase_snap.rddata_en, 1)
self.fsm.act('transfer',
If(clk_falling,
NextValue(self.spi.nSYNC, 0),
NextValue(self.mux.nE, 0),
NextValue(self.spi.DIN, Array(current_dac_word)[23 - current_bit]),
If(current_bit == 23,
NextValue(self.mux.nE, 1),
NextState('start'),
NextValue(self.mux.S, current_channel),
NextValue(current_channel, current_channel + 1)
).Else(NextValue(current_bit, current_bit + 1))
)
)
# output SPI CLK (if enabled)
self.sync += self.spi.SCLK.eq(clk & self._enable.storage[0])
from litex.gen.fhdl import verilog
from litex.gen.sim import run_simulation
if __name__ == '__main__':
def testbench_offsetdac(dut):
for _ in range(25 * 8 * 1000):
yield
print("Running simulation...")
t = OffsetDac()
run_simulation(t, testbench_offsetdac(t), vcd_name='offsetdac.vcd')
