def __init__(self, platform, sys_clk_freq):
self.rst = CSR()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_clk100 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
# # #
# Clk/Rst
clk50 = platform.request("clk50")
platform.add_period_constraint(clk50, 1e9 / 50e6)
# Delay software reset by 10us to ensure write has been acked on PCIe.
rst_delay = WaitTimer(int(10e-6 * sys_clk_freq))
self.submodules += rst_delay
self.sync += If(self.rst.re, rst_delay.wait.eq(1))
# PLL
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(rst_delay.done)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4 * sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_clk100, 100e6)
pll.create_clkout(self.cd_eth, 50e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
# # #
self.submodules.pll = pll = S7PLL(speedgrade=-1)
pll.register_clkin(platform.request("clk25"), 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
# # #
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys8x = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
# # #
self.submodules.pll = pll = S7PLL(speedgrade=-1)
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
pll.create_clkout(self.cd_sys8x, 8 * sys_clk_freq)
pll.create_clkout(self.cd_idelay, iodelay_clk_freq)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
# # #
self.cd_sys.clk.attr.add("keep")
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll_clkin = Signal()
pll.register_clkin(pll_clkin, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
self.specials += Instance("BUFG",
i_I=platform.request("clk100"),
o_O=pll_clkin)
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
# # #
pll_clkin = Signal()
self.specials += Instance("BUFG",
i_I=platform.request("clk100"),
o_O=pll_clkin)
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(pll_clkin, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4 * sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
def __init__(self, platform, sys_clk_freq):
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6)
self.clock_domains.cd_sys = ClockDomain()
pll.create_clkout(self.cd_sys, sys_clk_freq)
# Etherbone --------------------------------------------------------------------------------
self.clock_domains.cd_eth = ClockDomain()
pll.create_clkout(self.cd_eth, 25e6)
self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
# DDRPHY -----------------------------------------------------------------------------------
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4 * sys_clk_freq, phase=90)
self.clock_domains.cd_clk200 = ClockDomain()
pll.create_clkout(self.cd_clk200, 200e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
def __init__(self,
clock_pads,
pads,
with_hw_init_reset,
tx_delay=2e-9,
hw_reset_cycles=256):
self._reset = CSRStorage()
# # #
# RX clock
self.clock_domains.cd_eth_rx = ClockDomain()
eth_rx_clk_ibuf = Signal()
self.specials += [
Instance(
"IBUF",
i_I=clock_pads.rx,
o_O=eth_rx_clk_ibuf,
),
Instance(
"BUFG",
i_I=eth_rx_clk_ibuf,
o_O=self.cd_eth_rx.clk,
),
]
# TX clock
self.clock_domains.cd_eth_tx = ClockDomain()
self.clock_domains.cd_eth_tx_delayed = ClockDomain(reset_less=True)
tx_phase = 125e6 * tx_delay * 360
assert tx_phase < 360
from litex.soc.cores.clock import S7PLL
self.submodules.pll = pll = S7PLL()
pll.register_clkin(ClockSignal("eth_rx"), 125e6)
pll.create_clkout(self.cd_eth_tx, 125e6, with_reset=False)
pll.create_clkout(self.cd_eth_tx_delayed, 125e6, phase=tx_phase)
eth_tx_clk_obuf = Signal()
self.specials += [
Instance(
"ODDR",
p_DDR_CLK_EDGE="SAME_EDGE",
i_C=ClockSignal("eth_tx_delayed"),
i_CE=1,
i_S=0,
i_R=0,
i_D1=1,
i_D2=0,
o_Q=eth_tx_clk_obuf,
),
Instance(
"OBUF",
i_I=eth_tx_clk_obuf,
o_O=clock_pads.tx,
)
]
# Reset
self.reset = reset = Signal()
if with_hw_init_reset:
self.submodules.hw_reset = LiteEthPHYHWReset(
cycles=hw_reset_cycles)
self.comb += reset.eq(self._reset.storage | self.hw_reset.reset)
else:
self.comb += reset.eq(self._reset.storage)
if hasattr(pads, "rst_n"):
self.comb += pads.rst_n.eq(~reset)
self.specials += [
AsyncResetSynchronizer(self.cd_eth_tx, reset),
AsyncResetSynchronizer(self.cd_eth_rx, reset),
]