def do_finalize(self): registered_mems = {regions[0] for regions in self._memory_regions} if self.cpu_type is not None: for mem in "rom", "sram": if mem not in registered_mems: raise FinalizeError("CPU needs a {} to be registered with SoC.register_mem()".format(mem)) if len(self._wb_masters): # Wishbone self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters, self._wb_slaves, register=True) # CSR self.submodules.csrbankarray = csr_bus.CSRBankArray(self, self.get_csr_dev_address, data_width=self.csr_data_width, address_width=self.csr_address_width) self.submodules.csrcon = csr_bus.Interconnect( self.wishbone2csr.csr, self.csrbankarray.get_buses()) for name, csrs, mapaddr, rmap in self.csrbankarray.banks: self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, csrs) for name, memory, mapaddr, mmap in self.csrbankarray.srams: self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory) for name, constant in self.csrbankarray.constants: self._constants.append(((name + "_" + constant.name).upper(), constant.value.value)) for name, value in sorted(self.config.items(), key=itemgetter(0)): self._constants.append(("CONFIG_" + name.upper(), value)) # Interrupts if hasattr(self.cpu_or_bridge, "interrupt"): for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)): if hasattr(self, k): self.comb += self.cpu_or_bridge.interrupt[v].eq(getattr(self, k).ev.irq)
def do_finalize(self): # Verify CPU has required memories registered_mems = {regions[0] for regions in self._memory_regions} if self.cpu_type is not None: for mem in "rom", "sram": if mem not in registered_mems: raise FinalizeError("CPU needs \"{}\" to be registered with SoC.register_mem()".format(mem)) # Add the Wishbone Masters/Slaves interconnect if len(self._wb_masters): self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters, self._wb_slaves, register=True, timeout_cycles=self.wishbone_timeout_cycles) if self.with_ctrl and (self.wishbone_timeout_cycles is not None): self.comb += self.ctrl.bus_error.eq(self.wishbonecon.timeout.error) # Collect and create CSRs self.submodules.csrbankarray = csr_bus.CSRBankArray(self, self.get_csr_dev_address, data_width=self.csr_data_width, address_width=self.csr_address_width, alignment=self.csr_alignment) # Add CSRs interconnect if len(self._csr_masters) != 0: self.submodules.csrcon = csr_bus.InterconnectShared( self._csr_masters, self.csrbankarray.get_buses()) # Check and add CSRs regions for name, csrs, mapaddr, rmap in self.csrbankarray.banks: self.check_csr_range(name, 0x800*mapaddr) self.add_csr_region(name, (self.soc_mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, csrs) # Check and add Memory regions for name, memory, mapaddr, mmap in self.csrbankarray.srams: self.check_csr_range(name, 0x800*mapaddr) self.add_csr_region(name + "_" + memory.name_override, (self.soc_mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory) # Add CSRs / Config items to constants for name, constant in self.csrbankarray.constants: self._constants.append(((name + "_" + constant.name).upper(), constant.value.value)) for name, value in sorted(self.config.items(), key=itemgetter(0)): self._constants.append(("CONFIG_" + name.upper(), value)) if isinstance(value, str): self._constants.append(("CONFIG_" + name.upper() + "_" + value, 1)) # Connect interrupts if hasattr(self, "cpu"): if hasattr(self.cpu, "interrupt"): for _name, _id in sorted(self.soc_interrupt_map.items()): if _name in self.cpu.reserved_interrupts.keys(): continue if hasattr(self, _name): module = getattr(self, _name) assert hasattr(module, 'ev'), "Submodule %s does not have EventManager (xx.ev) module" % _name self.comb += self.cpu.interrupt[_id].eq(module.ev.irq)
def do_finalize(self): registered_mems = {regions[0] for regions in self._memory_regions} if self.cpu_type is not None: for mem in "rom", "sram": if mem not in registered_mems: raise FinalizeError( "CPU needs a {} to be registered with SoC.register_mem()" .format(mem)) if len(self._wb_masters): # Wishbone self.submodules.wishbonecon = wishbone.InterconnectShared( self._wb_masters, self._wb_slaves, register=True) if self.with_ctrl: self.comb += self.ctrl.bus_error.eq( self.wishbonecon.timeout.error) # CSR self.submodules.csrbankarray = csr_bus.CSRBankArray( self, self.get_csr_dev_address, data_width=self.csr_data_width, address_width=self.csr_address_width) if self.csr_expose: self.submodules.csrcon = csr_bus.InterconnectShared( [self.csr, self.wishbone2csr.csr], self.csrbankarray.get_buses()) else: self.submodules.csrcon = csr_bus.Interconnect( self.wishbone2csr.csr, self.csrbankarray.get_buses()) for name, csrs, mapaddr, rmap in self.csrbankarray.banks: self.add_csr_region(name, (self.mem_map["csr"] + 0x800 * mapaddr) | self.shadow_base, self.csr_data_width, csrs) for name, memory, mapaddr, mmap in self.csrbankarray.srams: self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800 * mapaddr) | self.shadow_base, self.csr_data_width, memory) for name, constant in self.csrbankarray.constants: self._constants.append(((name + "_" + constant.name).upper(), constant.value.value)) for name, value in sorted(self.config.items(), key=itemgetter(0)): self._constants.append(("CONFIG_" + name.upper(), value)) # Interrupts if hasattr(self.cpu_or_bridge, "interrupt"): for interrupt, mod_name in sorted(self.interrupt_rmap.items()): if mod_name == "nmi": continue if hasattr(self, mod_name): mod_impl = getattr(self, mod_name) assert hasattr( mod_impl, 'ev' ), "Submodule %s does not have EventManager (xx.ev) module" % mod_name self.comb += self.cpu_or_bridge.interrupt[ interrupt].eq(mod_impl.ev.irq)
def __init__(self, platform, clk_freq, code, wb_masters=None, wb_slaves=None): self.platform = platform self.submodules.cpu = MCS51(self.platform) # memories self.submodules.main_ram = MainRAM(init=code) self.submodules.scratch_ram = ScratchRAM() self.submodules.gpif_waveforms = GPIFWaveformsBuffer() self.submodules.csr_bank = FX2CSRBank() self.submodules.ep0 = EP0Buffer() self.submodules.ep1_out = EP1OutBuffer() self.submodules.ep1_in = EP1InBuffer() self.submodules.ep2468 = EP2468Buffer() # connect instruction memory directly using csr bus self.submodules.csr_interconn = csr_bus.Interconnect( self.cpu.ibus, [self.main_ram.ibus]) # connect all wishbone masters and slaves masters = [self.cpu.dbus] + (wb_masters or []) slaves = [ self.main_ram, self.scratch_ram, self.gpif_waveforms, self.csr_bank, self.ep0, self.ep1_out, self.ep1_in, self.ep2468, ] slaves = [(slave.mem_decoder(), slave.bus) for slave in slaves] + (wb_slaves or []) self.submodules.wb_interconn = wishbone.InterconnectShared( masters, slaves, register=True) self.submodules.usb = FX2USB(self)
def __init__(self, platform): self.submodules.crg = _CRG(platform, int(50e6)) # SRAM self.submodules.sram = wishbone.SRAM(1024) # SD Emulator sdcard_pads = _sdemulator_pads() self.submodules.sdemulator = ClockDomainsRenamer("sd")( SDEmulator(platform, sdcard_pads)) # SD Core self.submodules.sdphy = SDPHY(sdcard_pads, platform.device) self.submodules.sdcore = SDCore(self.sdphy) self.submodules.bist_generator = BISTBlockGenerator(random=False) self.submodules.bist_checker = BISTBlockChecker(random=False) self.comb += [ self.sdcore.source.connect(self.bist_checker.sink), self.bist_generator.source.connect(self.sdcore.sink) ] # Wishbone self.bus = wishbone.Interface() wb_masters = [ self.bus ] wb_slaves = [ (mem_decoder(sram_base), self.sram.bus), (mem_decoder(sdemulator_base), self.sdemulator.bus) ] self.submodules.wb_decoder = wishbone.InterconnectShared(wb_masters, wb_slaves, register=True) # Tester self.submodules.sdtester = SDTester(self.sdcore, self.sdemulator, self.bist_generator, self.bist_checker, self.bus)
def do_finalize(self): # Verify CPU has required memories if not isinstance(self.cpu, cpu.CPUNone): for name in ["rom", "sram"]: if name not in self.mem_regions.keys(): raise FinalizeError( "CPU needs \"{}\" to be defined as memory or linker region" .format(name)) # Add the Wishbone Masters/Slaves interconnect if len(self._wb_masters): self.submodules.wishbonecon = wishbone.InterconnectShared( self._wb_masters, self._wb_slaves, register=True, timeout_cycles=self.wishbone_timeout_cycles) if self.with_ctrl and (self.wishbone_timeout_cycles is not None): self.comb += self.ctrl.bus_error.eq( self.wishbonecon.timeout.error) # Collect and create CSRs self.submodules.csrbankarray = csr_bus.CSRBankArray( self, self.get_csr_dev_address, data_width=self.csr_data_width, address_width=self.csr_address_width, alignment=self.csr_alignment) # Add CSRs interconnect if len(self._csr_masters) != 0: self.submodules.csrcon = csr_bus.InterconnectShared( self._csr_masters, self.csrbankarray.get_buses()) # Check and add CSRs regions for name, csrs, mapaddr, rmap in self.csrbankarray.banks: self.check_csr_range(name, 0x800 * mapaddr) self.add_csr_region(name, (self.soc_mem_map["csr"] + 0x800 * mapaddr), self.csr_data_width, csrs) # Check and add Memory regions for name, memory, mapaddr, mmap in self.csrbankarray.srams: self.check_csr_range(name, 0x800 * mapaddr) self.add_csr_region(name + "_" + memory.name_override, (self.soc_mem_map["csr"] + 0x800 * mapaddr), self.csr_data_width, memory) # Sort CSR regions by origin self.csr_regions = { k: v for k, v in sorted(self.csr_regions.items(), key=lambda item: item[1].origin) } # Add CSRs / Config items to constants for name, constant in self.csrbankarray.constants: self.add_constant(name.upper() + "_" + constant.name.upper(), constant.value.value) for name, value in sorted(self.config.items(), key=itemgetter(0)): self.add_constant("CONFIG_" + name.upper(), value) if isinstance(value, str): self.add_constant("CONFIG_" + name.upper() + "_" + value) # Connect interrupts if hasattr(self.cpu, "interrupt"): for _name, _id in sorted(self.soc_interrupt_map.items()): if _name in self.cpu.interrupts.keys(): continue if hasattr(self, _name): module = getattr(self, _name) assert hasattr( module, 'ev' ), "Submodule %s does not have EventManager (xx.ev) module" % _name self.comb += self.cpu.interrupt[_id].eq(module.ev.irq) self.constants[_name.upper() + "_INTERRUPT"] = _id
def do_finalize(self): self.logger.info(colorer("-"*80, color="bright")) self.logger.info(colorer("Finalized SoC:")) self.logger.info(colorer("-"*80, color="bright")) self.logger.info(self.bus) self.logger.info(self.csr) self.logger.info(self.irq) self.logger.info(colorer("-"*80, color="bright")) # SoC Bus Interconnect --------------------------------------------------------------------- bus_masters = self.bus.masters.values() bus_slaves = [(self.bus.regions[n].decoder(self.bus), s) for n, s in self.bus.slaves.items()] if len(bus_masters) and len(bus_slaves): self.submodules.bus_interconnect = wishbone.InterconnectShared( masters = bus_masters, slaves = bus_slaves, register = True, timeout_cycles = self.bus.timeout) if hasattr(self, "ctrl") and self.bus.timeout is not None: self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error) # SoC CSR Interconnect --------------------------------------------------------------------- self.submodules.csr_bankarray = csr_bus.CSRBankArray(self, address_map = self.csr.address_map, data_width = self.csr.data_width, address_width = self.csr.address_width, alignment = self.csr.alignment, paging = self.csr.paging, soc_bus_data_width = self.bus.data_width) if len(self.csr.masters): self.submodules.csr_interconnect = csr_bus.InterconnectShared( masters = list(self.csr.masters.values()), slaves = self.csr_bankarray.get_buses()) # Add CSRs regions for name, csrs, mapaddr, rmap in self.csr_bankarray.banks: self.csr.add_region(name, SoCCSRRegion( origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr), busword = self.csr.data_width, obj = csrs)) # Add Memory regions for name, memory, mapaddr, mmap in self.csr_bankarray.srams: self.csr.add_region(name + "_" + memory.name_override, SoCCSRRegion( origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr), busword = self.csr.data_width, obj = memory)) # Sort CSR regions by origin self.csr.regions = {k: v for k, v in sorted(self.csr.regions.items(), key=lambda item: item[1].origin)} # Add CSRs / Config items to constants for name, constant in self.csr_bankarray.constants: self.add_constant(name + "_" + constant.name, constant.value.value) # SoC CPU Check ---------------------------------------------------------------------------- if not isinstance(self.cpu, cpu.CPUNone): for name in ["rom", "sram"]: if name not in self.bus.regions.keys(): self.logger.error("CPU needs {} Region to be {} as Bus or Linker Region.".format( colorer(name), colorer("defined", color="red"))) self.logger.error(self.bus) raise # SoC IRQ Interconnect --------------------------------------------------------------------- if hasattr(self, "cpu"): if hasattr(self.cpu, "interrupt"): for name, loc in sorted(self.irq.locs.items()): if name in self.cpu.interrupts.keys(): continue if hasattr(self, name): module = getattr(self, name) if not hasattr(module, "ev"): self.logger.error("EventManager {} in {} SubModule.".format( colorer("not found", color="red"), colorer(name))) raise self.comb += self.cpu.interrupt[loc].eq(module.ev.irq) self.add_constant(name + "_INTERRUPT", loc)