def connect(desc, *args, add_args=None, **kw):
parser = argparse.ArgumentParser(description=desc)
make_args(parser, *args, **kw)
parser.add_argument("--ipaddress")
parser.add_argument("--port") #, desc="Serial port")
if add_args is not None:
add_args(parser)
args = parser.parse_args()
if args.port:
s = ServerProxy(args.port)
s.start()
while not s.ready:
continue
args.ipaddress = "127.0.0.1"
elif not args.ipaddress:
args.ipaddress = "{}.50".format(args.iprange)
print("Connecting to {}".format(args.ipaddress))
wb = RemoteClient(args.ipaddress,
1234,
csr_csv="{}/csr.csv".format(make_testdir(args)),
csr_data_width=32)
wb.open()
print()
print("Device DNA: {}".format(get_dna(wb)))
print(" Git Rev: {}".format(get_git(wb)))
print(" Platform: {}".format(get_platform(wb)))
print(" Analyzer: {}".format(["No", "Yes"][hasattr(wb.regs, "analyzer")]))
print(" XADC: {}".format(get_xadc(wb)))
print()
return args, wb
def __init__(self, MainWindow):
super().__init__()
self.wb = RemoteClient()
self.wb.open()
self.prcon = PRBSControl(self.wb.regs, "top_gtp")
self.setupUi(MainWindow)
self.attachHandlers()
self.prcon.BERinit()
self.pllStatusCheck()
self.checklinkstatus()
self.updateBER()
def __init__(self,MainWindow):
super().__init__()
self.wb = RemoteClient()
self.wb.open()
self.sel=0
self.prcon = PRBSControl(self.wb.regs,"top_gtp")
self.setupUi(MainWindow)
self.attachHandlers()
self.prcon.phaseAlign()
self.prcon.BERinit()
self.lineratelabel.setText(self.prcon.MGTLinerate()+" Gbps")
self.updateAnalyzer()
#!/usr/bin/env python3
import sys
import time
from litex.soc.tools.remote import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver
wb_amc = RemoteClient(port=1234, csr_csv="../sayma_amc/csr.csv", debug=False)
wb_rtm = RemoteClient(port=1235, csr_csv="../sayma_rtm/csr.csv", debug=False)
wb_amc.open()
wb_rtm.open()
# # #
def seed_to_data(seed, random=True):
if random:
return (1664525 * seed + 1013904223) & 0xffffffff
else:
return seed
def write_pattern(length):
for i in range(length):
wb_amc.write(wb_amc.mems.serwb.base + 4 * i, seed_to_data(i))
def check_pattern(length, debug=False):
errors = 0
def main():
parser = argparse.ArgumentParser(description=__doc__)
parser.add_argument("--tty_ctrl",
default="/dev/ttyUSB1",
help="UartWishboneBridge for control")
parser.add_argument("--tty_dump",
default="/dev/ttyUSB2",
help="UartMemoryDumper for data")
parser.add_argument("--br_ctrl",
default=115200,
type=int,
help="UartWishboneBridge baudrate")
parser.add_argument("--br_dump",
default=115200,
type=int,
help="UartMemoryDumper baudrate")
args = parser.parse_args()
#----------------------------------------------
# Setup litex_server
#----------------------------------------------
call(["pkill", "litex_server*"])
Popen(["litex_server", "uart", args.tty_ctrl, str(args.br_ctrl)])
sleep(0.5)
wishbone = RemoteClient(csr_csv="./build/csr.csv")
atexit.register(wishbone.close)
wishbone.open()
fclk = wishbone.constants.system_clock_frequency
#----------------------------------------------
# Setup Matplotlib
#----------------------------------------------
def get_tau():
intVal = wishbone.regs.ccd_i_tau.read()
tau = intVal / fclk / 1e-3
return tau
def set_tau(tau):
intVal = int(tau * 1e-3 * fclk)
wishbone.regs.ccd_i_tau.write(intVal)
fig, axs = subplots(2, 1, figsize=(10, 6))
# Rolling image
i = axs[0].imshow(
rollBuffer.transpose(),
vmin=0,
vmax=4095,
aspect="equal",
animated=True,
# cmap="gnuplot2"
)
# Line plot
l, = axs[1].plot(arange(128), zeros(128), "-o")
axs[1].axis((-1, 128, -1, 4096))
fig.tight_layout()
# GUI slider
axfreq = axes([0.13, 0.9, 0.7, 0.05])
sfreq = Slider(axfreq, 'Tau [ms]', 0.01, 100, valinit=get_tau())
sfreq.on_changed(set_tau)
#----------------------------------------------
# Setup serial reader thread
#----------------------------------------------
wishbone.regs.mem_dump_tuneWord.write(int(args.br_dump / fclk * 2**32))
serial = Serial(args.tty_dump, args.br_dump)
def read_from_port():
global rollBuffer
while serial.isOpen():
serial.read_until(b"\x42")
buf = serial.read(256)
readData = fromstring(buf, dtype=">u2")
rollBuffer = roll(rollBuffer, 1, 0)
rollBuffer[0, :] = readData
l.set_ydata(readData)
i.set_array(rollBuffer.transpose())
fig.canvas.draw_idle()
# print("*", end="", flush=True)
atexit.register(serial.close)
threading.Thread(target=read_from_port).start()
show()
# use nexys_ddr3 design with this script to # find working bitslip/delay configuration dfii_control_sel = 0x01 dfii_control_cke = 0x02 dfii_control_odt = 0x04 dfii_control_reset_n = 0x08 dfii_command_cs = 0x01 dfii_command_we = 0x02 dfii_command_cas = 0x04 dfii_command_ras = 0x08 dfii_command_wrdata = 0x10 dfii_command_rddata = 0x20 wb = RemoteClient(csr_data_width=8) wb.open() regs = wb.regs # # # regs.sdram_dfii_control.write(0) # release reset regs.sdram_dfii_pi0_address.write(0x0) regs.sdram_dfii_pi0_baddress.write(0) regs.sdram_dfii_control.write(dfii_control_odt | dfii_control_reset_n) time.sleep(0.1) # bring cke high regs.sdram_dfii_pi0_address.write(0x0)
from litex.soc.tools.remote import RemoteClient
wb = RemoteClient()
wb.open()
# # #
identifier = ""
for i in range(30):
identifier += chr(wb.read(wb.bases.identifier_mem + 4*(i+1))) # TODO: why + 1?
print(identifier)
print("frequency : {}MHz".format(wb.constants.system_clock_frequency/1000000))
print("link up : {}".format(wb.regs.pcie_phy_lnk_up.read()))
print("bus_master_enable : {}".format(wb.regs.pcie_phy_bus_master_enable.read()))
print("msi_enable : {}".format(wb.regs.pcie_phy_msi_enable.read()))
print("max_req_request_size : {}".format(wb.regs.pcie_phy_max_request_size.read()))
print("max_payload_size : {}".format(wb.regs.pcie_phy_max_payload_size.read()))
# # #
wb.close()
SATA BIST utility.
""")
parser.add_argument("-s", "--transfer_size", default=1024, help="transfer sizes (in KB, up to 16MB)")
parser.add_argument("-l", "--total_length", default=256, help="total transfer length (in MB, up to HDD capacity)")
parser.add_argument("-n", "--loops", default=1, help="number of loop per transfer (allow more precision on speed calculation for small transfers)")
parser.add_argument("-r", "--random", action="store_true", help="use random data")
parser.add_argument("-c", "--continuous", action="store_true", help="continuous mode (Escape to exit)")
parser.add_argument("-i", "--identify", action="store_true", help="only run identify")
parser.add_argument("-t", "--software_timer", action="store_true", help="use software timer")
parser.add_argument("-a", "--random_addressing", action="store_true", help="use random addressing")
parser.add_argument("-d", "--delayed_read", action="store_true", help="read after total length has been written")
return parser.parse_args()
if __name__ == "__main__":
args = _get_args()
wb = RemoteClient()
wb.open()
# # #
identify = LiteSATABISTIdentifyDriver(wb.regs, wb.constants, "sata_bist")
generator = LiteSATABISTGeneratorDriver(wb.regs, wb.constants, "sata_bist")
checker = LiteSATABISTCheckerDriver(wb.regs, wb.constants, "sata_bist")
identify.run()
identify.hdd_info()
if not int(args.identify):
count = int(args.transfer_size)*KB//logical_sector_size
loops = int(args.loops)
length = int(args.total_length)*MB
random = int(args.random)
continuous = int(args.continuous)
# use arty_ddr3 design with this script to # find working bitslip/delay configuration dfii_control_sel = 0x01 dfii_control_cke = 0x02 dfii_control_odt = 0x04 dfii_control_reset_n = 0x08 dfii_command_cs = 0x01 dfii_command_we = 0x02 dfii_command_cas = 0x04 dfii_command_ras = 0x08 dfii_command_wrdata = 0x10 dfii_command_rddata = 0x20 wb = RemoteClient(debug=False) wb.open() # # # wb.regs.sdram_dfii_control.write(0) # release reset wb.regs.sdram_dfii_pi0_address.write(0x0) wb.regs.sdram_dfii_pi0_baddress.write(0) wb.regs.sdram_dfii_control.write(dfii_control_odt | dfii_control_reset_n) time.sleep(0.1) # bring cke high wb.regs.sdram_dfii_pi0_address.write(0x0) wb.regs.sdram_dfii_pi0_baddress.write(0)
# DDR3 init and test for sayma ddr3 test design dfii_control_sel = 0x01 dfii_control_cke = 0x02 dfii_control_odt = 0x04 dfii_control_reset_n = 0x08 dfii_command_cs = 0x01 dfii_command_we = 0x02 dfii_command_cas = 0x04 dfii_command_ras = 0x08 dfii_command_wrdata = 0x10 dfii_command_rddata = 0x20 wb = RemoteClient(port=1234, debug=False) wb.open() # # # wb.regs.sdram_dfii_control.write(0) # release reset wb.regs.sdram_dfii_pi0_address.write(0x0) wb.regs.sdram_dfii_pi0_baddress.write(0) wb.regs.sdram_dfii_control.write(dfii_control_odt|dfii_control_reset_n) time.sleep(0.1) # bring cke high wb.regs.sdram_dfii_pi0_address.write(0x0) wb.regs.sdram_dfii_pi0_baddress.write(0)
# use arty_ddr3 design with this script to # find working bitslip/delay configuration dfii_control_sel = 0x01 dfii_control_cke = 0x02 dfii_control_odt = 0x04 dfii_control_reset_n = 0x08 dfii_command_cs = 0x01 dfii_command_we = 0x02 dfii_command_cas = 0x04 dfii_command_ras = 0x08 dfii_command_wrdata = 0x10 dfii_command_rddata = 0x20 wb = RemoteClient(debug=True) wb.open() regs = wb.regs # # # regs.sdram_dfii_control.write(0) # release reset regs.sdram_dfii_pi0_address.write(0x0) regs.sdram_dfii_pi0_baddress.write(0) regs.sdram_dfii_control.write(dfii_control_odt | dfii_control_reset_n) time.sleep(0.1) # bring cke high regs.sdram_dfii_pi0_address.write(0x0)
class Ui(Ui_MainWindow):
def __init__(self, MainWindow):
super().__init__()
self.wb = RemoteClient()
self.wb.open()
self.prcon = PRBSControl(self.wb.regs, "top_gtp")
self.setupUi(MainWindow)
self.attachHandlers()
self.prcon.BERinit()
self.pllStatusCheck()
self.checklinkstatus()
self.updateBER()
def attachHandlers(self):
self.comboBox_4.activated.connect(self.handleActivatedTx)
self.comboBox_5.activated.connect(self.handleActivatedRx)
self.comboBox_6.activated.connect(self.handleActivatedErr)
self.txpolcheckbox.stateChanged.connect(self.txpolchange)
self.rxpolcheckbox.stateChanged.connect(self.rxpolchange)
self.loopbackcheck.stateChanged.connect(self.loopbackmode)
self.txrst.clicked.connect(self.TxReset)
self.rxrst.clicked.connect(self.RxReset)
self.submitbutton.clicked.connect(self.drpReadWrite)
self.swingcombo.activated.connect(self.changeSwing)
self.precombo.activated.connect(self.changePrecursor)
self.postcombo.activated.connect(self.changePostcursor)
def drpReadWrite(self):
drp_addr = int(self.drpaddr.text(), 16)
drp_value = int(self.drpval.text(), 16)
if drpreadradio.isChecked == True:
self.prcon.drpWrite(drp_addr, drp_value)
if drpwriteradio.isChecked == True:
drp_value = self.prcon.drpRead(drp_addr)
self.drpval.setText(hex(drp_value))
def loopbackmode(self, state):
if state == QtCore.Qt.Checked:
self.enableLoopback()
else:
self.disableLoopback()
def txpolchange(self, state):
if state == QtCore.Qt.Checked:
self.txPolarity(True)
else:
self.txPolarity(False)
def rxpolchange(self, state):
if state == QtCore.Qt.Checked:
self.rxPolarity(True)
else:
self.rxPolarity(False)
def changeSwing(self, index):
if index == 0:
self.prcon.changeOutputSwing(0b0001)
if index == 1:
self.prcon.changeOutputSwing(0b0100)
if index == 2:
self.prcon.changeOutputSwing(0b1000)
if index == 3:
self.prcon.changeOutputSwing(0b1011)
if index == 4:
self.prcon.changeOutputSwing(0b1111)
def changePrecursor(self, index):
if index == 0:
self.prcon.changetxPrecursor(0b00000)
if index == 1:
self.prcon.changetxPrecursor(0b00010)
if index == 2:
self.prcon.changetxPrecursor(0b00101)
if index == 3:
self.prcon.changetxPrecursor(0b01000)
if index == 4:
self.prcon.changetxPrecursor(0b01111)
if index == 5:
self.prcon.changetxPrecursor(0b10100)
def changePostcursor(self, index):
if index == 0:
self.prcon.changetxPostcursor(0b00000)
if index == 1:
self.prcon.changetxPostcursor(0b00010)
if index == 2:
self.prcon.changetxPostcursor(0b00100)
if index == 3:
self.prcon.changetxPostcursor(0b01000)
if index == 4:
self.prcon.changetxPostcursor(0b01111)
if index == 5:
self.prcon.changetxPostcursor(0b10100)
if index == 6:
self.prcon.changetxPostcursor(0b11000)
if index == 7:
self.prcon.changetxPostcursor(0b11110)
def pllStatusCheck(self):
self.plllabel.setText(prcon.PLLlockStatus())
QtCore.QTimer.singleShot(5000, self.updateBER)
def updateBER(self):
self.label_4.setText(str(round(self.prcon.calcBER(), 3)))
QtCore.QTimer.singleShot(1000, self.updateBER)
def checklinkstatus(self):
self.linklabel.setText(prcon.checkMGTLink())
QtCore.QTimer.singleShot(5000, self.checklinkstatus)
def TxReset(self):
self.prcon.resetTx()
def RxReset(self):
self.prcon.resetRx()
def handleActivatedTx(self, index):
if index == 0:
self.prcon.setPRBSConfig(7, None)
if index == 1:
self.prcon.setPRBSConfig(15, None)
if index == 2:
self.prcon.setPRBSConfig(23, None)
if index == 3:
self.prcon.setPRBSConfig(31, None)
def handleActivatedRx(self, index):
if index == 0:
self.prcon.setPRBSConfig(None, 7)
if index == 1:
self.prcon.setPRBSConfig(None, 15)
if index == 2:
self.prcon.setPRBSConfig(None, 23)
if index == 3:
self.prcon.setPRBSConfig(None, 31)
def handleActivatedErr(self, index):
if index == 0:
self.prcon.setErrMask(0, 40)
if index == 1:
self.prcon.setErrMask(0.25, 40)
if index == 2:
self.prcon.setErrMask(0.5, 40)
if index == 3:
self.prcon.setErrMask(0.75, 40)
if index == 4:
self.prcon.setErrMask(1, 40)
from litex.soc.tools.remote import RemoteClient
wb = RemoteClient()
wb.open()
# # #
identifier = ""
for i in range(30):
identifier += chr(wb.read(wb.bases.identifier_mem + 4 *
(i + 1))) # TODO: why + 1?
print(identifier)
print("frequency : {}MHz".format(wb.constants.system_clock_frequency /
1000000))
SRAM_BASE = 0x02000000
wb.write(SRAM_BASE, [i for i in range(64)])
print(wb.read(SRAM_BASE, 64))
# # #
wb.close()
from litex.soc.tools.remote import RemoteClient
wb = RemoteClient()
wb.open()
# # #
identifier = ""
for i in range(30):
identifier += chr(wb.read(wb.bases.identifier_mem + 4*(i+1))) # TODO: why + 1?
print(identifier)
print("frequency : {}MHz".format(wb.constants.system_clock_frequency/1000000))
# # #
wb.close()
l.set_ydata(dat)
return l
ani = FuncAnimation(gcf(), update, interval=1000)
return ani
def startAni2():
xdata = arange(128)
ydata = zeros(128)
ydata[1] = 4096
l, = plot(xdata, ydata, "-o")
def update(frame):
b = s.read_until(b"\x42")
if len(b) == 257:
dat = fromstring(b[1:], dtype=uint16)
l.set_ydata(dat)
else:
print("E", end="", flush=True)
return l
ani = FuncAnimation(gcf(), update, interval=10)
return ani
ws = RemoteClient(csr_csv="./build/csr.csv")
atexit.register(ws.close)
ws.open()
print("ws.regs.")
for k in ws.regs.__dict__.keys():
print(k)
s = Serial("/dev/ttyUSB0", 115200)
atexit.register(s.close)
#!/usr/bin/env python3
from litex.soc.tools.remote import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver
wb = RemoteClient("192.168.1.50", 1234, debug=False)
wb.open()
# # #
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
analyzer.configure_trigger(cond={})
analyzer.configure_subsampler(1)
analyzer.run(offset=16, length=1024)
while not analyzer.done():
pass
analyzer.upload()
analyzer.save("dump.vcd")
# # #
wb.close()
import time
from litex.soc.tools.remote import RemoteClient
wb = RemoteClient(debug=True, csr_data_width=8)
wb.open()
regs = wb.regs
def config_720p60(bpp):
regs.hdmi_out0_core_initiator_hres.write(1280)
regs.hdmi_out0_core_initiator_hsync_start.write(1390)
regs.hdmi_out0_core_initiator_hsync_end.write(1430)
regs.hdmi_out0_core_initiator_hscan.write(1650)
regs.hdmi_out0_core_initiator_vres.write(720)
regs.hdmi_out0_core_initiator_vsync_start.write(725)
regs.hdmi_out0_core_initiator_vsync_end.write(730)
regs.hdmi_out0_core_initiator_vscan.write(750)
regs.hdmi_out0_core_initiator_enable.write(0)
regs.hdmi_out0_core_initiator_base.write(0x02000000)
regs.hdmi_out0_core_initiator_length.write(1280*720*bpp)
time.sleep(1)
regs.hdmi_out0_core_initiator_enable.write(1)
# # #
config_720p60(2)
# # #
from litex.soc.tools.remote import RemoteClient from control_prbs import * wb = RemoteClient() wb.open() prcon = PRBSControl(wb.regs, "top_gtp") prcon.phaseAlign() prcon.setErrMask(0, 20) prcon.setPRBSConfig(7, 7) print(prcon.calcBERabs(5, 20)) prcon.setErrMask(0.5, 20) print(prcon.calcBERabs(5, 20)) prcon.resetTx() prcon.resetRx() prcon.phaseAlign() prcon.setPRBSConfig(7, 7) print(prcon.calcBERabs(5, 20)) prcon.setErrMask(0.5, 20) print(prcon.calcBERabs(5, 20)) prcon.PLLlockStatus()
#!/usr/bin/env python3
from litex.soc.tools.remote import RemoteClient
wb = RemoteClient(port=1235, debug=False)
wb.open()
# # #
fpga_id = ""
for i in range(256):
c = chr(wb.read(wb.bases.identifier_mem + 4 * i) & 0xff)
fpga_id += c
if c == "\0":
break
print("fpga_id:" + fpga_id)
# # #
wb.close()
#!/usr/bin/env python3
from litex.soc.tools.remote import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver
wb = RemoteClient("192.168.1.50", 1234, csr_data_width=8)
wb.open()
# # #
logic_analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
cond = {}
logic_analyzer.configure_trigger(cond=cond)
logic_analyzer.run(offset=256, length=2048)
while not logic_analyzer.done():
pass
logic_analyzer.upload()
logic_analyzer.save("dump.vcd")
# # #
wb.close()
#!/usr/bin/env python3
import time
from litex.soc.tools.remote import RemoteClient
wb = RemoteClient()
wb.open()
#print("trigger_mem_full: ")
#t = wb.read(0xe000b838)
#print(t)
print("Temperature: ")
t = wb.read(0xe0005800)
t <<= 8
t |= wb.read(0xe0005804)
print(t * 503.975 / 4096 - 273.15, "C")
print("VCCint: ")
t = wb.read(0xe0005808)
t <<= 8
t |= wb.read(0xe000580c)
print(t / 0x555, "V")
print("VCCaux: ")
t = wb.read(0xe0005810)
t <<= 8
t |= wb.read(0xe0005814)
print(t / 0x555, "V")
print("VCCbram: ")
#!/usr/bin/env python3
import sys
from litex.soc.tools.remote import RemoteClient
from litejesd204b.common import *
from libbase.ad9154 import *
wb_amc = RemoteClient(port=1234, csr_csv="../sayma_amc/csr.csv", debug=False)
wb_rtm = RemoteClient(port=1235, csr_csv="../sayma_rtm/csr.csv", debug=False)
wb_amc.open()
wb_rtm.open()
# # #
# jesd settings
ps = JESD204BPhysicalSettings(l=8, m=4, n=16, np=16)
ts = JESD204BTransportSettings(f=2, s=2, k=16, cs=0)
jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
# configure tx electrical settings
for i in range(8):
produce_square_wave = getattr(
wb_amc.regs,
"dac0_core_phy{:d}_transmitter_produce_square_wave".format(i))
txdiffctrl = getattr(wb_amc.regs,
"dac0_core_phy{:d}_transmitter_txdiffcttrl".format(i))
txmaincursor = getattr(
wb_amc.regs, "dac0_core_phy{:d}_transmitter_txmaincursor".format(i))
txprecursor = getattr(
#!/usr/bin/env python3
from litex.soc.tools.remote import RemoteClient
rom_base = 0x00000000
dump_size = 0x8000
words_per_packet = 128
wb = RemoteClient()
wb.open()
# # #
print("dumping cpu rom to dump.bin...")
dump = []
for n in range(dump_size // (words_per_packet * 4)):
dump += wb.read(rom_base + n * words_per_packet * 4, words_per_packet)
f = open("dump.bin", "wb")
for v in dump:
f.write(v.to_bytes(4, byteorder="big"))
f.close()
# # #
wb.close()
from litex.soc.tools.remote import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver
wb = RemoteClient()
wb.open()
# # #
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
analyzer.configure_trigger(cond={"s7pciephy_sink_valid": 1})
#analyzer.configure_trigger(cond={})
analyzer.configure_subsampler(1)
analyzer.run(offset=16, length=64)
analyzer.wait_done()
analyzer.upload()
analyzer.save("dump.vcd")
# # #
wb.close()
from litex.soc.tools.remote import RemoteClient
wb = RemoteClient()
wb.open()
# # #
identifier = ""
for i in range(30):
identifier += chr(wb.read(wb.bases.identifier_mem + 4*(i+1))) # TODO: why + 1?
print(identifier)
print("frequency : {}MHz".format(wb.constants.system_clock_frequency/1000000))
SRAM_BASE = 0x02000000
wb.write(SRAM_BASE, [i for i in range(64)])
print(wb.read(SRAM_BASE, 64))
# # #
wb.close()
#!/usr/bin/env python3
import sys
sys.path.insert(0, '/opt')
from litex.soc.tools.remote import RemoteClient
wb = RemoteClient()
wb.open()
# # #
# get identifier
fpga_id = ""
for i in range(256):
c = chr(wb.read(wb.bases.identifier_mem + 4 * i) & 0xff)
fpga_id += c
if c == "\0":
break
print("fpga_id: " + fpga_id)
# # #
wb.close()
#!/usr/bin/env python3
import time
import sys
sys.path.append("../")
from litex.soc.tools.remote import RemoteClient
wb = RemoteClient("192.168.1.50", 1234)
wb.open()
# # #
# test uart
for c in "hello world from host\n":
wb.regs.uart_rxtx.write(ord(c))
# # #
wb.close()