def main():
parser = argparse.ArgumentParser(
description="LiteSATA bench on Acorn CLE 215+")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load",
action="store_true",
help="Load bitstream (to SRAM)")
parser.add_argument("--gen",
default="3",
help="SATA Gen: 1, 2 or 3 (default)")
parser.add_argument("--with-analyzer",
action="store_true",
help="Add LiteScope Analyzer")
args = parser.parse_args()
platform = acorn.Platform()
platform.add_extension(_sata_io)
soc = SATATestSoC(platform,
"gen" + args.gen,
with_analyzer=args.with_analyzer)
builder = Builder(soc, csr_csv="csr.csv")
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def __init__(self,
variant="cle-215+",
sys_clk_freq=int(100e6),
with_led_chaser=True,
with_pcie=False,
with_sata=False,
**kwargs):
platform = acorn.Platform(variant=variant)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="LiteX SoC on Acorn CLE-101/215(+)",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq,
iodelay_clk_freq=200e6)
self.add_sdram("sdram",
phy=self.ddrphy,
module=MT41K512M16(sys_clk_freq, "1:4"),
l2_cache_size=kwargs.get("l2_size", 8192))
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x4"),
data_width=128,
bar0_size=0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# FIXME: Apply it to all targets (integrate it in LitePCIe?).
platform.add_period_constraint(self.crg.cd_sys.clk,
1e9 / sys_clk_freq)
platform.toolchain.pre_placement_commands.add(
"set_clock_groups -group [get_clocks {sys_clk}] -group [get_clocks userclk2] -asynchronous",
sys_clk=self.crg.cd_sys.clk)
platform.toolchain.pre_placement_commands.add(
"set_clock_groups -group [get_clocks {sys_clk}] -group [get_clocks clk_125mhz] -asynchronous",
sys_clk=self.crg.cd_sys.clk)
platform.toolchain.pre_placement_commands.add(
"set_clock_groups -group [get_clocks {sys_clk}] -group [get_clocks clk_250mhz] -asynchronous",
sys_clk=self.crg.cd_sys.clk)
platform.toolchain.pre_placement_commands.add(
"set_clock_groups -group [get_clocks clk_125mhz] -group [get_clocks clk_250mhz] -asynchronous"
)
# ICAP (For FPGA reload over PCIe).
from litex.soc.cores.icap import ICAP
self.submodules.icap = ICAP()
self.icap.add_reload()
self.icap.add_timing_constraints(platform, sys_clk_freq,
self.crg.cd_sys.clk)
# Flash (For SPIFlash update over PCIe).
from litex.soc.cores.gpio import GPIOOut
from litex.soc.cores.spi_flash import S7SPIFlash
self.submodules.flash_cs_n = GPIOOut(
platform.request("flash_cs_n"))
self.submodules.flash = S7SPIFlash(platform.request("flash"),
sys_clk_freq, 25e6)
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litesata.phy import LiteSATAPHY
# IOs
_sata_io = [
# PCIe 2 SATA Custom Adapter (With PCIe Riser / SATA cable mod).
(
"pcie2sata",
0,
Subsignal("tx_p", Pins("B6")),
Subsignal("tx_n", Pins("A6")),
Subsignal("rx_p", Pins("B10")),
Subsignal("rx_n", Pins("A10")),
),
]
platform.add_extension(_sata_io)
# RefClk, Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
platform.add_platform_command(
"set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(
platform.device,
refclk=sata_refclk,
pads=platform.request("pcie2sata"),
gen="gen1",
clk_freq=sys_clk_freq,
data_width=16)
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads=platform.request_all("user_led"),
sys_clk_freq=sys_clk_freq)