class FastModelCortexR52(IrisBaseCPU):
type = 'FastModelCortexR52'
cxx_class = 'FastModel::CortexR52'
cxx_header = 'arch/arm/fastmodel/CortexR52/cortex_r52.hh'
evs = Parent.evs
ppi = VectorIntSinkPin('PPI inputs (0-8)')
llpp = AmbaInitiatorSocket(64, 'Low Latency Peripheral Port')
flash = AmbaInitiatorSocket(64, 'Flash')
amba = AmbaInitiatorSocket(64, 'AMBA initiator socket')
CFGEND = Param.Bool(False, "Endianness configuration at reset. 0, " \
"little endian. 1, big endian.")
CFGTE = Param.Bool(False, "Equivalent to CFGTHUMBEXCEPTIONS")
RVBARADDR = Param.UInt32(0, "Equivalent to CFGVECTABLE")
ase_present = Param.Bool(True, "Set whether the model has been built " \
"with NEON support")
dcache_size = Param.UInt16(0x8000, "L1 D-Cache size in bytes")
flash_enable = Param.Bool(False, "Equivalent to CFGFLASHEN")
icache_size = Param.UInt16(0x8000, "L1 I-Cache size in bytes")
llpp_base = Param.UInt32(0, "Equivalent to CFGLLPPBASEADDR")
llpp_size = Param.UInt32(0x1000, "Equivalent to CFGLLPPSIZE")
max_code_cache_mb = Param.UInt64(0x100, "Maximum size of the " \
"simulation code cache (MiB). For platforms with more than 2 " \
"cores this limit will be scaled down. (e.g 1/8 for 16 or more " \
"cores).")
min_sync_level = Param.UInt8(0, "Force minimum syncLevel " \
"(0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)")
semihosting_A32_HLT = Param.UInt16(0xf000, "A32 HLT number for " \
"semihosting calls.")
semihosting_ARM_SVC = Param.UInt32(0x123456, "A32 SVC number for " \
"semihosting calls.")
semihosting_T32_HLT = Param.UInt8(60, "T32 HLT number for semihosting " \
"calls.")
semihosting_Thumb_SVC = Param.UInt8(171, "T32 SVC number for " \
"semihosting calls.")
semihosting_cmd_line = Param.String("", "Command line available to " \
"semihosting calls.")
semihosting_cwd = Param.String("", "Base directory for semihosting " \
"file access.")
semihosting_enable = Param.Bool(True, "Enable semihosting SVC/HLT traps.")
semihosting_heap_base = Param.UInt32(0, "Virtual address of heap base.")
semihosting_heap_limit = Param.UInt32(0xf000000, "Virtual address of " \
"top of heap.")
semihosting_stack_base = Param.UInt32(0x10000000, "Virtual address of " \
"base of descending stack.")
semihosting_stack_limit = Param.UInt32(0xf000000, "Virtual address of " \
"stack limit.")
tcm_a_enable = Param.Bool(False, "Equivalent to CFGTCMBOOT")
tcm_a_size = Param.UInt32(0x4000, "Sets the size of the ATCM(in bytes)")
tcm_b_size = Param.UInt32(0x4000, "Sets the size of the BTCM(in bytes)")
tcm_c_size = Param.UInt32(0x2000, "Sets the size of the CTCM(in bytes)")
vfp_dp_present = Param.Bool(True, "Whether double-precision floating " \
"point feature is implemented")
vfp_enable_at_reset = Param.Bool(False, "Enable VFP in CPACR, CPPWR, " \
"NSACR at reset. Warning: Arm recommends going through the "
"implementation's suggested VFP power-up sequence!")
class FastModelGIC(BaseGic):
type = 'FastModelGIC'
cxx_class = 'FastModel::GIC'
cxx_header = 'arch/arm/fastmodel/GIC/gic.hh'
sc_gic = Param.SCFastModelGIC(SCFastModelGIC(),
'SystemC version of the GIC')
amba_m = AmbaInitiatorSocket(64, 'Memory initiator socket')
amba_s = AmbaTargetSocket(64, 'Memory target socket')
redistributor = Gicv3CommsInitiatorSocket('GIC communication initiator')
class FastModelGIC(BaseGic):
type = 'FastModelGIC'
cxx_class = 'FastModel::GIC'
cxx_header = 'arch/arm/fastmodel/GIC/gic.hh'
sc_gic = Param.SCFastModelGIC(SCFastModelGIC(),
'SystemC version of the GIC')
amba_m = AmbaInitiatorSocket(64, 'Memory initiator socket')
amba_s = AmbaTargetSocket(64, 'Memory target socket')
redistributor = VectorGicv3CommsInitiatorSocket(
'GIC communication initiator')
def get_redist_bases(self):
"""
The format of reg_base_per_redistributor is
'0.0.0.0=0x2c010000,0.0.0.1=0x2c020000...'
Return an array of base addresses
"""
redists = self.sc_gic.reg_base_per_redistributor.split(",")
# make sure we have at least one redistributor
assert len(redists) > 0 and "=" in redists[0]
return [int(r.split('=')[1], 16) for r in redists]
def get_addr_ranges(self):
""" Return address ranges that should be served by this GIC """
sc_gic = self.sc_gic
gic_frame_size = 0x10000
# Add range of distributor
ranges = [AddrRange(sc_gic.reg_base, size=gic_frame_size)]
# Add ranges of redistributors
redist_frame_size = gic_frame_size * (4 if sc_gic.has_gicv4_1 else 2)
ranges += [
AddrRange(redist_base, size=redist_frame_size)
for redist_base in self.get_redist_bases()
]
# Add ranges of ITSs
its_bases = [
sc_gic.its0_base, sc_gic.its1_base, sc_gic.its2_base,
sc_gic.its3_base
]
ranges += [
AddrRange(its_bases[i], size=2 * gic_frame_size)
for i in xrange(sc_gic.its_count)
]
return ranges
class FastModelGIC(BaseGic):
type = 'FastModelGIC'
cxx_class = 'FastModel::GIC'
cxx_header = 'arch/arm/fastmodel/GIC/gic.hh'
sc_gic = Param.SCFastModelGIC(SCFastModelGIC(),
'SystemC version of the GIC')
amba_m = AmbaInitiatorSocket(64, 'Memory initiator socket')
amba_s = AmbaTargetSocket(64, 'Memory target socket')
redistributor_m = Gicv3CommsInitiatorSocket('GIC communication initiator')
redistributor_s = Gicv3CommsTargetSocket('GIC communication target')
cnthpirq = ScSlavePort("Slave port for CPU-to-GIC signal", "bool")
cnthvirq = ScSlavePort("Slave port for CPU-to-GIC signal", "bool")
cntpsirq = ScSlavePort("Slave port for CPU-to-GIC signal", "bool")
cntvirq = ScSlavePort("Slave port for CPU-to-GIC signal", "bool")
commirq = ScSlavePort("Slave port for CPU-to-GIC signal", "bool")
ctidbgirq = ScSlavePort("Slave port for CPU-to-GIC signal", "bool")
pmuirq = ScSlavePort("Slave port for CPU-to-GIC signal", "bool")
vcpumntirq = ScSlavePort("Slave port for CPU-to-GIC signal", "bool")
cntpnsirq = ScSlavePort("Slave port for CPU-to-GIC signal", "bool")
class FastModelGIC(BaseGic):
type = 'FastModelGIC'
cxx_class = 'FastModel::GIC'
cxx_header = 'arch/arm/fastmodel/GIC/gic.hh'
sc_gic = Param.SCFastModelGIC(SCFastModelGIC(),
'SystemC version of the GIC')
amba_m = AmbaInitiatorSocket(64, 'Memory initiator socket')
amba_s = AmbaTargetSocket(64, 'Memory target socket')
redistributor = VectorGicv3CommsInitiatorSocket(
'GIC communication initiator')
# Used for DTB autogeneration
_state = FdtState(addr_cells=2, size_cells=2, interrupt_cells=3)
def get_redist_bases(self):
"""
The format of reg_base_per_redistributor is
'0.0.0.0=0x2c010000,0.0.0.1=0x2c020000...'
Return an array of base addresses
"""
redists = self.sc_gic.reg_base_per_redistributor.split(",")
# make sure we have at least one redistributor
assert len(redists) > 0 and "=" in redists[0]
return [int(r.split('=')[1], 16) for r in redists]
def get_addr_ranges(self):
""" Return address ranges that should be served by this GIC """
sc_gic = self.sc_gic
gic_frame_size = 0x10000
# Add range of distributor
ranges = [AddrRange(sc_gic.reg_base, size=gic_frame_size)]
# Add ranges of redistributors
redist_frame_size = gic_frame_size * (4 if sc_gic.has_gicv4_1 else 2)
ranges += [
AddrRange(redist_base, size=redist_frame_size)
for redist_base in self.get_redist_bases()
]
# Add ranges of ITSs
its_bases = [
sc_gic.its0_base, sc_gic.its1_base, sc_gic.its2_base,
sc_gic.its3_base
]
ranges += [
AddrRange(its_bases[i], size=2 * gic_frame_size)
for i in xrange(sc_gic.its_count)
]
return ranges
def interruptCells(self, int_type, int_num, int_flag):
"""
Interupt cells generation helper:
Following specifications described in
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
"""
prop = self._state.interruptCells(0)
assert len(prop) >= 3
prop[0] = int_type
prop[1] = int_num
prop[2] = int_flag
return prop
def generateDeviceTree(self, state):
sc_gic = self.sc_gic
node = FdtNode("interrupt-controller")
node.appendCompatible(["arm,gic-v3"])
node.append(self._state.interruptCellsProperty())
node.append(self._state.addrCellsProperty())
node.append(self._state.sizeCellsProperty())
node.append(FdtProperty("ranges"))
node.append(FdtProperty("interrupt-controller"))
redist_stride = 0x40000 if sc_gic.has_gicv4_1 else 0x20000
node.append(
FdtPropertyWords("redistributor-stride",
state.sizeCells(redist_stride)))
regs = (state.addrCells(sc_gic.reg_base) + state.sizeCells(0x10000) +
state.addrCells(self.get_redist_bases()[0]) +
state.sizeCells(0x2000000))
node.append(FdtPropertyWords("reg", regs))
# Maintenance interrupt (PPI 25).
node.append(
FdtPropertyWords("interrupts", self.interruptCells(1, 9, 0xf04)))
node.appendPhandle(self)
# Generate the ITS device tree
its_frame_size = 0x10000
its_bases = [
sc_gic.its0_base, sc_gic.its1_base, sc_gic.its2_base,
sc_gic.its3_base
]
for its_base in its_bases:
its_node = self.generateBasicPioDeviceNode(state, "gic-its",
its_base,
2 * its_frame_size)
its_node.appendCompatible(["arm,gic-v3-its"])
its_node.append(FdtProperty("msi-controller"))
its_node.append(FdtPropertyWords("#msi-cells", [1]))
node.append(its_node)
yield node
class FastModelCortexA76Cluster(SimObject):
type = 'FastModelCortexA76Cluster'
cxx_class = 'gem5::fastmodel::CortexA76Cluster'
cxx_header = 'arch/arm/fastmodel/CortexA76/cortex_a76.hh'
cores = VectorParam.FastModelCortexA76(
'Core in a given cluster of CortexA76s')
evs = Param.SystemC_ScModule(
"Fast mo0del exported virtual subsystem holding cores")
cnthpirq = Param.ArmInterruptPin(ArmPPI(num=10),
"EL2 physical timer event")
cnthvirq = Param.ArmInterruptPin(ArmPPI(num=12), "EL2 virtual timer event")
cntpsirq = Param.ArmInterruptPin(ArmPPI(num=13),
"EL1 Secure physical timer event")
cntvirq = Param.ArmInterruptPin(ArmPPI(num=11), "Virtual timer event")
commirq = Param.ArmInterruptPin(
ArmPPI(num=6), "Interrupt signal from debug communications channel")
ctidbgirq = Param.ArmInterruptPin(
ArmPPI(num=8),
"Cross Trigger Interface (CTI) interrupt trigger output")
pmuirq = Param.ArmInterruptPin(
ArmPPI(num=7), "Interrupt from performance monitoring unit")
vcpumntirq = Param.ArmInterruptPin(
ArmPPI(num=9), "Interrupt signal for virtual CPU maintenance IRQ")
cntpnsirq = Param.ArmInterruptPin(ArmPPI(num=14),
"Non-secure physical timer event")
amba = AmbaInitiatorSocket(64, 'AMBA initiator socket')
# These parameters are described in "Fast Models Reference Manual" section
# 3.4.19, "ARMCortexA7x1CT".
BROADCASTATOMIC = Param.Bool(True, "Enable broadcasting of atomic "\
"operation. The broadcastatomic signal will override this value "\
"if used")
BROADCASTCACHEMAINT = Param.Bool(True, "Enable broadcasting of cache "\
"maintenance operations to downstream caches. The "\
"broadcastcachemaint signal will override this value if used.")
BROADCASTOUTER = Param.Bool(True, "Enable broadcasting of Outer "\
"Shareable transactions. The broadcastouter signal will override "\
"this value if used.")
BROADCASTPERSIST = Param.Bool(True, "Enable broadcasting of cache clean "\
"to the point of persistence operations. The broadcastpersist "\
"signal will override this value if used")
CLUSTER_ID = Param.UInt16(0x0, "Processor cluster ID value")
GICDISABLE = Param.Bool(True, "Disable the new style GICv3 CPU interface "\
"in each core model. Should be left enabled unless the platform "\
"contains a GICv3 distributor.")
cpi_div = Param.UInt32(
1, "Divider for calculating CPI (Cycles Per Instruction)")
cpi_mul = Param.UInt32(
1, "Multiplier for calculating CPI (Cycles Per Instruction)")
dcache_hit_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\
"latency for hit. Intended to model the tag-lookup time. This "\
"is only used when dcache-state_modelled=true.")
dcache_maintenance_latency = Param.UInt64(0, "L1 D-Cache timing "\
"annotation latency for cache maintenance operations given in "\
"total ticks. This is only used when dcache-state_modelled=true.")
dcache_miss_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\
"latency for miss. Intended to model the time for failed "\
"tag-lookup and allocation of intermediate buffers. This is "\
"only used when dcache-state_modelled=true.")
dcache_prefetch_enabled = Param.Bool(False, "Enable simulation of data "\
"cache prefetching. This is only used when "\
"dcache-state_modelled=true")
dcache_read_access_latency = Param.UInt64(0, "L1 D-Cache timing "\
"annotation latency for read accesses given in ticks per access "\
"(of size dcache-read_bus_width_in_bytes). If this parameter is "\
"non-zero, per-access latencies will be used instead of per-byte "\
"even if dcache-read_latency is set. This is in addition to the "\
"hit or miss latency, and intended to correspond to the time "\
"taken to transfer across the cache upstream bus, this is only "\
"used when dcache-state_modelled=true.")
dcache_read_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\
"latency for read accesses given in ticks per byte "\
"accessed.dcache-read_access_latency must be set to 0 for "\
"per-byte latencies to be applied. This is in addition to the "\
"hit or miss latency, and intended to correspond to the time "\
"taken to transfer across the cache upstream bus. This is only "\
"used when dcache-state_modelled=true.")
dcache_snoop_data_transfer_latency = Param.UInt64(0, "L1 D-Cache timing "\
"annotation latency for received snoop accesses that perform a data "\
"transfer given in ticks per byte accessed. This is only used when "\
"dcache-state_modelled=true.")
dcache_state_modelled = Param.Bool(
False, "Set whether D-cache has stateful implementation")
dcache_write_access_latency = Param.UInt64(0, "L1 D-Cache timing "\
"annotation latency for write accesses given in ticks per access "\
"(of size dcache-write_bus_width_in_bytes). If this parameter is "\
"non-zero, per-access latencies will be used instead of per-byte "\
"even if dcache-write_latency is set. This is only used when "\
"dcache-state_modelled=true.")
dcache_write_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\
"latency for write accesses given in ticks per byte accessed. "\
"dcache-write_access_latency must be set to 0 for per-byte latencies "\
"to be applied. This is only used when dcache-state_modelled=true.")
default_opmode = Param.Unsigned(4, "Operating mode of DynamIQ coming out "\
"of reset. 0: SFONLY ON, 1: 1/4 CACHE ON, 2: 1/2 CACHE ON, 3: "\
"3/4 CACHE ON, 4: FULL CACHE ON")
diagnostics = Param.Bool(False, "Enable DynamIQ diagnostic messages")
enable_simulation_performance_optimizations = Param.Bool(True,
"With this option enabled, the model will run more quickly, but "\
"be less accurate to exact CPU behavior. The model will still be "\
"functionally accurate for software, but may increase "\
"differences seen between hardware behavior and model behavior "\
"for certain workloads (it changes the micro-architectural value "\
"of stage12_tlb_size parameter to 1024).")
ext_abort_device_read_is_sync = Param.Bool(
False, "Synchronous reporting of device-nGnRE read external aborts")
ext_abort_device_write_is_sync = Param.Bool(
False, "Synchronous reporting of device-nGnRE write external aborts")
ext_abort_so_read_is_sync = Param.Bool(
False, "Synchronous reporting of device-nGnRnE read external aborts")
ext_abort_so_write_is_sync = Param.Bool(
False, "Synchronous reporting of device-nGnRnE write external aborts")
gicv3_cpuintf_mmap_access_level = Param.Unsigned(0, "Allowed values are: "\
"0-mmap access is supported for GICC,GICH,GICV registers. 1-mmap "\
"access is supported only for GICV registers. 2-mmap access is "\
"not supported.")
has_peripheral_port = Param.Bool(
False, "If true, additional AXI peripheral port is configured.")
has_statistical_profiling = Param.Bool(
True, "Whether Statistical Based Profiling is implemented")
icache_hit_latency = Param.UInt64(0, "L1 I-Cache timing annotation "\
"latency for hit. Intended to model the tag-lookup time. This "\
"is only used when icache-state_modelled=true.")
icache_maintenance_latency = Param.UInt64(0, "L1 I-Cache timing "\
"annotation latency for cache maintenance operations given in "\
"total ticks. This is only used when icache-state_modelled=true.")
icache_miss_latency = Param.UInt64(0, "L1 I-Cache timing annotation "\
"latency for miss. Intended to model the time for failed "\
"tag-lookup and allocation of intermediate buffers. This is "\
"only used when icache-state_modelled=true.")
icache_prefetch_enabled = Param.Bool(False, "Enable simulation of "\
"instruction cache prefetching. This is only used when "\
"icache-state_modelled=true.")
icache_read_access_latency = Param.UInt64(0, "L1 I-Cache timing "\
"annotation latency for read accesses given in ticks per access "\
"(of size icache-read_bus_width_in_bytes). If this parameter is "\
"non-zero, per-access latencies will be used instead of per-byte "\
"even if icache-read_latency is set. This is in addition to the "\
"hit or miss latency, and intended to correspond to the time "\
"taken to transfer across the cache upstream bus, this is only "\
"used when icache-state_modelled=true.")
icache_read_latency = Param.UInt64(0, "L1 I-Cache timing annotation "\
"latency for read accesses given in ticks per byte "\
"accessed.icache-read_access_latency must be set to 0 for "\
"per-byte latencies to be applied. This is in addition to the "\
"hit or miss latency, and intended to correspond to the time "\
"taken to transfer across the cache upstream bus. This is only "\
"used when icache-state_modelled=true.")
icache_state_modelled = Param.Bool(
False, "Set whether I-cache has stateful implementation")
l3cache_hit_latency = Param.UInt64(0, "L3 Cache timing annotation "\
"latency for hit. Intended to model the tag-lookup time. This "\
"is only used when l3cache-state_modelled=true.")
l3cache_maintenance_latency = Param.UInt64(0, "L3 Cache timing "\
"annotation latency for cache maintenance operations given in "\
"total ticks. This is only used when dcache-state_modelled=true.")
l3cache_miss_latency = Param.UInt64(0, "L3 Cache timing annotation "\
"latency for miss. Intended to model the time for failed "\
"tag-lookup and allocation of intermediate buffers. This is "\
"only used when l3cache-state_modelled=true.")
l3cache_read_access_latency = Param.UInt64(0, "L3 Cache timing "\
"annotation latency for read accesses given in ticks per access "\
"(of size l3cache-read_bus_width_in_bytes). If this parameter "\
"is non-zero, per-access latencies will be used instead of "\
"per-byte even if l3cache-read_latency is set. This is in "\
"addition to the hit or miss latency, and intended to correspond "\
"to the time taken to transfer across the cache upstream bus, "\
"this is only used when l3cache-state_modelled=true.")
l3cache_read_latency = Param.UInt64(0, "L3 Cache timing annotation "\
"latency for read accesses given in ticks per byte "\
"accessed.l3cache-read_access_latency must be set to 0 for "\
"per-byte latencies to be applied. This is in addition to the "\
"hit or miss latency, and intended to correspond to the time "\
"taken to transfer across the cache upstream bus. This is only "\
"used when l3cache-state_modelled=true.")
l3cache_size = Param.MemorySize('0x100000', "L3 Cache size in bytes.")
l3cache_snoop_data_transfer_latency = Param.UInt64(0, "L3 Cache timing "\
"annotation latency for received snoop accesses that perform a "\
"data transfer given in ticks per byte accessed. This is only "\
"used when dcache-state_modelled=true.")
l3cache_snoop_issue_latency = Param.UInt64(0, "L3 Cache timing "\
"annotation latency for snoop accesses issued by this cache in "\
"total ticks. This is only used when dcache-state_modelled=true.")
l3cache_write_access_latency = Param.UInt64(0, "L3 Cache timing "\
"annotation latency for write accesses given in ticks per access "\
"(of size l3cache-write_bus_width_in_bytes). If this parameter "\
"is non-zero, per-access latencies will be used instead of "\
"per-byte even if l3cache-write_latency is set. This is only "\
"used when l3cache-state_modelled=true.")
l3cache_write_latency = Param.UInt64(0, "L3 Cache timing annotation "\
"latency for write accesses given in ticks per byte accessed. "\
"l3cache-write_access_latency must be set to 0 for per-byte "\
"latencies to be applied. This is only used when "\
"l3cache-state_modelled=true.")
pchannel_treat_simreset_as_poreset = Param.Bool(
False, "Register core as ON state to cluster with simulation reset.")
periph_address_end = Param.Addr(0x0, "End address for peripheral port "\
"address range exclusive(corresponds to AENDMP input signal).")
periph_address_start = Param.Addr(0x0, "Start address for peripheral "\
"port address range inclusive(corresponds to ASTARTMP input "\
"signal).")
ptw_latency = Param.UInt64(0, "Page table walker latency for TA "\
"(Timing Annotation), expressed in simulation ticks")
tlb_latency = Param.UInt64(0, "TLB latency for TA (Timing Annotation), "\
"expressed in simulation ticks")
treat_dcache_cmos_to_pou_as_nop = Param.Bool(False, "Whether dcache "\
"invalidation to the point of unification is required for "\
"instruction to data coherence. true - Invalidate operations not "\
"required")
walk_cache_latency = Param.UInt64(0, "Walk cache latency for TA (Timing "\
"Annotation), expressed in simulation ticks")
def generateDeviceTree(self, state):
node = FdtNode("timer")
node.appendCompatible(
["arm,cortex-a15-timer", "arm,armv7-timer", "arm,armv8-timer"])
node.append(
FdtPropertyWords("interrupts", [
1,
int(self.cntpsirq.num),
0xf08,
1,
int(self.cntpnsirq.num),
0xf08,
1,
int(self.cntvirq.num),
0xf08,
1,
int(self.cnthpirq.num),
0xf08,
]))
yield node
class FastModelCortexA76x1(SystemC_ScModule):
type = 'FastModelCortexA76x1'
cxx_class = 'FastModel::CortexA76x1'
cxx_header = 'arch/arm/fastmodel/CortexA76x1/cortex_a76x1.hh'
_core_paths = ['core.cpu0']
cpu_wrapper = FastModelArmCPU(
core_paths=_core_paths,
cntfrq=0x1800000,
# We shouldn't need these, but gem5 gets mad without them.
interrupts=[ArmInterrupts()],
isa=[ArmISA()],
)
cnthpirq = Param.ArmInterruptPin(ArmPPI(num=10),
"EL2 physical timer event")
cnthvirq = Param.ArmInterruptPin(ArmPPI(num=12), "EL2 virtual timer event")
cntpsirq = Param.ArmInterruptPin(ArmPPI(num=13),
"EL1 Secure physical timer event")
cntvirq = Param.ArmInterruptPin(ArmPPI(num=11), "Virtual timer event")
commirq = Param.ArmInterruptPin(
ArmPPI(num=6), "Interrupt signal from debug communications channel")
ctidbgirq = Param.ArmInterruptPin(
ArmPPI(num=8),
"Cross Trigger Interface (CTI) interrupt trigger output")
pmuirq = Param.ArmInterruptPin(
ArmPPI(num=7), "Interrupt from performance monitoring unit")
vcpumntirq = Param.ArmInterruptPin(
ArmPPI(num=9), "Interrupt signal for virtual CPU maintenance IRQ")
cntpnsirq = Param.ArmInterruptPin(ArmPPI(num=14),
"Non-secure physical timer event")
amba = AmbaInitiatorSocket(64, 'AMBA initiator socket')
redistributor = Gicv3CommsTargetSocket('GIC communication target')
# These parameters are described in "Fast Models Reference Manual" section
# 3.4.19, "ARMCortexA7x1CT".
BROADCASTATOMIC = Param.Bool(True, "Enable broadcasting of atomic "\
"operation. The broadcastatomic signal will override this value "\
"if used")
BROADCASTCACHEMAINT = Param.Bool(True, "Enable broadcasting of cache "\
"maintenance operations to downstream caches. The "\
"broadcastcachemaint signal will override this value if used.")
BROADCASTOUTER = Param.Bool(True, "Enable broadcasting of Outer "\
"Shareable transactions. The broadcastouter signal will override "\
"this value if used.")
BROADCASTPERSIST = Param.Bool(True, "Enable broadcasting of cache clean "\
"to the point of persistence operations. The broadcastpersist "\
"signal will override this value if used")
CLUSTER_ID = Param.UInt16(0x0, "Processor cluster ID value")
GICDISABLE = Param.Bool(True, "Disable the new style GICv3 CPU interface "\
"in each core model. Should be left enabled unless the platform "\
"contains a GICv3 distributor.")
cpi_div = Param.UInt32(
1, "Divider for calculating CPI (Cycles Per Instruction)")
cpi_mul = Param.UInt32(
1, "Multiplier for calculating CPI (Cycles Per Instruction)")
dcache_hit_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\
"latency for hit. Intended to model the tag-lookup time. This "\
"is only used when dcache-state_modelled=true.")
dcache_maintenance_latency = Param.UInt64(0, "L1 D-Cache timing "\
"annotation latency for cache maintenance operations given in "\
"total ticks. This is only used when dcache-state_modelled=true.")
dcache_miss_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\
"latency for miss. Intended to model the time for failed "\
"tag-lookup and allocation of intermediate buffers. This is "\
"only used when dcache-state_modelled=true.")
dcache_prefetch_enabled = Param.Bool(False, "Enable simulation of data "\
"cache prefetching. This is only used when "\
"dcache-state_modelled=true")
dcache_read_access_latency = Param.UInt64(0, "L1 D-Cache timing "\
"annotation latency for read accesses given in ticks per access "\
"(of size dcache-read_bus_width_in_bytes). If this parameter is "\
"non-zero, per-access latencies will be used instead of per-byte "\
"even if dcache-read_latency is set. This is in addition to the "\
"hit or miss latency, and intended to correspond to the time "\
"taken to transfer across the cache upstream bus, this is only "\
"used when dcache-state_modelled=true.")
dcache_read_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\
"latency for read accesses given in ticks per byte "\
"accessed.dcache-read_access_latency must be set to 0 for "\
"per-byte latencies to be applied. This is in addition to the "\
"hit or miss latency, and intended to correspond to the time "\
"taken to transfer across the cache upstream bus. This is only "\
"used when dcache-state_modelled=true.")
dcache_snoop_data_transfer_latency = Param.UInt64(0, "L1 D-Cache timing "\
"annotation latency for received snoop accesses that perform a data "\
"transfer given in ticks per byte accessed. This is only used when "\
"dcache-state_modelled=true.")
dcache_state_modelled = Param.Bool(
False, "Set whether D-cache has stateful implementation")
dcache_write_access_latency = Param.UInt64(0, "L1 D-Cache timing "\
"annotation latency for write accesses given in ticks per access "\
"(of size dcache-write_bus_width_in_bytes). If this parameter is "\
"non-zero, per-access latencies will be used instead of per-byte "\
"even if dcache-write_latency is set. This is only used when "\
"dcache-state_modelled=true.")
dcache_write_latency = Param.UInt64(0, "L1 D-Cache timing annotation "\
"latency for write accesses given in ticks per byte accessed. "\
"dcache-write_access_latency must be set to 0 for per-byte latencies "\
"to be applied. This is only used when dcache-state_modelled=true.")
default_opmode = Param.Unsigned(4, "Operating mode of DynamIQ coming out "\
"of reset. 0: SFONLY ON, 1: 1/4 CACHE ON, 2: 1/2 CACHE ON, 3: "\
"3/4 CACHE ON, 4: FULL CACHE ON")
diagnostics = Param.Bool(False, "Enable DynamIQ diagnostic messages")
enable_simulation_performance_optimizations = Param.Bool(True,
"With this option enabled, the model will run more quickly, but "\
"be less accurate to exact CPU behavior. The model will still be "\
"functionally accurate for software, but may increase "\
"differences seen between hardware behavior and model behavior "\
"for certain workloads (it changes the micro-architectural value "\
"of stage12_tlb_size parameter to 1024).")
ext_abort_device_read_is_sync = Param.Bool(
False, "Synchronous reporting of device-nGnRE read external aborts")
ext_abort_device_write_is_sync = Param.Bool(
False, "Synchronous reporting of device-nGnRE write external aborts")
ext_abort_so_read_is_sync = Param.Bool(
False, "Synchronous reporting of device-nGnRnE read external aborts")
ext_abort_so_write_is_sync = Param.Bool(
False, "Synchronous reporting of device-nGnRnE write external aborts")
gicv3_cpuintf_mmap_access_level = Param.Unsigned(0, "Allowed values are: "\
"0-mmap access is supported for GICC,GICH,GICV registers. 1-mmap "\
"access is supported only for GICV registers. 2-mmap access is "\
"not supported.")
has_peripheral_port = Param.Bool(
False, "If true, additional AXI peripheral port is configured.")
has_statistical_profiling = Param.Bool(
True, "Whether Statistical Based Profiling is implemented")
icache_hit_latency = Param.UInt64(0, "L1 I-Cache timing annotation "\
"latency for hit. Intended to model the tag-lookup time. This "\
"is only used when icache-state_modelled=true.")
icache_maintenance_latency = Param.UInt64(0, "L1 I-Cache timing "\
"annotation latency for cache maintenance operations given in "\
"total ticks. This is only used when icache-state_modelled=true.")
icache_miss_latency = Param.UInt64(0, "L1 I-Cache timing annotation "\
"latency for miss. Intended to model the time for failed "\
"tag-lookup and allocation of intermediate buffers. This is "\
"only used when icache-state_modelled=true.")
icache_prefetch_enabled = Param.Bool(False, "Enable simulation of "\
"instruction cache prefetching. This is only used when "\
"icache-state_modelled=true.")
icache_read_access_latency = Param.UInt64(0, "L1 I-Cache timing "\
"annotation latency for read accesses given in ticks per access "\
"(of size icache-read_bus_width_in_bytes). If this parameter is "\
"non-zero, per-access latencies will be used instead of per-byte "\
"even if icache-read_latency is set. This is in addition to the "\
"hit or miss latency, and intended to correspond to the time "\
"taken to transfer across the cache upstream bus, this is only "\
"used when icache-state_modelled=true.")
icache_read_latency = Param.UInt64(0, "L1 I-Cache timing annotation "\
"latency for read accesses given in ticks per byte "\
"accessed.icache-read_access_latency must be set to 0 for "\
"per-byte latencies to be applied. This is in addition to the "\
"hit or miss latency, and intended to correspond to the time "\
"taken to transfer across the cache upstream bus. This is only "\
"used when icache-state_modelled=true.")
icache_state_modelled = Param.Bool(
False, "Set whether I-cache has stateful implementation")
l3cache_hit_latency = Param.UInt64(0, "L3 Cache timing annotation "\
"latency for hit. Intended to model the tag-lookup time. This "\
"is only used when l3cache-state_modelled=true.")
l3cache_maintenance_latency = Param.UInt64(0, "L3 Cache timing "\
"annotation latency for cache maintenance operations given in "\
"total ticks. This is only used when dcache-state_modelled=true.")
l3cache_miss_latency = Param.UInt64(0, "L3 Cache timing annotation "\
"latency for miss. Intended to model the time for failed "\
"tag-lookup and allocation of intermediate buffers. This is "\
"only used when l3cache-state_modelled=true.")
l3cache_read_access_latency = Param.UInt64(0, "L3 Cache timing "\
"annotation latency for read accesses given in ticks per access "\
"(of size l3cache-read_bus_width_in_bytes). If this parameter "\
"is non-zero, per-access latencies will be used instead of "\
"per-byte even if l3cache-read_latency is set. This is in "\
"addition to the hit or miss latency, and intended to correspond "\
"to the time taken to transfer across the cache upstream bus, "\
"this is only used when l3cache-state_modelled=true.")
l3cache_read_latency = Param.UInt64(0, "L3 Cache timing annotation "\
"latency for read accesses given in ticks per byte "\
"accessed.l3cache-read_access_latency must be set to 0 for "\
"per-byte latencies to be applied. This is in addition to the "\
"hit or miss latency, and intended to correspond to the time "\
"taken to transfer across the cache upstream bus. This is only "\
"used when l3cache-state_modelled=true.")
l3cache_size = Param.MemorySize('0x100000', "L3 Cache size in bytes.")
l3cache_snoop_data_transfer_latency = Param.UInt64(0, "L3 Cache timing "\
"annotation latency for received snoop accesses that perform a "\
"data transfer given in ticks per byte accessed. This is only "\
"used when dcache-state_modelled=true.")
l3cache_snoop_issue_latency = Param.UInt64(0, "L3 Cache timing "\
"annotation latency for snoop accesses issued by this cache in "\
"total ticks. This is only used when dcache-state_modelled=true.")
l3cache_write_access_latency = Param.UInt64(0, "L3 Cache timing "\
"annotation latency for write accesses given in ticks per access "\
"(of size l3cache-write_bus_width_in_bytes). If this parameter "\
"is non-zero, per-access latencies will be used instead of "\
"per-byte even if l3cache-write_latency is set. This is only "\
"used when l3cache-state_modelled=true.")
l3cache_write_latency = Param.UInt64(0, "L3 Cache timing annotation "\
"latency for write accesses given in ticks per byte accessed. "\
"l3cache-write_access_latency must be set to 0 for per-byte "\
"latencies to be applied. This is only used when "\
"l3cache-state_modelled=true.")
pchannel_treat_simreset_as_poreset = Param.Bool(
False, "Register core as ON state to cluster with simulation reset.")
periph_address_end = Param.Addr(0x0, "End address for peripheral port "\
"address range exclusive(corresponds to AENDMP input signal).")
periph_address_start = Param.Addr(0x0, "Start address for peripheral "\
"port address range inclusive(corresponds to ASTARTMP input "\
"signal).")
ptw_latency = Param.UInt64(0, "Page table walker latency for TA "\
"(Timing Annotation), expressed in simulation ticks")
tlb_latency = Param.UInt64(0, "TLB latency for TA (Timing Annotation), "\
"expressed in simulation ticks")
treat_dcache_cmos_to_pou_as_nop = Param.Bool(False, "Whether dcache "\
"invalidation to the point of unification is required for "\
"instruction to data coherence. true - Invalidate operations not "\
"required")
walk_cache_latency = Param.UInt64(0, "Walk cache latency for TA (Timing "\
"Annotation), expressed in simulation ticks")
cpu0_CFGEND = Param.Bool(False, "Endianness configuration at reset. "\
"0, little endian. 1, big endian.")
cpu0_CFGTE = Param.Bool(False, "Instruction set state when resetting "\
"into AArch32. 0, A32. 1, T32.")
cpu0_CRYPTODISABLE = Param.Bool(False, "Disable cryptographic features.")
cpu0_RVBARADDR = Param.Addr(0x0, "Value of RVBAR_ELx register.")
cpu0_VINITHI = Param.Bool(False, "Reset value of SCTLR.V.")
cpu0_enable_trace_special_hlt_imm16 = Param.Bool(
False, "Enable usage of parameter trace_special_hlt_imm16")
cpu0_l2cache_hit_latency = Param.UInt64(0, "L2 Cache timing annotation "\
"latency for hit. Intended to model the tag-lookup time. This "\
"is only used when l2cache-state_modelled=true.")
cpu0_l2cache_maintenance_latency = Param.UInt64(0, "L2 Cache timing "\
"annotation latency for cache maintenance operations given in "\
"total ticks. This is only used when dcache-state_modelled=true.")
cpu0_l2cache_miss_latency = Param.UInt64(0, "L2 Cache timing annotation "\
"latency for miss. Intended to model the time for failed "\
"tag-lookup and allocation of intermediate buffers. This is "\
"only used when l2cache-state_modelled=true.")
cpu0_l2cache_read_access_latency = Param.UInt64(0, "L2 Cache timing "\
"annotation latency for read accesses given in ticks per "\
"access. If this parameter is non-zero, per-access latencies "\
"will be used instead of per-byte even if l2cache-read_latency "\
"is set. This is in addition to the hit or miss latency, and "\
"intended to correspond to the time taken to transfer across the "\
"cache upstream bus, this is only used when "\
"l2cache-state_modelled=true.")
cpu0_l2cache_read_latency = Param.UInt64(0, "L2 Cache timing annotation "\
"latency for read accesses given in ticks per byte "\
"accessed.l2cache-read_access_latency must be set to 0 for "\
"per-byte latencies to be applied. This is in addition to the "\
"hit or miss latency, and intended to correspond to the time "\
"taken to transfer across the cache upstream bus. This is only "\
"used when l2cache-state_modelled=true.")
cpu0_l2cache_size = Param.MemorySize32('0x80000',
"L2 Cache size in bytes.")
cpu0_l2cache_snoop_data_transfer_latency = Param.UInt64(0, "L2 Cache "\
"timing annotation latency for received snoop accesses that "\
"perform a data transfer given in ticks per byte accessed. This "\
"is only used when dcache-state_modelled=true.")
cpu0_l2cache_snoop_issue_latency = Param.UInt64(0, "L2 Cache timing "\
"annotation latency for snoop accesses issued by this cache in "\
"total ticks. This is only used when dcache-state_modelled=true.")
cpu0_l2cache_write_access_latency = Param.UInt64(0, "L2 Cache timing "\
"annotation latency for write accesses given in ticks per "\
"access. If this parameter is non-zero, per-access latencies "\
"will be used instead of per-byte even if l2cache-write_latency "\
"is set. This is only used when l2cache-state_modelled=true.")
cpu0_l2cache_write_latency = Param.UInt64(0, "L2 Cache timing annotation "\
"latency for write accesses given in ticks per byte accessed. "\
"l2cache-write_access_latency must be set to 0 for per-byte "\
"latencies to be applied. This is only used when "\
"l2cache-state_modelled=true.")
cpu0_max_code_cache_mb = Param.MemorySize32('0x100', "Maximum size of "\
"the simulation code cache (MiB). For platforms with more than 2 "\
"cores this limit will be scaled down. (e.g 1/8 for 16 or more "\
"cores)")
cpu0_min_sync_level = Param.Unsigned(0, "Force minimum syncLevel "\
"(0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)")
cpu0_semihosting_A32_HLT = Param.UInt16(
0xf000, "A32 HLT number for semihosting calls.")
cpu0_semihosting_A64_HLT = Param.UInt16(
0xf000, "A64 HLT number for semihosting calls.")
cpu0_semihosting_ARM_SVC = Param.UInt32(
0x123456, "A32 SVC number for semihosting calls.")
cpu0_semihosting_T32_HLT = Param.Unsigned(
60, "T32 HLT number for semihosting calls.")
cpu0_semihosting_Thumb_SVC = Param.Unsigned(
171, "T32 SVC number for semihosting calls.")
cpu0_semihosting_cmd_line = Param.String(
"", "Command line available to semihosting calls.")
cpu0_semihosting_cwd = Param.String(
"", "Base directory for semihosting file access.")
cpu0_semihosting_enable = Param.Bool(True,
"Enable semihosting SVC/HLT traps.")
cpu0_semihosting_heap_base = Param.Addr(0x0,
"Virtual address of heap base.")
cpu0_semihosting_heap_limit = Param.Addr(
0xf000000, "Virtual address of top of heap.")
cpu0_semihosting_stack_base = Param.Addr(
0x10000000, "Virtual address of base of descending stack.")
cpu0_semihosting_stack_limit = Param.Addr(
0xf000000, "Virtual address of stack limit.")
cpu0_trace_special_hlt_imm16 = Param.UInt16(0xf000, "For this HLT "\
"number, IF enable_trace_special_hlt_imm16=true, skip performing "\
"usual HLT execution but call MTI trace if registered")
cpu0_vfp_enable_at_reset = Param.Bool(False, "Enable VFP in CPACR, "\
"CPPWR, NSACR at reset. Warning: Arm recommends going through "\
"the implementation's suggested VFP power-up sequence!")
class FastModelPL330(SystemC_ScModule):
type = 'FastModelPL330'
cxx_class = 'gem5::fastmodel::PL330'
cxx_header = 'arch/arm/fastmodel/PL330_DMAC/pl330.hh'
clock = Param.Frequency("Clock frequency")
irq_0 = IntSourcePin("Sets when DMASEV 0")
irq_1 = IntSourcePin("Sets when DMASEV 1")
irq_2 = IntSourcePin("Sets when DMASEV 2")
irq_3 = IntSourcePin("Sets when DMASEV 3")
irq_4 = IntSourcePin("Sets when DMASEV 4")
irq_5 = IntSourcePin("Sets when DMASEV 5")
irq_6 = IntSourcePin("Sets when DMASEV 6")
irq_7 = IntSourcePin("Sets when DMASEV 7")
irq_8 = IntSourcePin("Sets when DMASEV 8")
irq_9 = IntSourcePin("Sets when DMASEV 9")
irq_10 = IntSourcePin("Sets when DMASEV 10")
irq_11 = IntSourcePin("Sets when DMASEV 11")
irq_12 = IntSourcePin("Sets when DMASEV 12")
irq_13 = IntSourcePin("Sets when DMASEV 13")
irq_14 = IntSourcePin("Sets when DMASEV 14")
irq_15 = IntSourcePin("Sets when DMASEV 15")
irq_16 = IntSourcePin("Sets when DMASEV 16")
irq_17 = IntSourcePin("Sets when DMASEV 17")
irq_18 = IntSourcePin("Sets when DMASEV 18")
irq_19 = IntSourcePin("Sets when DMASEV 19")
irq_20 = IntSourcePin("Sets when DMASEV 20")
irq_21 = IntSourcePin("Sets when DMASEV 21")
irq_22 = IntSourcePin("Sets when DMASEV 22")
irq_23 = IntSourcePin("Sets when DMASEV 23")
irq_24 = IntSourcePin("Sets when DMASEV 24")
irq_25 = IntSourcePin("Sets when DMASEV 25")
irq_26 = IntSourcePin("Sets when DMASEV 26")
irq_27 = IntSourcePin("Sets when DMASEV 27")
irq_28 = IntSourcePin("Sets when DMASEV 28")
irq_29 = IntSourcePin("Sets when DMASEV 29")
irq_30 = IntSourcePin("Sets when DMASEV 30")
irq_31 = IntSourcePin("Sets when DMASEV 31")
irq_abort = IntSourcePin("Undefined instruction or instruction error")
fifo_size = Param.UInt32(16, "Channel FIFO size in bytes")
max_transfer = Param.UInt32(256, "Largest atomic transfer")
generate_clear = Param.Bool(False, "Generate clear response")
activate_delay = Param.UInt32(0, "request delay")
revision = Param.String("r0p0", "revision ID")
max_irqs = Param.UInt32(32, "number of interrupts")
buffer_depth = Param.UInt32(16, "buffer depth")
lsq_read_size = Param.UInt32(4, "LSQ read buffer depth")
lsq_write_size = Param.UInt32(4, "LSQ write buffer depth")
read_issuing_capability = Param.UInt32(1, "AXI read issuing capability")
write_issuing_capability = Param.UInt32(1, "AXI write issuing capability")
axi_bus_width = Param.UInt32(32, "AXI bus width")
cache_line_words = Param.UInt32(1, "number of words in a cache line")
cache_lines = Param.UInt32(1, "number of cache lines")
max_channels = Param.UInt32(8, "virtual channels")
controller_nsecure = Param.Bool(
False, "Controller non-secure at reset "
"(boot_manager_ns)")
irq_nsecure = Param.UInt32(0, "Interrupts non-secure at reset")
periph_nsecure = Param.Bool(False, "Peripherals non-secure at reset")
controller_boots = Param.Bool(True, "DMA boots from reset")
reset_pc = Param.UInt32(0x60000000, "DMA PC at reset")
max_periph = Param.UInt32(32, "number of peripheral interfaces")
perip_request_acceptance_0 = \
Param.UInt32(2, "Peripheral 0 request acceptance" )
perip_request_acceptance_1 = \
Param.UInt32(2, "Peripheral 1 request acceptance" )
perip_request_acceptance_2 = \
Param.UInt32(2, "Peripheral 2 request acceptance" )
perip_request_acceptance_3 = \
Param.UInt32(2, "Peripheral 3 request acceptance" )
perip_request_acceptance_4 = \
Param.UInt32(2, "Peripheral 4 request acceptance" )
perip_request_acceptance_5 = \
Param.UInt32(2, "Peripheral 5 request acceptance" )
perip_request_acceptance_6 = \
Param.UInt32(2, "Peripheral 6 request acceptance" )
perip_request_acceptance_7 = \
Param.UInt32(2, "Peripheral 7 request acceptance" )
perip_request_acceptance_8 = \
Param.UInt32(2, "Peripheral 8 request acceptance" )
perip_request_acceptance_9 = \
Param.UInt32(2, "Peripheral 9 request acceptance" )
perip_request_acceptance_10 = \
Param.UInt32(2, "Peripheral 10 request acceptance")
perip_request_acceptance_11 = \
Param.UInt32(2, "Peripheral 11 request acceptance")
perip_request_acceptance_12 = \
Param.UInt32(2, "Peripheral 12 request acceptance")
perip_request_acceptance_13 = \
Param.UInt32(2, "Peripheral 13 request acceptance")
perip_request_acceptance_14 = \
Param.UInt32(2, "Peripheral 14 request acceptance")
perip_request_acceptance_15 = \
Param.UInt32(2, "Peripheral 15 request acceptance")
perip_request_acceptance_16 = \
Param.UInt32(2, "Peripheral 16 request acceptance")
perip_request_acceptance_17 = \
Param.UInt32(2, "Peripheral 17 request acceptance")
perip_request_acceptance_18 = \
Param.UInt32(2, "Peripheral 18 request acceptance")
perip_request_acceptance_19 = \
Param.UInt32(2, "Peripheral 19 request acceptance")
perip_request_acceptance_20 = \
Param.UInt32(2, "Peripheral 20 request acceptance")
perip_request_acceptance_21 = \
Param.UInt32(2, "Peripheral 21 request acceptance")
perip_request_acceptance_22 = \
Param.UInt32(2, "Peripheral 22 request acceptance")
perip_request_acceptance_23 = \
Param.UInt32(2, "Peripheral 23 request acceptance")
perip_request_acceptance_24 = \
Param.UInt32(2, "Peripheral 24 request acceptance")
perip_request_acceptance_25 = \
Param.UInt32(2, "Peripheral 25 request acceptance")
perip_request_acceptance_26 = \
Param.UInt32(2, "Peripheral 26 request acceptance")
perip_request_acceptance_27 = \
Param.UInt32(2, "Peripheral 27 request acceptance")
perip_request_acceptance_28 = \
Param.UInt32(2, "Peripheral 28 request acceptance")
perip_request_acceptance_29 = \
Param.UInt32(2, "Peripheral 29 request acceptance")
perip_request_acceptance_30 = \
Param.UInt32(2, "Peripheral 30 request acceptance")
perip_request_acceptance_31 = \
Param.UInt32(2, "Peripheral 31 request acceptance")
# Singleton IRQ abort signal port
# 32 bit wide IRQ master DMASEV port
dma = AmbaInitiatorSocket(64, "Memory accesses")
pio_s = AmbaTargetSocket(64, "Register accesses (secure)")
pio_ns = AmbaTargetSocket(64, "Register accesses (non-secure)")