Beispiel #1
0
    def find_all(self, ptype):
        all = {}
        # search children
        for child in self._children.itervalues():
            # a child could be a list, so ensure we visit each item
            if isinstance(child, list):
                children = child
            else:
                children = [child]

            for child in children:
                if isinstance(child, ptype) and not isproxy(child) and \
                        not isNullPointer(child):
                    all[child] = True
                if isSimObject(child):
                    # also add results from the child itself
                    child_all, done = child.find_all(ptype)
                    all.update(dict(zip(child_all, [done] * len(child_all))))
        # search param space
        for pname, pdesc in self._params.iteritems():
            if issubclass(pdesc.ptype, ptype):
                match_obj = self._values[pname]
                if not isproxy(match_obj) and not isNullPointer(match_obj):
                    all[match_obj] = True
        return all.keys(), True
Beispiel #2
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    def find_all(self, ptype):
        all = {}
        # search children
        for child in self._children.itervalues():
            # a child could be a list, so ensure we visit each item
            if isinstance(child, list):
                children = child
            else:
                children = [child]

            for child in children:
                if isinstance(child, ptype) and not isproxy(child) and \
                        not isNullPointer(child):
                    all[child] = True
                if isSimObject(child):
                    # also add results from the child itself
                    child_all, done = child.find_all(ptype)
                    all.update(dict(zip(child_all, [done] * len(child_all))))
        # search param space
        for pname,pdesc in self._params.iteritems():
            if issubclass(pdesc.ptype, ptype):
                match_obj = self._values[pname]
                if not isproxy(match_obj) and not isNullPointer(match_obj):
                    all[match_obj] = True
        return all.keys(), True
Beispiel #3
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def simnode_children(simNode):
    for child in simNode._children.itervalues():
        if isNullPointer(child):
            continue
        if isSimObjectVector(child):
            for obj in child:
                if not isNullPointer(obj):
                    yield obj
        else:
            yield child
Beispiel #4
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def simnode_children(simNode):
    for child in simNode._children.itervalues():
        if isNullPointer(child):
            continue
        if isSimObjectVector(child):
            for obj in child:
                if not isNullPointer(obj):
                    yield obj
        else:
            yield child
Beispiel #5
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 def find_all(self, ptype):
     all = {}
     # search children
     for child in self._children.itervalues():
         if isinstance(child, ptype) and not isproxy(child) and \
            not isNullPointer(child):
             all[child] = True
     # search param space
     for pname,pdesc in self._params.iteritems():
         if issubclass(pdesc.ptype, ptype):
             match_obj = self._values[pname]
             if not isproxy(match_obj) and not isNullPointer(match_obj):
                 all[match_obj] = True
     return all.keys(), True
Beispiel #6
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    def addArchEvents(self,
                      cpu=None,
                      itb=None,
                      dtb=None,
                      icache=None,
                      dcache=None,
                      l2cache=None):
        """Add architected events to the PMU.

        This method can be called multiple times with only a subset of
        the keyword arguments set. This enables event registration in
        configuration scripts to happen closer to the instantiation of
        the instrumented objects (e.g., the memory system) instead of
        a central point.

        CPU events should also be registered once per CPU that is
        sharing the PMU (e.g., when switching between CPU models).
        """

        bpred = getattr(cpu, "branchPred", None) if cpu else None
        if bpred is not None and isNullPointer(bpred):
            bpred = None

        self.addEvent(SoftwareIncrement(self, 0x00))
        # 0x01: L1I_CACHE_REFILL
        self.addEvent(ProbeEvent(self, 0x02, itb, "Refills"))
        # 0x03: L1D_CACHE_REFILL
        # 0x04: L1D_CACHE
        self.addEvent(ProbeEvent(self, 0x05, dtb, "Refills"))
        self.addEvent(ProbeEvent(self, 0x06, cpu, "RetiredLoads"))
        self.addEvent(ProbeEvent(self, 0x07, cpu, "RetiredStores"))
        self.addEvent(ProbeEvent(self, 0x08, cpu, "RetiredInsts"))
        # 0x09: EXC_TAKEN
        # 0x0A: EXC_RETURN
        # 0x0B: CID_WRITE_RETIRED
        # 0x0C: PC_WRITE_RETIRED
        # 0x0D: BR_IMMED_RETIRED
        # 0x0E: BR_RETURN_RETIRED
        # 0x0F: UNALIGEND_LDST_RETIRED
        self.addEvent(ProbeEvent(self, 0x10, bpred, "Misses"))
        self.addEvent(
            ProbeEvent(self, ARCH_EVENT_CORE_CYCLES, cpu, "ActiveCycles"))
        self.addEvent(ProbeEvent(self, 0x12, bpred, "Branches"))
        self.addEvent(
            ProbeEvent(self, 0x13, cpu, "RetiredLoads", "RetiredStores"))
        # 0x14: L1I_CACHE
        # 0x15: L1D_CACHE_WB
        # 0x16: L2D_CACHE
        # 0x17: L2D_CACHE_REFILL
        # 0x18: L2D_CACHE_WB
        # 0x19: BUS_ACCESS
        # 0x1A: MEMORY_ERROR
        # 0x1B: INST_SPEC
        # 0x1C: TTBR_WRITE_RETIRED
        # 0x1D: BUS_CYCLES
        # 0x1E: CHAIN
        # 0x1F: L1D_CACHE_ALLOCATE
        # 0x20: L2D_CACHE_ALLOCATE
        self.addEvent(ProbeEvent(self, 0x21, cpu, "RetiredBranches"))
Beispiel #7
0
def isSimObjectSequence(value):
    if not isinstance(value, (list, tuple)) or len(value) == 0:
        return False

    for val in value:
        if not isNullPointer(val) and not isSimObject(val):
            return False

    return True
def isSimObjectSequence(value):
    if not isinstance(value, (list, tuple)) or len(value) == 0:
        return False

    for val in value:
        if not isNullPointer(val) and not isSimObject(val):
            return False

    return True
Beispiel #9
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    def addArchEvents(self,
                      cpu=None,
                      itb=None,
                      dtb=None,
                      icache=None,
                      dcache=None,
                      l2cache=None):
        """Add architected events to the PMU.

        This method can be called multiple times with only a subset of
        the keyword arguments set. This enables event registration in
        configuration scripts to happen closer to the instantiation of
        the instrumented objects (e.g., the memory system) instead of
        a central point.

        CPU events should also be registered once per CPU that is
        sharing the PMU (e.g., when switching between CPU models).
        """

        bpred = cpu.branchPred if cpu and not isNullPointer(cpu.branchPred) \
            else None

        self.addEvent(SoftwareIncrement(self, 0x00))
        # 0x01: L1I_CACHE_REFILL
        self.addEvent(ProbeEvent(self, 0x02, itb, "Refills"))
        # 0x03: L1D_CACHE_REFILL
        # 0x04: L1D_CACHE
        self.addEvent(ProbeEvent(self, 0x05, dtb, "Refills"))
        self.addEvent(ProbeEvent(self, 0x06, cpu, "RetiredLoads"))
        self.addEvent(ProbeEvent(self, 0x07, cpu, "RetiredStores"))
        self.addEvent(ProbeEvent(self, 0x08, cpu, "RetiredInsts"))
        # 0x09: EXC_TAKEN
        # 0x0A: EXC_RETURN
        # 0x0B: CID_WRITE_RETIRED
        self.addEvent(ProbeEvent(self, 0x0C, cpu, "RetiredBranches"))
        # 0x0D: BR_IMMED_RETIRED
        # 0x0E: BR_RETURN_RETIRED
        # 0x0F: UNALIGEND_LDST_RETIRED
        self.addEvent(ProbeEvent(self, 0x10, bpred, "Misses"))
        self.addEvent(
            ProbeEvent(self, ARCH_EVENT_CORE_CYCLES, cpu, "ActiveCycles"))
        self.addEvent(ProbeEvent(self, 0x12, bpred, "Branches"))
        self.addEvent(
            ProbeEvent(self, 0x13, cpu, "RetiredLoads", "RetiredStores"))
Beispiel #10
0
    def addArchEvents(self,
                      cpu=None,
                      itb=None, dtb=None,
                      icache=None, dcache=None,
                      l2cache=None):
        """Add architected events to the PMU.

        This method can be called multiple times with only a subset of
        the keyword arguments set. This enables event registration in
        configuration scripts to happen closer to the instantiation of
        the instrumented objects (e.g., the memory system) instead of
        a central point.

        CPU events should also be registered once per CPU that is
        sharing the PMU (e.g., when switching between CPU models).
        """

        bpred = getattr(cpu, "branchPred", None) if cpu else None
        if bpred is not None and isNullPointer(bpred):
            bpred = None

        self.addEvent(SoftwareIncrement(self,0x00))
        # 0x01: L1I_CACHE_REFILL
        self.addEvent(ProbeEvent(self,0x02, itb, "Refills"))
        # 0x03: L1D_CACHE_REFILL
        # 0x04: L1D_CACHE
        self.addEvent(ProbeEvent(self,0x05, dtb, "Refills"))
        self.addEvent(ProbeEvent(self,0x06, cpu, "RetiredLoads"))
        self.addEvent(ProbeEvent(self,0x07, cpu, "RetiredStores"))
        self.addEvent(ProbeEvent(self,0x08, cpu, "RetiredInsts"))
        # 0x09: EXC_TAKEN
        # 0x0A: EXC_RETURN
        # 0x0B: CID_WRITE_RETIRED
        self.addEvent(ProbeEvent(self,0x0C, cpu, "RetiredBranches"))
        # 0x0D: BR_IMMED_RETIRED
        # 0x0E: BR_RETURN_RETIRED
        # 0x0F: UNALIGEND_LDST_RETIRED
        self.addEvent(ProbeEvent(self,0x10, bpred, "Misses"))
        self.addEvent(ProbeEvent(self, ARCH_EVENT_CORE_CYCLES, cpu,
                                 "ActiveCycles"))
        self.addEvent(ProbeEvent(self,0x12, bpred, "Branches"))
        self.addEvent(ProbeEvent(self,0x13, cpu, "RetiredLoads",
                                 "RetiredStores"))
Beispiel #11
0
    def _bind_obj(name, obj):
        if isNullPointer(obj):
            return
        if m5.SimObject.isSimObjectVector(obj):
            for idx, obj in enumerate(obj):
                _bind_obj("{}{}".format(name, idx), obj)
        else:
            # We need this check because not all obj.getCCObject() is an
            # instance of Stat::Group. For example, sc_core::sc_module, the C++
            # class of SystemC_ScModule, is not a subclass of Stat::Group. So
            # it will cause a type error if obj is a SystemC_ScModule when
            # calling addStatGroup().
            if isinstance(obj.getCCObject(), _m5.stats.Group):
                parent = root
                while parent:
                    if hasattr(parent, 'addStatGroup'):
                        parent.addStatGroup(name, obj.getCCObject())
                        break
                    parent = parent.get_parent();

            _bindStatHierarchy(obj)