def gen_model(real_type):
# declare module
m = MixedSignalModel('model', real_type=real_type)
m.add_digital_input('clk')
m.add_digital_input('rst')
m.add_analog_output('g')
# bind expression to internal signal
m.add_digital_param('param_a')
m.add_digital_param('param_b')
m.add_digital_param('param_c', width=2, signed=True)
m.add_digital_param('param_d', width=2, signed=True)
m.add_real_param('param_e')
m.add_real_param('param_f')
# create state signals
m.add_digital_state('sig1', init=m.param_a)
m.add_digital_state('sig2', init=m.param_c, width=2, signed=True)
m.add_analog_state('sig3', init=m.param_e, range_=25)
# create main logic
m.set_next_cycle(m.sig1, m.param_b, clk=m.clk, rst=m.rst)
m.set_next_cycle(m.sig2, m.param_d, clk=m.clk, rst=m.rst)
m.set_next_cycle(m.sig3, m.param_f, clk=m.clk, rst=m.rst)
# sum signals to output
m.set_this_cycle(m.g, m.sig1 + m.sig2 + m.sig3)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(rp1, rn1, rp2, rn2, real_type, dt=0.1e-6):
# declare model
m = MixedSignalModel('model', dt=dt, real_type=real_type)
# declare I/O
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_digital_input('sw1')
m.add_digital_input('sw2')
# declare switch circuit
c = m.make_circuit()
gnd = c.make_ground()
c.voltage('net_v_in', gnd, m.v_in)
c.switch('net_v_in', 'net_v_x', m.sw1, r_on=rp1, r_off=rn1)
c.switch('net_v_x', gnd, m.sw2, r_on=rp2, r_off=rn2)
c.add_eqns(AnalogSignal('net_v_x') == m.v_out)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(cap=0.16e-6, ind=0.16e-6, res=0.1, dt=0.01e-6,
real_type=RealType.FixedPoint):
# declare model
m = MixedSignalModel('model', dt=dt, real_type=real_type)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_digital_input('clk')
m.add_digital_input('rst')
# declare system of equations
m.add_analog_state('i_ind', 10) # TODO: can this be tightened down a bit?
v_l = AnalogSignal('v_l')
v_r = AnalogSignal('v_r')
eqns = [
Deriv(m.i_ind) == v_l / ind,
Deriv(m.v_out) == m.i_ind / cap,
v_r == m.i_ind * res,
m.v_in == m.v_out + v_l + v_r
]
m.add_eqn_sys(eqns, clk=m.clk, rst=m.rst)
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
return model_file
def gen_model(tau, real_type):
# create mixed-signal model
m = MixedSignalModel('model', build_dir=BUILD_DIR, real_type=real_type)
# define I/O
x = m.add_analog_input('x')
dt = m.add_analog_input('dt')
y = m.add_analog_output('y')
clk = m.add_digital_input('clk')
rst = m.add_digital_input('rst')
# create function
func = m.make_function(lambda t: np.exp(-t / tau),
domain=[0, 1e-6],
order=1)
# apply function
f = m.set_from_sync_func('f', func, dt, clk=clk, rst=rst)
# update output
x_prev = m.cycle_delay(x, 1, clk=clk, rst=rst)
y_prev = m.cycle_delay(y, 1, clk=clk, rst=rst)
m.set_this_cycle(y, f * y_prev + (1 - f) * x_prev)
# write the model
return m.compile_to_file(VerilogGenerator())
def gen_model(r_off=2.6e3, current_range=100, real_type=RealType.FixedPoint):
# declare model
m = MixedSignalModel('model', dt=1e-9, real_type=real_type)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_digital_input('sw1')
m.add_digital_input('sw2')
m.add_digital_input('clk')
m.add_digital_input('rst')
# create test circuit
c = m.make_circuit(clk=m.clk, rst=m.rst)
gnd = c.make_ground()
c.voltage('net_v_in', gnd, m.v_in)
c.switch('net_v_in', 'net_v_x', m.sw1, r_off=r_off)
c.switch('net_v_x', gnd, m.sw2, r_off=r_off)
c.inductor('net_v_in', 'net_v_x', 1.0, current_range=current_range)
c.add_eqns(AnalogSignal('net_v_x') == m.v_out)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(tau=1e-6, dt=0.1e-6, real_type=RealType.FixedPoint):
m = MixedSignalModel('model', dt=dt, real_type=real_type)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_digital_input('clk')
m.add_digital_input('rst')
m.set_tf(input_=m.v_in,
output=m.v_out,
tf=((1, ), (tau, 1)),
clk=m.clk,
rst=m.rst)
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
return model_file
def gen_model():
# declare model I/O
m = MixedSignalModel('model')
m.add_digital_input('a', width=63, signed=True)
m.add_digital_input('b', width=63, signed=True)
m.add_digital_output('c', width=64, signed=True)
# assign expression to output
m.bind_name('d', m.a - m.b)
m.set_this_cycle(m.c, m.d)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(width, init, real_type):
# declare module
m = MixedSignalModel('model', real_type=real_type)
m.add_digital_input('clk')
m.add_digital_input('rst')
m.add_digital_output('out', width=width)
# bind expression to internal signal
lfsr = m.lfsr_signal(width, clk=m.clk, rst=m.rst, init=init)
m.set_this_cycle(m.out, lfsr)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(n, vn, vp, dt, real_type):
# declare model I/O
m = MixedSignalModel('model', dt=dt, real_type=real_type)
m.add_digital_input('d_in', width=n, signed=True)
m.add_analog_output('a_out')
# compute expression for DAC output
expr = ((m.d_in + (2**(n - 1))) / ((2**n) - 1)) * (vp - vn) + vn
# assign expression to output
m.set_this_cycle(m.a_out, expr)
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file
def gen_model(res=1e3, cap=1e-9, dt=0.1e-6, real_type=RealType.FixedPoint):
m = MixedSignalModel('model', dt=dt, real_type=real_type)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_digital_input('clk')
m.add_digital_input('rst')
c = m.make_circuit(clk=m.clk, rst=m.rst)
gnd = c.make_ground()
c.capacitor('net_v_out', gnd, cap, voltage_range=RangeOf(m.v_out))
c.resistor('net_v_in', 'net_v_out', res)
c.voltage('net_v_in', gnd, m.v_in)
c.add_eqns(AnalogSignal('net_v_out') == m.v_out)
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
return model_file
def gen_model(tau_f=1e-9,
tau_s=100e-9,
dt=10e-9,
real_type=RealType.FixedPoint):
m = MixedSignalModel('model', dt=dt, real_type=real_type)
m.add_analog_input('v_in')
m.add_analog_output('v_out')
m.add_digital_input('clk')
m.add_digital_input('rst')
m.bind_name('in_gt_out', m.v_in > m.v_out)
# detector dynamics
eqns = [
Deriv(m.v_out) == eqn_case([0, 1 / tau_f], [m.in_gt_out]) *
(m.v_in - m.v_out) - (m.v_out / tau_s)
]
m.add_eqn_sys(eqns, clk=m.clk, rst=m.rst)
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
return model_file
def gen_model():
# declare module
m = MixedSignalModel('model')
m.add_digital_input('clk')
m.add_digital_input('rst')
m.add_digital_input('seed', width=32)
m.add_digital_output('out', width=32)
# sum signals to output
m.set_this_cycle(m.out, mt19937(clk=m.clk, rst=m.rst, seed=m.seed))
# compile to a file
BUILD_DIR.mkdir(parents=True, exist_ok=True)
model_file = BUILD_DIR / 'model.sv'
m.compile_to_file(VerilogGenerator(), filename=model_file)
# return file location
return model_file