def test(request, silent=True): veriloggen.reset() simtype = request.config.getoption('--sim') rslt = matrix_conv2d_conv2d.run(act_shape, weight1_shape, bias1_shape, scale1_shape, weight2_shape, bias2_shape, scale2_shape, act_dtype, weight1_dtype, bias1_dtype, scale1_dtype, weight2_dtype, bias2_dtype, scale2_dtype, tmp_dtype, out_dtype, stride1, stride2, rshift_mul1, rshift_sum1, rshift_out1, rshift_mul2, rshift_sum2, rshift_out2, act_func1, act_func2, par_ich1, par_och1, par_col1, par_row1, concur_och1, stationary1, par_ich2, par_och2, par_col2, par_row2, concur_och2, stationary2, input_ram_size1, filter_ram_size1, bias_ram_size1, scale_ram_size1, out_ram_size1, input_ram_size2, filter_ram_size2, bias_ram_size2, scale_ram_size2, out_ram_size2, axi_datawidth, silent, filename=None, simtype=simtype, outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out') verify_rslt = rslt.splitlines()[-1] assert(verify_rslt == '# verify: PASSED')
rslt = matrix_conv2d_conv2d.run( act_shape, weight1_shape, bias1_shape, scale1_shape, weight2_shape, bias2_shape, scale2_shape, act_dtype, weight1_dtype, bias1_dtype, scale1_dtype, weight2_dtype, bias2_dtype, scale2_dtype, tmp_dtype, out_dtype, stride1, stride2, rshift_mul1, rshift_sum1, rshift_out1, rshift_mul2, rshift_sum2, rshift_out2, act_func1, act_func2, par_ich1, par_och1, par_col1, par_row1, concur_och1, stationary1, par_ich2, par_och2, par_col2, par_row2, concur_och2, stationary2, input_ram_size1, filter_ram_size1, bias_ram_size1, scale_ram_size1, out_ram_size1, input_ram_size2, filter_ram_size2, bias_ram_size2, scale_ram_size2, out_ram_size2, axi_datawidth, silent=False, filename='tmp.v', outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')