def getPageBasesExtended(cpu, lgr, kernel_base):
ENTRIES_PER_TABLE = 512
WORD_SIZE = 8
retval = []
reg_num = cpu.iface.int_register.get_number("cr3")
cr3 = cpu.iface.int_register.read(reg_num)
page_table_directory = cr3
pdir_index = 0
for pdir_table_index in range(4):
pdir_entry_addr = SIM_read_phys_memory(cpu, page_table_directory, 8)
for i in range(ENTRIES_PER_TABLE):
pdir_entry = SIM_read_phys_memory(cpu, pdir_entry_addr, WORD_SIZE)
pdir_entry_20 = memUtils.bitRange(pdir_entry, 12, 31)
ptable_base = pdir_entry_20 * PAGE_SIZE
if pdir_entry != 0:
ptable_entry_addr = ptable_base
ptable_index = 0
for j in range(ENTRIES_PER_TABLE):
ptable_entry = SIM_read_phys_memory(
cpu, ptable_entry_addr, WORD_SIZE)
present = memUtils.testBit(ptable_entry, 0)
if present:
entry_20 = memUtils.bitRange(ptable_entry, 12, 31)
page_base = entry_20 * PAGE_SIZE
logical = 0
logical = memUtils.setBitRange(logical, pdir_index, 22)
#lgr.debug('logical now 0x%x from index %d' % (logical, pdir_index))
logical = memUtils.setBitRange(logical, ptable_index,
12)
if logical >= kernel_base:
break
#lgr.debug('logical now 0x%x from ptable index %d' % (logical, ptable_index))
addr_info = PageAddrInfo(logical, page_base,
ptable_entry)
retval.append(addr_info)
ptable_entry_addr += WORD_SIZE
ptable_index += 1
pdir_entry_addr += WORD_SIZE
pdir_index += 1
page_table_directory += WORD_SIZE
return retval
def getPageBases(cpu, lgr, kernel_base):
if cpu.architecture == 'arm':
return getPageBasesArm(cpu, lgr, kernel_base)
ENTRIES_PER_TABLE = 1024
retval = []
reg_num = cpu.iface.int_register.get_number("cr3")
cr3 = cpu.iface.int_register.read(reg_num)
pdir_entry_addr = cr3
pdir_index = 0
for i in range(ENTRIES_PER_TABLE):
pdir_entry = SIM_read_phys_memory(cpu, pdir_entry_addr, 4)
pdir_entry_20 = memUtils.bitRange(pdir_entry, 12, 31)
ptable_base = pdir_entry_20 * PAGE_SIZE
if pdir_entry != 0:
ptable_entry_addr = ptable_base
ptable_index = 0
for j in range(ENTRIES_PER_TABLE):
ptable_entry = SIM_read_phys_memory(cpu, ptable_entry_addr, 4)
present = memUtils.testBit(ptable_entry, 0)
if present:
entry_20 = memUtils.bitRange(ptable_entry, 12, 31)
page_base = entry_20 * PAGE_SIZE
logical = 0
logical = memUtils.setBitRange(logical, pdir_index, 22)
#lgr.debug('logical now 0x%x from index %d' % (logical, pdir_index))
logical = memUtils.setBitRange(logical, ptable_index, 12)
if logical >= kernel_base:
break
#lgr.debug('logical now 0x%x from ptable index %d' % (logical, ptable_index))
addr_info = PageAddrInfo(logical, page_base, ptable_entry)
retval.append(addr_info)
ptable_entry_addr += 4
ptable_index += 1
pdir_entry_addr += 4
pdir_index += 1
return retval