gpregs = reg_info(gpregs_str, gpregs_expr)
bgpregs_str = ['R%d_BANK' % r for r in xrange(0x8)]
bgpregs_expr = [ExprId(x, 32) for x in bgpregs_str]
bgpregs = reg_info(bgpregs_str, bgpregs_expr)
fregs_str = ['FR%d' % r for r in xrange(0x10)]
fregs_expr = [ExprId(x, 32) for x in fregs_str]
fregs = reg_info(fregs_str, fregs_expr)
dregs_str = ['DR%d' % r for r in xrange(0x8)]
dregs_expr = [ExprId(x, 32) for x in dregs_str]
dregs = reg_info(dregs_str, dregs_expr)
gen_reg('PC', globals())
gen_reg('PR', globals())
gen_reg('R0', globals())
gen_reg('GBR', globals())
gen_reg('SR', globals())
gen_reg('VBR', globals())
gen_reg('SSR', globals())
gen_reg('SPC', globals())
gen_reg('SGR', globals())
gen_reg('DBR', globals())
gen_reg('MACH', globals())
gen_reg('MACL', globals())
gen_reg('FPUL', globals())
gen_reg('FR0', globals())
R0 = gpregs_expr[0]
#!/usr/bin/env python
#-*- coding:utf-8 -*-
from miasm2.expression.expression import ExprId
from miasm2.core.cpu import gen_reg, gen_regs
gen_reg('PC', globals())
gen_reg('PC_FETCH', globals())
gen_reg('R_LO', globals())
gen_reg('R_HI', globals())
exception_flags = ExprId('exception_flags', 32)
PC_init = ExprId("PC_init")
PC_FETCH_init = ExprId("PC_FETCH_init")
regs32_str = ["ZERO", 'AT', 'V0', 'V1'] +\
['A%d'%i for i in xrange(4)] +\
['T%d'%i for i in xrange(8)] +\
['S%d'%i for i in xrange(8)] +\
['T%d'%i for i in xrange(8, 10)] +\
['K0', 'K1'] +\
['GP', 'SP', 'FP', 'RA']
regs32_expr = [ExprId(x, 32) for x in regs32_str]
regs_flt_str = ['F%d'%i for i in xrange(0x20)]
regs_fcc_str = ['FCC%d'%i for i in xrange(8)]
simd16_str = ["H%d" % i for i in xrange(0x20)]
simd16_expr, simd16_init, simd16_info = gen_regs(simd16_str, globals(), 16)
simd32_str = ["S%d" % i for i in xrange(0x20)]
simd32_expr, simd32_init, simd32_info = gen_regs(simd32_str, globals(), 32)
simd64_str = ["D%d" % i for i in xrange(0x20)]
simd64_expr, simd64_init, simd64_info = gen_regs(simd64_str, globals(), 64)
simd128_str = ["Q%d" % i for i in xrange(0x20)]
simd128_expr, simd128_init, simd128_info = gen_regs(
simd128_str, globals(), 128)
PC, PC_init = gen_reg("PC", globals(), 64)
WZR, WZR_init = gen_reg("WZR", globals(), 32)
XZR, XZR_init = gen_reg("XZR", globals(), 64)
reg_zf = 'zf'
reg_nf = 'nf'
reg_of = 'of'
reg_cf = 'cf'
zf = ExprId(reg_zf, size=1)
nf = ExprId(reg_nf, size=1)
of = ExprId(reg_of, size=1)
cf = ExprId(reg_cf, size=1)
zf_init = ExprId("zf_init", size=1)
nf_init = ExprId("nf_init", size=1)
#!/usr/bin/env python
#-*- coding:utf-8 -*-
from miasm2.expression.expression import ExprId
from miasm2.core.cpu import gen_reg, gen_regs
gen_reg('PC', globals())
gen_reg('PC_FETCH', globals())
gen_reg('R_LO', globals())
gen_reg('R_HI', globals())
PC_init = ExprId("PC_init")
PC_FETCH_init = ExprId("PC_FETCH_init")
regs32_str = ["ZERO", 'AT', 'V0', 'V1'] +\
['A%d'%i for i in xrange(4)] +\
['T%d'%i for i in xrange(8)] +\
['S%d'%i for i in xrange(8)] +\
['T%d'%i for i in xrange(8, 10)] +\
['K0', 'K1'] +\
['GP', 'SP', 'FP', 'RA']
regs32_expr = [ExprId(x, 32) for x in regs32_str]
regs_flt_str = ['F%d' % i for i in xrange(0x20)]
regs_fcc_str = ['FCC%d' % i for i in xrange(8)]
R_LO = ExprId('R_LO', 32)
R_HI = ExprId('R_HI', 32)
gpregs_expr = [ExprId(x, 32) for x in gpregs_str]
gpregs = reg_info(gpregs_str, gpregs_expr)
bgpregs_str = ['R%d_BANK' % r for r in xrange(0x8)]
bgpregs_expr = [ExprId(x, 32) for x in bgpregs_str]
bgpregs = reg_info(bgpregs_str, bgpregs_expr)
fregs_str = ['FR%d' % r for r in xrange(0x10)]
fregs_expr = [ExprId(x, 32) for x in fregs_str]
fregs = reg_info(fregs_str, fregs_expr)
dregs_str = ['DR%d' % r for r in xrange(0x8)]
dregs_expr = [ExprId(x, 32) for x in dregs_str]
dregs = reg_info(dregs_str, dregs_expr)
gen_reg('PC', globals())
gen_reg('PR', globals())
gen_reg('R0', globals())
gen_reg('GBR', globals())
gen_reg('SR', globals())
gen_reg('VBR', globals())
gen_reg('SSR', globals())
gen_reg('SPC', globals())
gen_reg('SGR', globals())
gen_reg('DBR', globals())
gen_reg('MACH', globals())
gen_reg('MACL', globals())
gen_reg('FPUL', globals())
gen_reg('FR0', globals())
R0 = gpregs_expr[0]
simd16_str = ["H%d" % i for i in xrange(0x20)]
simd16_expr, simd16_init, simd16_info = gen_regs(simd16_str, globals(), 16)
simd32_str = ["S%d" % i for i in xrange(0x20)]
simd32_expr, simd32_init, simd32_info = gen_regs(simd32_str, globals(), 32)
simd64_str = ["D%d" % i for i in xrange(0x20)]
simd64_expr, simd64_init, simd64_info = gen_regs(simd64_str, globals(), 64)
simd128_str = ["Q%d" % i for i in xrange(0x20)]
simd128_expr, simd128_init, simd128_info = gen_regs(
simd128_str, globals(), 128)
PC, _ = gen_reg("PC", 64)
WZR, _ = gen_reg("WZR", 32)
XZR, _ = gen_reg("XZR", 64)
PC_init = ExprId("PC_init", 64)
WZR_init = ExprId("WZR_init", 32)
XZR_init = ExprId("XZR_init", 64)
reg_zf = 'zf'
reg_nf = 'nf'
reg_of = 'of'
reg_cf = 'cf'
zf = ExprId(reg_zf, size=1)
nf = ExprId(reg_nf, size=1)
of = ExprId(reg_of, size=1)
gpregs = reg_info(gpregs_str, gpregs_expr)
bgpregs_str = ['R%d_BANK' % r for r in xrange(0x8)]
bgpregs_expr = [ExprId(x, 32) for x in bgpregs_str]
bgpregs = reg_info(bgpregs_str, bgpregs_expr)
fregs_str = ['FR%d' % r for r in xrange(0x10)]
fregs_expr = [ExprId(x, 32) for x in fregs_str]
fregs = reg_info(fregs_str, fregs_expr)
dregs_str = ['DR%d' % r for r in xrange(0x8)]
dregs_expr = [ExprId(x, 32) for x in dregs_str]
dregs = reg_info(dregs_str, dregs_expr)
PC, reg_info_pc = gen_reg('PC')
PR, reg_info_pr = gen_reg('PR')
R0, reg_info_r0 = gen_reg('R0')
GBR, reg_info_gbr = gen_reg('GBR')
SR, reg_info_sr = gen_reg('SR')
VBR, reg_info_vbr = gen_reg('VBR')
SSR, reg_info_ssr = gen_reg('SSR')
SPC, reg_info_spc = gen_reg('SPC')
SGR, reg_info_sgr = gen_reg('SGR')
DBR, reg_info_dbr = gen_reg('DBR')
MACH, reg_info_mach = gen_reg('MACH')
MACL, reg_info_macl = gen_reg('MACL')
FPUL, reg_info_fpul = gen_reg('FPUL')
FR0, reg_info_fr0 = gen_reg('FR0')
R0 = gpregs_expr[0]
#-*- coding:utf-8 -*-
from miasm2.expression.expression import ExprId
from miasm2.core.cpu import gen_reg, gen_regs
PC, _ = gen_reg('PC')
PC_FETCH, _ = gen_reg('PC_FETCH')
R_LO, _ = gen_reg('R_LO')
R_HI, _ = gen_reg('R_HI')
exception_flags = ExprId('exception_flags', 32)
PC_init = ExprId("PC_init", 32)
PC_FETCH_init = ExprId("PC_FETCH_init", 32)
regs32_str = ["ZERO", 'AT', 'V0', 'V1'] +\
['A%d'%i for i in xrange(4)] +\
['T%d'%i for i in xrange(8)] +\
['S%d'%i for i in xrange(8)] +\
['T%d'%i for i in xrange(8, 10)] +\
['K0', 'K1'] +\
['GP', 'SP', 'FP', 'RA']
regs32_expr = [ExprId(x, 32) for x in regs32_str]
regs_flt_str = ['F%d' % i for i in xrange(0x20)]
regs_fcc_str = ['FCC%d' % i for i in xrange(8)]
R_LO = ExprId('R_LO', 32)
gpregs_expr = [ExprId(x, 32) for x in gpregs_str]
gpregs = reg_info(gpregs_str, gpregs_expr)
bgpregs_str = ['R%d_BANK' % r for r in xrange(0x8)]
bgpregs_expr = [ExprId(x, 32) for x in bgpregs_str]
bgpregs = reg_info(bgpregs_str, bgpregs_expr)
fregs_str = ['FR%d' % r for r in xrange(0x10)]
fregs_expr = [ExprId(x, 32) for x in fregs_str]
fregs = reg_info(fregs_str, fregs_expr)
dregs_str = ['DR%d' % r for r in xrange(0x8)]
dregs_expr = [ExprId(x, 32) for x in dregs_str]
dregs = reg_info(dregs_str, dregs_expr)
PC, reg_info_pc = gen_reg('PC')
PR, reg_info_pr = gen_reg('PR')
R0, reg_info_r0 = gen_reg('R0')
GBR, reg_info_gbr = gen_reg('GBR')
SR, reg_info_sr = gen_reg('SR')
VBR, reg_info_vbr = gen_reg('VBR')
SSR, reg_info_ssr = gen_reg('SSR')
SPC, reg_info_spc = gen_reg('SPC')
SGR, reg_info_sgr = gen_reg('SGR')
DBR, reg_info_dbr = gen_reg('DBR')
MACH, reg_info_mach = gen_reg('MACH')
MACL, reg_info_macl = gen_reg('MACL')
FPUL, reg_info_fpul = gen_reg('FPUL')
FR0, reg_info_fr0 = gen_reg('FR0')
R0 = gpregs_expr[0]
simd08_expr, simd08_init, simd08_info = gen_regs(simd08_str, globals(), 8)
simd16_str = ["H%d" % i for i in xrange(0x20)]
simd16_expr, simd16_init, simd16_info = gen_regs(simd16_str, globals(), 16)
simd32_str = ["S%d" % i for i in xrange(0x20)]
simd32_expr, simd32_init, simd32_info = gen_regs(simd32_str, globals(), 32)
simd64_str = ["D%d" % i for i in xrange(0x20)]
simd64_expr, simd64_init, simd64_info = gen_regs(simd64_str, globals(), 64)
simd128_str = ["Q%d" % i for i in xrange(0x20)]
simd128_expr, simd128_init, simd128_info = gen_regs(simd128_str, globals(),
128)
gen_reg("PC", globals(), 64)
gen_reg("WZR", globals(), 32)
gen_reg("XZR", globals(), 64)
PC_init = ExprId("PC_init", 64)
WZR_init = ExprId("WZR_init", 32)
XZR_init = ExprId("XZR_init", 64)
reg_zf = 'zf'
reg_nf = 'nf'
reg_of = 'of'
reg_cf = 'cf'
zf = ExprId(reg_zf, size=1)
nf = ExprId(reg_nf, size=1)
of = ExprId(reg_of, size=1)
