def __init__(self):
XilinxISEPlatform.__init__(
self, "xc6slx9-2csg324", _io,
lambda p: SimpleCRG(p, "clk_y3", "user_btn"))
self.add_platform_command("""
CONFIG VCCAUX = "3.3";
""")
def __init__(self, manual_timing=False, extra_io=[]):
io = _io + extra_io
self.manual_timing = manual_timing
XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", io,
lambda p: SimpleCRG(p, "clk_if", None))
self.add_platform_command("""
CONFIG VCCAUX = "2.5";
""")
def __init__(self, manual_timing=False, extra_io=[]):
io = _io + extra_io
self.manual_timing = manual_timing
XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", io,
lambda p: SimpleCRG(p, "clk_if", None))
self.add_platform_command("""
CONFIG VCCAUX = "2.5";
""")
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx9-2csg324", _io,
lambda p: CRG_SE(p, "clk_y3", "user_btn"))
self.add_platform_command("""
CONFIG VCCAUX = "3.3";
""")
def __init__(self, crg_factory=lambda p: CRG_DS(p, "user_clk", "cpu_reset", 6.4)): XilinxISEPlatform.__init__(self, "xc7k325t-ffg900-1", _io, crg_factory)
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io,
lambda p: CRG_DS(p, "clk200", "cpu_reset", 5.0))
def __init__(self): XilinxISEPlatform.__init__(self, "xc7z020-clg484-1", _io, lambda p: CRG_SE(p, "clk100", None))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc5vsx95t-ff1136-1", _io)
def __init__(self):
XilinxISEPlatform.__init__(
self, "xc3s1400a-ft256-4", _io,
lambda p: CRG_DS(p, "clk64", "reset_n", rst_invert=True))
def __init__(self): XilinxISEPlatform.__init__(self, "xc3s1400a-ft256-4", _io, lambda p: CRG_DS(p, "clk64", "reset_n", rst_invert=True))
def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", self._io, lambda p: CRG_SE(p, "clk", "rst", 10.))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc3s500e-4pq208", _io,
lambda p: SimpleCRG(p, "clk50", None))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", self._io,
lambda p: SimpleCRG(p, "clk", "rst"))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", self._io, lambda p: SimpleCRG(p, "clk", "rst"))
def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, lambda p: CRG_SE(p, "clk50", "user_btn", 20.0))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc3s200a-ft256-4", _ios,
lambda p: SimpleCRG(p, "clk0", None),
_connectors)
def __init__(self):
io, chip = self._io["spartan3a"], "xc3s1400a-ft256-4"
#io, chip = self._io["spartan6"], "xc6slx45-fgg484-2"
XilinxISEPlatform.__init__(
self, chip, io, lambda p: CRG_SE(p, "clk", "rst", 1000 / 32.))
def __init__(self): XilinxISEPlatform.__init__(self, "xc5vsx95t-ff1136-1", _io)
def __init__(self):
XilinxISEPlatform.__init__(
self, "xc6slx45-fgg484-2", _io,
lambda p: CRG_SE(p, "clk50", "user_btn", 20.0))
def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io, lambda p: CRG_SE(p, "clk32", None, 31.25))
def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io, lambda p: SimpleCRG(p, "clk32", None), _connectors)
def __init__(self): XilinxISEPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io, lambda p: CRG_DS(p, "clk200", "user_btn"))
def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, lambda p: SimpleCRG(p, "clk50", None))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-3", _io,
lambda p: SimpleCRG(p, "clk50", None))
def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx150t-fgg676-3", _io, lambda p: CRG_DS(p, "clk100", "gpio"))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx150t-fgg676-3", _io,
lambda p: CRG_DS(p, "clk100", "gpio", 10.0))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", _io,
lambda p: SimpleCRG(p, "clk_if", "rst"))
self.add_platform_command("""
CONFIG VCCAUX = "2.5";
""")
def __init__(self):
XilinxISEPlatform.__init__(self, "xc3s200a-ft256-4", _ios, lambda p: SimpleCRG(p, "clk0", None), _connectors)
def __init__(self):
XilinxISEPlatform.__init__(
self, "xc6vlx240t-ff1156-1", _io,
lambda p: CRG_DS(p, "clk200", "user_btn", 5.0))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", self._io,
lambda p: CRG_SE(p, "clk", "rst", 10.))
def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io, lambda p: SimpleCRG(p, "clk50", None))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx150-3csg484", _io,
lambda p: CRG_SE(p, "clk_if", "rst"))
self.add_platform_command("""
CONFIG VCCAUX = "2.5";
""")
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io,
lambda p: CRG_SE(p, "clk32", None),
_connectors)
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-3", _io,
lambda p: SimpleCRG(p, "clk50", None))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx45-fgg484-2", _io,
lambda p: CRG_SE(p, "clk50", None))
self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n")
def __init__(self): XilinxISEPlatform.__init__(self, "xc6slx9-2csg225", _ios, lambda p: SimpleCRG(p, "clk3", None), _connectors)
def __init__(self):
XilinxISEPlatform.__init__(self, "xc7z020-clg484-1", _io,
lambda p: CRG_SE(p, "clk100", None))
def __init__(self):
XilinxISEPlatform.__init__(self, "xc3s200a-ft256-4", _io,
lambda p: CRG_SE(p, "CLK0", None))