def __init__(self, platform, **kwargs):
VideomixerSoC.__init__(self, platform, **kwargs)
lasmim = self.sdram.crossbar.get_master()
self.submodules.encoder_reader = EncoderDMAReader(lasmim)
self.submodules.encoder_cdc = RenameClockDomains(AsyncFIFO([("data", 128)], 4),
{"write": "sys", "read": "encoder"})
self.submodules.encoder_buffer = RenameClockDomains(EncoderBuffer(), "encoder")
self.submodules.encoder_fifo = RenameClockDomains(SyncFIFO(EndpointDescription([("data", 16)], packetized=True), 16), "encoder")
self.submodules.encoder = Encoder(platform)
self.submodules.usb_streamer = USBStreamer(platform, platform.request("fx2"))
self.comb += [
Record.connect(self.encoder_reader.source, self.encoder_cdc.sink),
Record.connect(self.encoder_cdc.source, self.encoder_buffer.sink),
Record.connect(self.encoder_buffer.source, self.encoder_fifo.sink),
Record.connect(self.encoder_fifo.source, self.encoder.sink),
Record.connect(self.encoder.source, self.usb_streamer.sink)
]
self.add_wb_slave(mem_decoder(self.mem_map["encoder"]), self.encoder.bus)
self.add_memory_region("encoder", self.mem_map["encoder"]+self.shadow_base, 0x2000)
platform.add_platform_command("""
NET "{usb_clk}" TNM_NET = "GRPusb_clk";
TIMESPEC "TSise_sucks11" = FROM "GRPusb_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSise_sucks12" = FROM "GRPsys_clk" TO "GRPusb_clk" TIG;
""", usb_clk=platform.lookup_request("fx2").ifclk)
def __init__(self, platform, **kwargs):
VideomixerSoC.__init__(self, platform, **kwargs)
lasmim = self.sdram.crossbar.get_master()
self.submodules.encoder_reader = EncoderDMAReader(lasmim)
self.submodules.encoder_cdc = RenameClockDomains(
AsyncFIFO([("data", 128)], 4), {
"write": "sys",
"read": "encoder"
})
self.submodules.encoder_buffer = RenameClockDomains(
EncoderBuffer(), "encoder")
self.submodules.encoder_fifo = RenameClockDomains(
SyncFIFO(EndpointDescription([("data", 16)], packetized=True), 16),
"encoder")
self.submodules.encoder = Encoder(platform)
encoder_port = self.ethcore.udp.crossbar.get_port(8000, 8)
self.submodules.encoder_streamer = UDPStreamer(
convert_ip("192.168.1.15"), 8000)
self.comb += [
platform.request("user_led", 0).eq(self.encoder_reader.source.stb),
platform.request("user_led", 1).eq(self.encoder_reader.source.ack),
Record.connect(self.encoder_reader.source, self.encoder_cdc.sink),
Record.connect(self.encoder_cdc.source, self.encoder_buffer.sink),
Record.connect(self.encoder_buffer.source, self.encoder_fifo.sink),
Record.connect(self.encoder_fifo.source, self.encoder.sink),
Record.connect(self.encoder.source, self.encoder_streamer.sink),
Record.connect(self.encoder_streamer.source, encoder_port.sink)
]
self.add_wb_slave(mem_decoder(self.mem_map["encoder"]),
self.encoder.bus)
self.add_memory_region("encoder",
self.mem_map["encoder"] + self.shadow_base,
0x2000)
def __init__(self, platform, **kwargs):
BaseSoC.__init__(self, platform, with_uart=False, **kwargs)
self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"), self.clk_freq)
self.submodules.usb_core = LiteUSBCore(self.usb_phy, self.clk_freq, with_crc=False)
# UART
usb_uart_port = self.usb_core.crossbar.get_port(self.usb_map["uart"])
self.submodules.uart = LiteUSBUART(usb_uart_port)
# DMA
usb_dma_port = self.usb_core.crossbar.get_port(self.usb_map["dma"])
usb_dma_loopback_fifo = SyncFIFO(user_description(8), 1024, buffered=True)
self.submodules += usb_dma_loopback_fifo
self.comb += [
usb_dma_port.source.connect(usb_dma_loopback_fifo.sink),
usb_dma_loopback_fifo.source.connect(usb_dma_port.sink)
]
# Wishbone Bridge
usb_bridge_port = self.usb_core.crossbar.get_port(self.usb_map["bridge"])
usb_bridge = LiteUSBWishboneBridge(usb_bridge_port, self.clk_freq)
self.submodules += usb_bridge
self.add_wb_master(usb_bridge.wishbone)
# Leds
leds = Cat(iter([platform.request("user_led", i) for i in range(8)]))
self.submodules.leds = GPIOOut(leds)
def __init__(self, fifo=0, **kwargs):
self.submodules.parser = Parser(**kwargs)
self.submodules.out = Sequencer()
if fifo:
self.submodules.fifo = SyncFIFO(line_layout, fifo)
self.comb += [
self.fifo.sink.connect(self.parser.source),
self.out.sink.connect(self.fifo.source)
]
else:
self.comb += self.out.sink.connect(self.parser.source)
def __init__(self, crc_class, layout):
self.sink = sink = Sink(layout)
self.source = source = Source(layout)
self.busy = Signal()
# # #
dw = flen(sink.data)
crc = crc_class(dw)
self.submodules += crc
ratio = crc.width // dw
error = Signal()
fifo = InsertReset(SyncFIFO(layout, ratio + 1))
self.submodules += fifo
fsm = FSM(reset_state="RESET")
self.submodules += fsm
fifo_in = Signal()
fifo_out = Signal()
fifo_full = Signal()
self.comb += [
fifo_full.eq(fifo.fifo.level == ratio),
fifo_in.eq(sink.stb & (~fifo_full | fifo_out)),
fifo_out.eq(source.stb & source.ack),
Record.connect(sink, fifo.sink),
fifo.sink.stb.eq(fifo_in),
self.sink.ack.eq(fifo_in),
source.stb.eq(sink.stb & fifo_full),
source.sop.eq(fifo.source.sop),
source.eop.eq(sink.eop),
fifo.source.ack.eq(fifo_out),
source.payload.eq(fifo.source.payload),
source.error.eq(sink.error | crc.error),
]
fsm.act(
"RESET",
crc.reset.eq(1),
fifo.reset.eq(1),
NextState("IDLE"),
)
fsm.act(
"IDLE", crc.data.eq(sink.data),
If(sink.stb & sink.sop & sink.ack, crc.ce.eq(1),
NextState("COPY")))
fsm.act(
"COPY", crc.data.eq(sink.data),
If(sink.stb & sink.ack, crc.ce.eq(1),
If(sink.eop, NextState("RESET"))))
self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
def __init__(self, phy, tx_fifo_depth=16, rx_fifo_depth=16):
self._rxtx = CSR(8)
self._txfull = CSRStatus()
self._rxempty = CSRStatus()
self.submodules.ev = EventManager()
self.ev.tx = EventSourceProcess()
self.ev.rx = EventSourceProcess()
self.ev.finalize()
# # #
tx_fifo = SyncFIFO([("data", 8)], tx_fifo_depth)
self.submodules += tx_fifo
self.comb += [
tx_fifo.sink.stb.eq(self._rxtx.re),
tx_fifo.sink.data.eq(self._rxtx.r),
self._txfull.status.eq(~tx_fifo.sink.ack),
Record.connect(tx_fifo.source, phy.sink)
]
rx_fifo = SyncFIFO([("data", 8)], rx_fifo_depth)
self.submodules += rx_fifo
self.comb += [
Record.connect(phy.source, rx_fifo.sink),
self._rxempty.status.eq(~rx_fifo.source.stb),
self._rxtx.w.eq(rx_fifo.source.data),
rx_fifo.source.ack.eq(self.ev.rx.clear)
]
self.comb += [
# Generate TX IRQ when tx_fifo becomes empty
self.ev.tx.trigger.eq(tx_fifo.source.stb),
# Generate RX IRQ when rx_fifo becomes non-empty
self.ev.rx.trigger.eq(~rx_fifo.source.stb),
]
def __init__(self, usb_actor):
g = DataFlowGraph()
fifo = SyncFIFO([('d', 16)], 64)
in_buffer = Relax([('d', 16)])
out_buffer = Relax([('d', 16)])
g.add_connection(in_buffer, fifo)
g.add_connection(fifo, out_buffer)
g.add_connection(out_buffer, usb_actor)
g.add_connection(usb_actor, in_buffer)
self.submodules.composite = CompositeActor(g)
self.busy = self.composite.busy
def __init__(self, platform, **kwargs):
BaseSoC.__init__(self, platform, with_uart=False, **kwargs)
self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"),
self.clk_freq)
self.submodules.usb_core = LiteUSBCore(self.usb_phy,
self.clk_freq,
with_crc=False)
# UART
usb_uart_port = self.usb_core.crossbar.get_port(self.usb_map["uart"])
self.submodules.uart = LiteUSBUART(usb_uart_port)
# DMA
usb_dma_port = self.usb_core.crossbar.get_port(self.usb_map["dma"])
usb_dma_loopback_fifo = SyncFIFO(user_description(8),
1024,
buffered=True)
self.submodules += usb_dma_loopback_fifo
self.comb += [
usb_dma_port.source.connect(usb_dma_loopback_fifo.sink),
usb_dma_loopback_fifo.source.connect(usb_dma_port.sink)
]
def __init__(self, ip_address, udp_port, fifo_depth=1024):
self.sink = sink = Sink([("data", 8)])
self.source = source = Source(eth_udp_user_description(8))
# # #
self.submodules.async_fifo = async_fifo = RenameClockDomains(AsyncFIFO([("data", 8)], 4),
{"write": "encoder", "read": "sys"})
self.submodules.fifo = fifo = SyncFIFO([("data", 8)], fifo_depth)
self.comb += [
Record.connect(sink, async_fifo.sink),
Record.connect(async_fifo.source, fifo.sink)
]
level = Signal(max=fifo_depth + 1)
level_update = Signal()
self.sync += If(level_update, level.eq(fifo.fifo.level))
counter = Signal(max=fifo_depth)
counter_reset = Signal()
counter_ce = Signal()
self.sync += \
If(counter_reset,
counter.eq(0)
).Elif(counter_ce,
counter.eq(counter + 1)
)
self.submodules.flush_timer = WaitTimer(10000)
flush = Signal()
self.comb += [
flush.eq((fifo.fifo.level > 0) & self.flush_timer.done)
]
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
self.flush_timer.wait.eq(1),
If((fifo.fifo.level >= 256) | flush,
level_update.eq(1),
counter_reset.eq(1),
NextState("SEND")
)
)
fsm.act("SEND",
source.stb.eq(fifo.source.stb),
source.sop.eq(counter == 0),
If(level == 0,
source.eop.eq(1),
).Else(
source.eop.eq(counter == (level - 1)),
),
source.src_port.eq(udp_port),
source.dst_port.eq(udp_port),
source.ip_address.eq(ip_address),
If(level == 0,
source.length.eq(1),
).Else(
source.length.eq(level),
),
source.data.eq(fifo.source.data),
fifo.source.ack.eq(source.ack),
If(source.stb & source.ack,
counter_ce.eq(1),
If(source.eop,
NextState("IDLE")
)
)
)
def __init__(self,
pads,
clk_freq,
fifo_depth=32,
read_time=128,
write_time=128):
dw = flen(pads.data)
# read fifo (FTDI --> SoC)
read_fifo = RenameClockDomains(
AsyncFIFO(phy_description(8), fifo_depth), {
"write": "usb",
"read": "sys"
})
read_buffer = RenameClockDomains(SyncFIFO(phy_description(8), 4),
{"sys": "usb"})
self.comb += read_buffer.source.connect(read_fifo.sink)
# write fifo (SoC --> FTDI)
write_fifo = RenameClockDomains(
AsyncFIFO(phy_description(8), fifo_depth), {
"write": "sys",
"read": "usb"
})
self.submodules += read_fifo, read_buffer, write_fifo
# sink / source interfaces
self.sink = write_fifo.sink
self.source = read_fifo.source
# read / write arbitration
wants_write = Signal()
wants_read = Signal()
txe_n = Signal()
rxf_n = Signal()
self.comb += [
txe_n.eq(pads.txe_n),
rxf_n.eq(pads.rxf_n),
wants_write.eq(~txe_n & write_fifo.source.stb),
wants_read.eq(~rxf_n & read_fifo.sink.ack),
]
read_time_en, max_read_time = anti_starvation(self, read_time)
write_time_en, max_write_time = anti_starvation(self, write_time)
data_w_accepted = Signal(reset=1)
fsm = FSM(reset_state="READ")
self.submodules += RenameClockDomains(fsm, {"sys": "usb"})
fsm.act(
"READ", read_time_en.eq(1),
If(wants_write, If(~wants_read | max_read_time, NextState("RTW"))))
fsm.act("RTW", NextState("WRITE"))
fsm.act(
"WRITE", write_time_en.eq(1),
If(wants_read, If(~wants_write | max_write_time,
NextState("WTR"))),
write_fifo.source.ack.eq(wants_write & data_w_accepted))
fsm.act("WTR", NextState("READ"))
# databus tristate
data_w = Signal(dw)
data_r = Signal(dw)
data_oe = Signal()
self.specials += Tristate(pads.data, data_w, data_oe, data_r)
# read / write actions
pads.oe_n.reset = 1
pads.rd_n.reset = 1
pads.wr_n.reset = 1
self.sync.usb += [
If(fsm.ongoing("READ"), data_oe.eq(0), pads.oe_n.eq(0),
pads.rd_n.eq(~wants_read),
pads.wr_n.eq(1)).Elif(fsm.ongoing("WRITE"), data_oe.eq(1),
pads.oe_n.eq(1), pads.rd_n.eq(1),
pads.wr_n.eq(~wants_write),
data_w_accepted.eq(~txe_n)).Else(
data_oe.eq(1),
pads.oe_n.eq(~fsm.ongoing("WTR")),
pads.rd_n.eq(1), pads.wr_n.eq(1)),
read_buffer.sink.stb.eq(~pads.rd_n & ~rxf_n),
read_buffer.sink.data.eq(data_r),
If(~txe_n & data_w_accepted, data_w.eq(write_fifo.source.data))
]
def __init__(self,
pads,
clk_freq,
fifo_depth=32,
read_time=128,
write_time=128):
dw = flen(pads.data)
self.clk_freq = clk_freq
# timings
tRD = self.ns(30) # RD# active pulse width (t4)
tRDDataSetup = self.ns(14) # RD# to DATA (t3)
tWRDataSetup = self.ns(5) # DATA to WR# active setup time (t8)
tWR = self.ns(30) # WR# active pulse width (t10)
tMultiReg = 2
# read fifo (FTDI --> SoC)
read_fifo = SyncFIFO(phy_description(8), fifo_depth)
# write fifo (SoC --> FTDI)
write_fifo = SyncFIFO(phy_description(8), fifo_depth)
self.submodules += read_fifo, write_fifo
# sink / source interfaces
self.sink = write_fifo.sink
self.source = read_fifo.source
# read / write arbitration
wants_write = Signal()
wants_read = Signal()
txe_n = Signal()
rxf_n = Signal()
self.specials += [
MultiReg(pads.txe_n, txe_n),
MultiReg(pads.rxf_n, rxf_n)
]
self.comb += [
wants_write.eq(~txe_n & write_fifo.source.stb),
wants_read.eq(~rxf_n & read_fifo.sink.ack),
]
read_time_en, max_read_time = anti_starvation(self, read_time)
write_time_en, max_write_time = anti_starvation(self, write_time)
fsm = FSM(reset_state="READ")
self.submodules += fsm
read_done = Signal()
write_done = Signal()
commuting = Signal()
fsm.act(
"READ", read_time_en.eq(1),
If(
wants_write & read_done,
If(~wants_read | max_read_time, commuting.eq(1),
NextState("RTW"))))
fsm.act("RTW", NextState("WRITE"))
fsm.act(
"WRITE", write_time_en.eq(1),
If(
wants_read & write_done,
If(~wants_write | max_write_time, commuting.eq(1),
NextState("WTR"))))
fsm.act("WTR", NextState("READ"))
# databus tristate
data_w = Signal(dw)
data_r_async = Signal(dw)
data_r = Signal(dw)
data_oe = Signal()
self.specials += [
Tristate(pads.data, data_w, data_oe, data_r_async),
MultiReg(data_r_async, data_r)
]
# read actions
pads.rd_n.reset = 1
read_fsm = FSM(reset_state="IDLE")
read_counter = Counter(8)
self.submodules += read_fsm, read_counter
read_fsm.act(
"IDLE", read_done.eq(1), read_counter.reset.eq(1),
If(
fsm.ongoing("READ") & wants_read,
If(~commuting, NextState("PULSE_RD_N"))))
read_fsm.act(
"PULSE_RD_N", pads.rd_n.eq(0), read_counter.ce.eq(1),
If(
read_counter.value == max((tRD - 1),
(tRDDataSetup + tMultiReg - 1)),
NextState("ACQUIRE_DATA")))
read_fsm.act("ACQUIRE_DATA", read_fifo.sink.stb.eq(1),
read_fifo.sink.data.eq(data_r), NextState("WAIT_RXF_N"))
read_fsm.act("WAIT_RXF_N", If(rxf_n, NextState("IDLE")))
# write actions
pads.wr_n.reset = 1
write_fsm = FSM(reset_state="IDLE")
write_counter = Counter(8)
self.submodules += write_fsm, write_counter
write_fsm.act(
"IDLE", write_done.eq(1), write_counter.reset.eq(1),
If(
fsm.ongoing("WRITE") & wants_write,
If(~commuting, NextState("SET_DATA"))))
write_fsm.act(
"SET_DATA", data_oe.eq(1), data_w.eq(write_fifo.source.data),
write_counter.ce.eq(1),
If(write_counter.value == (tWRDataSetup - 1),
write_counter.reset.eq(1), NextState("PULSE_WR_N")))
write_fsm.act(
"PULSE_WR_N", data_oe.eq(1), data_w.eq(write_fifo.source.data),
pads.wr_n.eq(0), write_counter.ce.eq(1),
If(write_counter.value == (tWR - 1), NextState("WAIT_TXE_N")))
write_fsm.act(
"WAIT_TXE_N",
If(txe_n, write_fifo.source.ack.eq(1), NextState("IDLE")))
def __init__(self, platform):
self.sink = Sink(EndpointDescription([("data", 16)], packetized=True))
self.source = Source([("data", 8)])
self.bus = wishbone.Interface()
# # #
# chroma upsampler
chroma_upsampler = RenameClockDomains(YCbCr422to444(), "encoder")
self.submodules += chroma_upsampler
self.comb += [
Record.connect(self.sink,
chroma_upsampler.sink,
leave_out=["data"]),
chroma_upsampler.sink.y.eq(self.sink.data[:8]),
chroma_upsampler.sink.cb_cr.eq(self.sink.data[8:])
]
# output fifo
output_fifo_almost_full = Signal()
output_fifo = RenameClockDomains(SyncFIFO([("data", 8)], 1024),
"encoder")
self.submodules += output_fifo
self.comb += [
output_fifo_almost_full.eq(output_fifo.fifo.level > 1024 - 128),
Record.connect(output_fifo.source, self.source)
]
# Wishbone cross domain crossing
jpeg_bus = wishbone.Interface()
self.specials += Instance(
"wb_async_reg",
i_wbm_clk=ClockSignal(),
i_wbm_rst=ResetSignal(),
i_wbm_adr_i=self.bus.adr,
i_wbm_dat_i=self.bus.dat_w,
o_wbm_dat_o=self.bus.dat_r,
i_wbm_we_i=self.bus.we,
i_wbm_sel_i=self.bus.sel,
i_wbm_stb_i=self.bus.stb,
o_wbm_ack_o=self.bus.ack,
o_wbm_err_o=self.bus.err,
#o_wbm_rty_o=,
i_wbm_cyc_i=self.bus.cyc,
i_wbs_clk=ClockSignal("encoder"),
i_wbs_rst=ResetSignal("encoder"),
o_wbs_adr_o=jpeg_bus.adr,
i_wbs_dat_i=jpeg_bus.dat_r,
o_wbs_dat_o=jpeg_bus.dat_w,
o_wbs_we_o=jpeg_bus.we,
o_wbs_sel_o=jpeg_bus.sel,
o_wbs_stb_o=jpeg_bus.stb,
i_wbs_ack_i=jpeg_bus.ack,
i_wbs_err_i=jpeg_bus.err,
i_wbs_rty_i=0,
o_wbs_cyc_o=jpeg_bus.cyc)
# encoder
self.specials += Instance(
"JpegEnc",
i_CLK=ClockSignal("encoder"),
i_RST=ResetSignal("encoder"),
i_OPB_ABus=Cat(Signal(2), jpeg_bus.adr) & 0x3ff,
i_OPB_BE=jpeg_bus.sel,
i_OPB_DBus_in=jpeg_bus.dat_w,
i_OPB_RNW=~jpeg_bus.we,
i_OPB_select=jpeg_bus.stb & jpeg_bus.cyc,
o_OPB_DBus_out=jpeg_bus.dat_r,
o_OPB_XferAck=jpeg_bus.ack,
#o_OPB_retry=,
#o_OPB_toutSup=,
o_OPB_errAck=jpeg_bus.err,
i_fdct_ack=chroma_upsampler.source.ack,
i_fdct_stb=chroma_upsampler.source.stb,
i_fdct_data=Cat(chroma_upsampler.source.y,
chroma_upsampler.source.cb,
chroma_upsampler.source.cr),
o_ram_byte=output_fifo.sink.data,
o_ram_wren=output_fifo.sink.stb,
#o_ram_wraddr=,
#o_frame_size=,
i_outif_almost_full=output_fifo_almost_full)
# add vhdl sources
platform.add_source_dir(
os.path.join(platform.soc_ext_path, "gateware", "encoder", "vhdl"))
# add verilog sources
platform.add_source(
os.path.join(platform.soc_ext_path, "gateware", "encoder",
"verilog", "wb_async_reg.v"))
# bandwidth
self.submodules.bandwidth = EncoderBandwidth() # XXX add CDC
self.comb += self.bandwidth.nbytes_inc.eq(self.source.stb
& self.source.ack)