def __init__(self, cd, async_reset):
if not hasattr(async_reset, "attr"):
i, async_reset = async_reset, Signal()
self.comb += async_reset.eq(i)
rst_meta = Signal()
self.specials += [
Instance(
"FDPE",
attr={"async_reg", "ars_ff1"},
p_INIT=1,
i_PRE=async_reset,
i_CE=1,
i_C=cd.clk,
i_D=0,
o_Q=rst_meta,
),
Instance("FDPE",
attr={"async_reg", "ars_ff2"},
p_INIT=1,
i_PRE=async_reset,
i_CE=1,
i_C=cd.clk,
i_D=rst_meta,
o_Q=cd.rst)
]
def __init__(self, cd, async_reset):
rst1 = Signal()
self.specials += [
Instance("SB_DFFS", i_D=0, i_S=async_reset,
i_C=cd.clk, o_Q=rst1),
Instance("SB_DFFS", i_D=rst1, i_S=async_reset,
i_C=cd.clk, o_Q=cd.rst)
]
def __init__(self, cd, async_reset):
rst1 = Signal()
self.specials += [
Instance("FD1S3BX", i_D=0, i_PD=async_reset,
i_CK=cd.clk, o_Q=rst1),
Instance("FD1S3BX", i_D=rst1, i_PD=async_reset,
i_CK=cd.clk, o_Q=cd.rst)
]
def __init__(self, i, o_p, o_n):
self.specials += Instance("SB_IO",
p_PIN_TYPE=C(0b011000, 6),
p_IO_STANDARD="SB_LVCMOS",
io_PACKAGE_PIN=o_p,
i_D_OUT_0=i)
self.specials += Instance("SB_IO",
p_PIN_TYPE=C(0b011000, 6),
p_IO_STANDARD="SB_LVCMOS",
io_PACKAGE_PIN=o_n,
i_D_OUT_0=~i)
def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
reset_less = rst_name is None
self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
self._clk = platform.request(clk_name)
_add_period_constraint(platform, self._clk.p, period)
self.specials += Instance("IBUFGDS", Instance.Input("I", self._clk.p),
Instance.Input("IB", self._clk.n),
Instance.Output("O", self.cd_sys.clk))
if not reset_less:
if rst_invert:
self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
else:
self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
def __init__(self, cd, async_reset):
rst_meta = Signal()
self.specials += [
Instance("DFF",
i_d=0, i_clk=cd.clk,
i_clrn=1, i_prn=~async_reset,
o_q=rst_meta
),
Instance("DFF",
i_d=rst_meta, i_clk=cd.clk,
i_clrn=1, i_prn=~async_reset,
o_q=cd.rst
)
]
def __init__(self, i_p, i_n, o):
self.specials += Instance(
"SB_IO",
p_PIN_TYPE=C(0b000001, 6), # simple input pin
p_IO_STANDARD="SB_LVDS_INPUT",
io_PACKAGE_PIN=i_p,
o_D_IN_0=o)
def __init__(self, i, o1, o2, clk):
self.specials += Instance("IDDRX1F",
i_SCLK = clk,
i_D = i,
o_Q0 = o1,
o_Q1 = o2,
)
def __init__(self, i_p, i_n, o):
self.specials += Instance(
"ILVDS",
i_A=i_p,
i_AN=i_n,
o_Z=o,
)
def __init__(self, i, o, clk):
self.specials += Instance("FDCE",
i_C=clk,
i_CE=1,
i_CLR=0,
i_D=i,
o_Q=o)
def __init__(self, i1, i2, o, clk):
self.specials += Instance("ODDRX1F",
i_SCLK = clk,
i_D0 = i1,
i_D1 = i2,
o_Q = o,
)
def __init__(self, i, o1, o2, clk):
self.specials += Instance("ALTDDIO_IN",
p_WIDTH=1,
i_inclock=clk,
i_datain=i,
o_dataout_h=o1,
o_dataout_l=o2)
def __init__(self, i, o_p, o_n):
self.specials += Instance(
"OLVDS",
i_A=i,
o_Z=o_p,
o_ZN=o_n,
)
def __init__(self, i1, i2, o, clk):
self.specials += Instance("ODDRE1",
i_C=clk,
i_SR=0,
i_D1=i1,
i_D2=i2,
o_Q=o)
def __init__(self, i1, i2, o, clk):
self.specials += Instance("ALTDDIO_OUT",
p_WIDTH = 1,
i_outclock = clk,
i_datain_h = i1,
i_datain_l = i2,
o_dataout = o,
)
def __init__(self, i_p, i_n, o):
self.specials += [
Instance("ALT_INBUF_DIFF",
name="ibuf_diff",
i_i=i_p,
i_ibar=i_n,
o_o=o)
]
def __init__(self, i, o_p, o_n):
self.specials += [
Instance("ALT_OUTBUF_DIFF",
name="obuf_diff",
i_i=i,
o_o=o_p,
o_obar=o_n)
]
def __init__(self, i1, i2, o, clk):
self.specials += Instance(
"ODDRXD1",
synthesis_directive="ODDRAPPS=\"SCLK_ALIGNED\"",
i_SCLK=clk,
i_DA=i1,
i_DB=i2,
o_Q=o)
def __init__(self, i, o, clk):
self.specials += Instance("OFS1P3BX",
i_SCLK = clk,
i_PD = 0,
i_SP = 1,
i_D = i,
o_Q = o,
)
def __init__(self, i, o1, o2, clk):
self.specials += Instance("IDDRE1",
p_DDR_CLK_EDGE="SAME_EDGE_PIPELINED",
p_IS_C_INVERTED=0,
i_D=i,
o_Q1=o1, o_Q2=o2,
i_C=clk, i_CB=~clk,
i_R=0
)
def __init__(self, io, o, oe, i):
nbits, sign = value_bits_sign(io)
for bit in range(nbits):
self.specials += Instance("TRELLIS_IO",
p_DIR="BIDIR",
i_B=io[bit] if nbits > 1 else io,
i_I=o[bit] if nbits > 1 else o,
o_O=i[bit] if nbits > 1 else i,
i_T=~oe)
def __init__(self, cd, async_reset):
rst_meta = Signal(name_override=f'ars_cd_{cd.name}_rst_meta')
self.specials += [
Instance("DFF", name=f'ars_cd_{cd.name}_ff0',
i_d = 0,
i_clk = cd.clk,
i_clrn = 1,
i_prn = ~async_reset,
o_q = rst_meta
),
Instance("DFF", name=f'ars_cd_{cd.name}_ff1',
i_d = rst_meta,
i_clk = cd.clk,
i_clrn = 1,
i_prn = ~async_reset,
o_q = cd.rst
)
]
def __init__(self, i_p, i_n, o):
o_n = Signal.like(o)
self.specials += Instance(
"SB_IO",
p_PIN_TYPE=C(0b000001, 6), # simple input pin
p_IO_STANDARD="SB_LVDS_INPUT",
io_PACKAGE_PIN=i_n,
o_D_IN_0=o_n)
self.comb += o.eq(~o_n)
def __init__(self, i, o1, o2, clk):
self.specials += Instance("SB_IO",
p_PIN_TYPE = C(0b000000, 6), # PIN_INPUT_DDR
p_IO_STANDARD = "SB_LVCMOS",
io_PACKAGE_PIN = i,
i_CLOCK_ENABLE = 1,
i_INPUT_CLK = clk,
o_D_IN_0 = o1,
o_D_IN_1 = o2
)
def __init__(self, i1, i2, o, clk):
self.specials += Instance("SB_IO",
p_PIN_TYPE=C(0b010000, 6),
p_IO_STANDARD="SB_LVCMOS",
io_PACKAGE_PIN=o,
i_CLOCK_ENABLE=1,
i_OUTPUT_CLK=clk,
i_OUTPUT_ENABLE=1,
i_D_OUT_0=i1,
i_D_OUT_1=i2)
def __init__(self, i1, i2, o, clk):
self.specials += Instance("ODDR",
p_DDR_CLK_EDGE="SAME_EDGE",
i_C=clk,
i_CE=1,
i_S=0,
i_R=0,
i_D1=i1,
i_D2=i2,
o_Q=o)
def __init__(self, io, o, oe, i, clk):
self.specials += Instance("SB_IO",
p_PIN_TYPE = C(0b110100, 6), # PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED + PIN_INPUT_REGISTERED
io_PACKAGE_PIN = io,
i_INPUT_CLK = clk,
i_OUTPUT_CLK = clk,
i_OUTPUT_ENABLE = oe,
i_D_OUT_0 = o,
o_D_IN_0 = i,
)
def __init__(self, i, o1, o2, clk):
self.specials += Instance("IDDR",
p_DDR_CLK_EDGE="SAME_EDGE",
i_C=clk,
i_CE=1,
i_S=0,
i_R=0,
i_D=i,
o_Q1=o1,
o_Q2=o2)
def __init__(self, io, o, oe, i):
nbits, sign = value_bits_sign(io)
for bit in range(nbits):
self.specials += Instance("SB_IO",
p_PIN_TYPE = C(0b101001, 6), # PIN_OUTPUT_TRISTATE + PIN_INPUT
io_PACKAGE_PIN = io[bit] if nbits > 1 else io,
i_OUTPUT_ENABLE = oe,
i_D_OUT_0 = o[bit] if nbits > 1 else o,
o_D_IN_0 = i[bit] if nbits > 1 else i,
)
def __init__(self, cd, async_reset):
rst1 = Signal()
self.specials += [
Instance("FDPE",
p_INIT=1,
i_D=0,
i_PRE=async_reset,
i_CE=1,
i_C=cd.clk,
o_Q=rst1),
Instance("FDPE",
p_INIT=1,
i_D=rst1,
i_PRE=async_reset,
i_CE=1,
i_C=cd.clk,
o_Q=cd.rst)
]
rst1.attr.add("async_reg")
cd.rst.attr.add("async_reg")
