def __init__(self, cpu_type="or1k", **kwargs):
MiniSoC.__init__(self,
cpu_type=cpu_type,
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
self.platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])
if isinstance(self.platform.toolchain, XilinxISEToolchain):
self.platform.toolchain.bitgen_opt += " -g compress"
self.submodules.leds = gpio.GPIOOut(
Cat(self.platform.request("user_led", 0),
self.platform.request("user_led", 1)))
self.csr_devices.append("leds")
self.platform.add_extension(_sma33_io)
self.platform.add_extension(_ams101_dac)
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_DDS"] = None
def __init__(self, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
**kwargs)
platform = self.platform
rtio_clk_freq = 150e6
disable_si5324_ibuf = Signal(reset=1)
disable_si5324_ibuf.attr.add("no_retiming")
si5324_clkout = platform.request("si5324_clkout")
si5324_clkout_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=disable_si5324_ibuf,
i_I=si5324_clkout.p,
i_IB=si5324_clkout.n,
o_O=si5324_clkout_buf)
qpll_drtio_settings = QPLLSettings(refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
self.submodules += qpll
self.comb += platform.request("sfp_ctl", 0).tx_disable.eq(0)
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0],
data_pads=[platform.request("sfp", 0)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += disable_si5324_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
si5324_clkout_fabric=platform.request("si5324_clkout_fabric"))
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
rtio_clk_period = 1e9 / rtio_clk_freq
gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp.txoutclk,
gtp.rxoutclk)
self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
fix_serdes_timing_path(platform)
def __init__(self, gateware_identifier_str=None, hw_rev="v2.0", **kwargs):
if hw_rev in ("v1.0", "v1.1"):
cpu_bus_width = 32
else:
cpu_bus_width = 64
MiniSoC.__init__(self,
cpu_type="vexriscv",
hw_rev=hw_rev,
cpu_bus_width=cpu_bus_width,
sdram_controller_type="minicon",
l2_size=128 * 1024,
integrated_sram_size=8192,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
add_identifier(self, gateware_identifier_str=gateware_identifier_str)
if self.platform.hw_rev == "v2.0":
self.submodules.error_led = gpio.GPIOOut(
Cat(self.platform.request("error_led")))
self.csr_devices.append("error_led")
self.submodules += SMAClkinForward(self.platform)
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
def __init__(self):
platform = self.platform
# forward RTM UART to second FTDI UART channel
serial_1 = platform.request("serial", 1)
serial_rtm = platform.request("serial_rtm")
self.comb += [
serial_1.tx.eq(serial_rtm.rx),
serial_rtm.tx.eq(serial_1.rx)
]
# RTM bitstream upload
slave_fpga_cfg = self.platform.request("rtm_fpga_cfg")
self.submodules.slave_fpga_cfg = gpio.GPIOTristate([
slave_fpga_cfg.cclk,
slave_fpga_cfg.din,
slave_fpga_cfg.done,
slave_fpga_cfg.init_b,
slave_fpga_cfg.program_b,
])
self.csr_devices.append("slave_fpga_cfg")
self.config["SLAVE_FPGA_GATEWARE"] = 0x200000
# AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb")
serwb_phy_amc = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="master")
self.submodules.serwb_phy_amc = serwb_phy_amc
self.csr_devices.append("serwb_phy_amc")
serwb_core = serwb.core.SERWBCore(serwb_phy_amc, int(self.clk_freq), mode="slave")
self.submodules += serwb_core
self.add_wb_slave(self.mem_map["serwb"], 8192, serwb_core.etherbone.wishbone.bus)
def __init__(self, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
self.submodules.leds = gpio.GPIOOut(
Cat(self.platform.request("user_led", 0)))
self.csr_devices.append("leds")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
def __init__(self,
gateware_identifier_str=None,
drtio_100mhz=False,
**kwargs):
MiniSoC.__init__(self,
cpu_type="vexriscv",
cpu_bus_width=64,
sdram_controller_type="minicon",
l2_size=128 * 1024,
integrated_sram_size=8192,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
add_identifier(self, gateware_identifier_str=gateware_identifier_str)
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
self.platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])
if isinstance(self.platform.toolchain, XilinxISEToolchain):
self.platform.toolchain.bitgen_opt += " -g compress"
self.submodules.timer1 = timer.Timer()
self.csr_devices.append("timer1")
self.interrupt_devices.append("timer1")
self.submodules.leds = gpio.GPIOOut(
Cat(self.platform.request("user_led", 0),
self.platform.request("user_led", 1)))
self.csr_devices.append("leds")
self.platform.add_extension(_reprogrammed3v3_io)
self.platform.add_extension(_ams101_dac)
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_DDS"] = None
def __init__(self, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
integrated_sram_size=8192,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
add_identifier(self)
self.submodules.leds = gpio.GPIOOut(
Cat(self.platform.request("user_led", 0)))
self.csr_devices.append("leds")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
def __init__(self, rtio_clk_freq, *, with_wrpll, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
**kwargs)
add_identifier(self)
self.rtio_clk_freq = rtio_clk_freq
platform = self.platform
disable_cdrclkc_ibuf = Signal(reset=1)
disable_cdrclkc_ibuf.attr.add("no_retiming")
cdrclkc_clkout = platform.request("cdr_clk_clean")
cdrclkc_clkout_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=disable_cdrclkc_ibuf,
i_I=cdrclkc_clkout.p, i_IB=cdrclkc_clkout.n,
o_O=cdrclkc_clkout_buf)
qpll_drtio_settings = QPLLSettings(
refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(cdrclkc_clkout_buf, qpll_drtio_settings)
self.submodules += qpll
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0],
data_pads=[platform.request("rtm_amc_link", 0)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += disable_cdrclkc_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
core = cdr(DRTIOSatellite(
self.rtio_tsc, self.drtio_transceiver.channels[0],
self.rx_synchronizer))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
coreaux = cdr(DRTIOAuxController(core.link_layer))
self.submodules.drtioaux0 = coreaux
self.csr_devices.append("drtioaux0")
memory_address = self.mem_map["drtioaux"]
self.add_wb_slave(memory_address, 0x800,
coreaux.bus)
self.add_memory_region("drtioaux0_mem", memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtioaux", ["drtioaux0"])
self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
gtp = self.drtio_transceiver.gtps[0]
rtio_clk_period = 1e9/rtio_clk_freq
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
if with_wrpll:
self.comb += [
platform.request("filtered_clk_sel").eq(0),
platform.request("ddmtd_main_dcxo_oe").eq(1),
platform.request("ddmtd_helper_dcxo_oe").eq(1)
]
self.submodules.wrpll_sampler = DDMTDSamplerGTP(
self.drtio_transceiver,
platform.request("cdr_clk_clean_fabric"))
self.submodules.wrpll = WRPLL(
helper_clk_pads=platform.request("ddmtd_helper_clk"),
main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"),
ddmtd_inputs=self.wrpll_sampler)
self.csr_devices.append("wrpll")
platform.add_period_constraint(self.wrpll.cd_helper.clk, rtio_clk_period*0.99)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.wrpll.cd_helper.clk)
platform.add_false_path_constraints(self.wrpll.cd_helper.clk, gtp.rxoutclk)
else:
self.comb += platform.request("filtered_clk_sel").eq(1)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ref_clk=self.crg.cd_sys.clk, ref_div2=True,
rtio_clk_freq=rtio_clk_freq)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk)
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform)
def __init__(self, rtio_clk_freq=150e6, **kwargs):
BaseSoC.__init__(self, cpu_type="or1k", **kwargs)
add_identifier(self)
platform = self.platform
disable_si5324_ibuf = Signal(reset=1)
disable_si5324_ibuf.attr.add("no_retiming")
si5324_clkout = platform.request("cdr_clk_clean")
si5324_clkout_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=disable_si5324_ibuf,
i_I=si5324_clkout.p,
i_IB=si5324_clkout.n,
o_O=si5324_clkout_buf)
qpll_drtio_settings = QPLLSettings(refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
self.submodules += qpll
if self.hw_rev == "v1.0":
drtio_data_pads = platform.request("sata", 0)
elif self.hw_rev == "v2.0":
drtio_data_pads = platform.request("rtm_amc_link", 0)
else:
raise NotImplementedError
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0],
data_pads=[drtio_data_pads],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += disable_si5324_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
core = cdr(
DRTIOSatellite(self.rtio_tsc, self.drtio_transceiver.channels[0],
self.rx_synchronizer))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
coreaux = cdr(DRTIOAuxController(core.link_layer))
self.submodules.drtioaux0 = coreaux
self.csr_devices.append("drtioaux0")
memory_address = self.mem_map["drtioaux"]
self.add_wb_slave(memory_address, 0x800, coreaux.bus)
self.add_memory_region("drtioaux0_mem",
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtioaux", ["drtioaux0"])
self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ref_clk=self.crg.cd_sys.clk,
ref_div2=True,
rtio_clk_freq=rtio_clk_freq)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
rtio_clk_period = 1e9 / rtio_clk_freq
gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp.txoutclk,
gtp.rxoutclk)
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform)
def __init__(self, identifier_str=None, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
integrated_sram_size=8192,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
csr_address_width=15,
**kwargs)
AMPSoC.__init__(self)
add_identifier(self, identifier_str=identifier_str)
platform = self.platform
rtio_clk_freq = 150e6
self.comb += platform.request("input_clk_sel").eq(1)
self.comb += platform.request("filtered_clk_sel").eq(1)
self.submodules.si5324_rst_n = gpio.GPIOOut(
platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("cdr_clk_clean", 0),
data_pads=[platform.request("mch_fabric_d", i) for i in range(11)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
drtio_csr_group = []
drtioaux_csr_group = []
drtioaux_memory_group = []
drtio_cri = []
for i in range(len(self.drtio_transceiver.channels)):
core_name = "drtio" + str(i)
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtio_csr_group.append(core_name)
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
core = cdr(
DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800 * i
self.add_wb_slave(memory_address, 0x800, coreaux.bus)
self.add_memory_region(memory_name,
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtio", drtio_csr_group)
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
rtio_clk_period = 1e9 / rtio_clk_freq
gth0 = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth0.txoutclk, rtio_clk_period / 2)
platform.add_period_constraint(gth0.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gth0.txoutclk,
gth0.rxoutclk)
for gth in self.drtio_transceiver.gths[1:]:
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
gth0.txoutclk, gth.rxoutclk)
self.rtio_channels = rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
eem.DIO.add_std(self,
2,
ttl_simple.Output,
ttl_simple.Output,
iostandard="LVDS")
eem.Urukul.add_std(self, 0, 1, ttl_simple.Output, iostandard="LVDS")
eem.Zotino.add_std(self, 3, ttl_simple.Output, iostandard="LVDS")
workaround_us_lvds_tristate(platform)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri] + drtio_cri,
enable_routing=True)
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
def __init__(self, with_sawg, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
**kwargs)
RTMCommon.__init__(self)
add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
self.config["HMC830_REF"] = "150"
platform = self.platform
rtio_clk_freq = 150e6
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(
platform, use_rtio_clock=True)
if with_sawg:
cls = AD9154
else:
cls = AD9154NoSAWG
self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
self.csr_devices.append("ad9154_crg")
self.csr_devices.append("ad9154_0")
self.csr_devices.append("ad9154_1")
self.config["HAS_AD9154"] = None
self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(
rtio.Channel.from_phy(phy)
for sawg in self.ad9154_0.sawgs + self.ad9154_1.sawgs
for phy in sawg.phys)
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
drtio_data_pads = [platform.request("sfp", 0)]
if self.hw_rev == "v2.0":
drtio_data_pads.append(platform.request("rtm_amc_link"))
self.comb += platform.request("sfp_tx_disable", 0).eq(0)
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("cdr_clk_clean"),
data_pads=drtio_data_pads,
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
self.submodules.drtiosat = rx0(
DRTIOSatellite(self.rtio_tsc, self.drtio_transceiver.channels[0],
self.rx_synchronizer))
self.csr_devices.append("drtiosat")
self.submodules.drtioaux0 = rx0(
DRTIOAuxController(self.drtiosat.link_layer))
self.csr_devices.append("drtioaux0")
self.add_wb_slave(self.mem_map["drtioaux"], 0x800, self.drtioaux0.bus)
self.add_memory_region("drtioaux0_mem",
self.mem_map["drtioaux"] | self.shadow_base,
0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtioaux", ["drtioaux0"])
self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
self.comb += [
self.drtiosat.cri.connect(self.local_io.cri),
self.drtiosat.async_errors.eq(self.local_io.async_errors),
]
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ultrascale=True,
rtio_clk_freq=rtio_clk_freq)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
self.submodules.si5324_rst_n = gpio.GPIOOut(
platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
platform.request("dac_sysref"), self.rtio_tsc.coarse_ts)
self.csr_devices.append("sysref_sampler")
self.ad9154_0.jesd.core.register_jref(self.sysref_sampler.jref)
self.ad9154_1.jesd.core.register_jref(self.sysref_sampler.jref)
rtio_clk_period = 1e9 / rtio_clk_freq
gth = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth.txoutclk, rtio_clk_period / 2)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk,
gth.rxoutclk)
# placeholder code to test I/O routing and standards
if self.hw_rev == "v2.0":
self.clock_domains.cd_ddmtd_helper = ClockDomain(reset_less=True)
helper_clk = platform.request("ddmtd_helper_clk")
self.specials += Instance("IBUFGDS",
i_I=helper_clk.p,
i_IB=helper_clk.n,
o_O=self.cd_ddmtd_helper.clk)
ddmtd = platform.request("ddmtd_results")
self.sync.ddmtd_helper += platform.request("tp16").eq(
ddmtd.rec_clk ^ ddmtd.main_xo)
def __init__(self, gateware_identifier_str=None, sma_as_sat=False, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
integrated_sram_size=8192,
**kwargs)
add_identifier(self, gateware_identifier_str=gateware_identifier_str)
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
self.platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])
if isinstance(self.platform.toolchain, XilinxISEToolchain):
self.platform.toolchain.bitgen_opt += " -g compress"
platform = self.platform
self.comb += platform.request("sfp_tx_disable_n").eq(1)
tx_pads = [
platform.request("sfp_tx"), platform.request("user_sma_mgt_tx")
]
rx_pads = [
platform.request("sfp_rx"), platform.request("user_sma_mgt_rx")
]
if sma_as_sat:
tx_pads = tx_pads[::-1]
rx_pads = rx_pads[::-1]
# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
self.submodules.drtio_transceiver = gtx_7series.GTX(
clock_pads=platform.request("si5324_clkout"),
tx_pads=tx_pads,
rx_pads=rx_pads,
sys_clk_freq=self.clk_freq)
self.csr_devices.append("drtio_transceiver")
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
drtioaux_csr_group = []
drtioaux_memory_group = []
drtiorep_csr_group = []
self.drtio_cri = []
for i in range(len(self.drtio_transceiver.channels)):
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
# Satellite
if i == 0:
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
core = cdr(DRTIOSatellite(
self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
# Repeaters
else:
corerep_name = "drtiorep" + str(i-1)
drtiorep_csr_group.append(corerep_name)
core = cdr(DRTIORepeater(
self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, corerep_name, core)
self.drtio_cri.append(core.cri)
self.csr_devices.append(corerep_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i
self.add_wb_slave(memory_address, 0x800,
coreaux.bus)
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.add_csr_group("drtiorep", drtiorep_csr_group)
self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
# Si5324 Phaser
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ultrascale=False,
rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.comb += [
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
]
rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
# Constrain TX & RX timing for the first transceiver channel
# (First channel acts as master for phase alignment for all channels' TX)
gtx0 = self.drtio_transceiver.gtxs[0]
platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtx0.txoutclk, gtx0.rxoutclk)
# Constrain RX timing for the each transceiver channel
# (Each channel performs single-lane phase alignment for RX)
for gtx in self.drtio_transceiver.gtxs[1:]:
platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtx.rxoutclk)
rtio_channels = []
for i in range(8):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for sma in "user_sma_gpio_p", "user_sma_gpio_n":
phy = ttl_simple.InOut(platform.request(sma))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.drtiosat.cri],
[self.local_io.cri] + self.drtio_cri,
mode="sync", enable_routing=True)
self.csr_devices.append("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
def __init__(self, jdcg_type, **kwargs):
SatelliteBase.__init__(self,
150e6,
identifier_suffix="." + jdcg_type,
**kwargs)
platform = self.platform
self.submodules += RTMUARTForward(platform)
# RTM bitstream upload
slave_fpga_cfg = self.platform.request("rtm_fpga_cfg")
self.submodules.slave_fpga_cfg = gpio.GPIOTristate([
slave_fpga_cfg.cclk,
slave_fpga_cfg.din,
slave_fpga_cfg.done,
slave_fpga_cfg.init_b,
slave_fpga_cfg.program_b,
])
self.csr_devices.append("slave_fpga_cfg")
self.config["SLAVE_FPGA_GATEWARE"] = 0x200000
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
mcx_io = platform.request("mcx_io", 0)
phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
self.comb += mcx_io.direction.eq(phy.oe)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
mcx_io = platform.request("mcx_io", 1)
phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
self.comb += mcx_io.direction.eq(phy.oe)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.jesd_crg = jesd204_tools.UltrascaleCRG(
platform, use_rtio_clock=True)
cls = {
"sawg": JDCGSAWG,
"pattern": JDCGPattern,
"syncdds": JDCGSyncDDS
}[jdcg_type]
self.submodules.jdcg_0 = cls(platform, self.crg, self.jesd_crg, 0)
self.submodules.jdcg_1 = cls(platform, self.crg, self.jesd_crg, 1)
self.csr_devices.append("jesd_crg")
self.csr_devices.append("jdcg_0")
self.csr_devices.append("jdcg_1")
self.config["HAS_JDCG"] = None
self.add_csr_group("jdcg", ["jdcg_0", "jdcg_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(
rtio.Channel.from_phy(phy)
for sawg in self.jdcg_0.sawgs + self.jdcg_1.sawgs
for phy in sawg.phys)
self.add_rtio(rtio_channels)
self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
platform.request("amc_fpga_sysref", 0), self.rtio_tsc.coarse_ts)
self.csr_devices.append("sysref_sampler")
self.jdcg_0.jesd.core.register_jref(self.sysref_sampler.jref)
self.jdcg_1.jesd.core.register_jref(self.sysref_sampler.jref)
if jdcg_type == "syncdds":
self.comb += [
self.jdcg_0.coarse_ts.eq(self.rtio_tsc.coarse_ts),
self.jdcg_1.coarse_ts.eq(self.rtio_tsc.coarse_ts),
]
def __init__(self, rtio_clk_freq=150e6, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
add_identifier(self)
platform = self.platform
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
sfp_ctls = [platform.request("sfp_ctl", i) for i in range(1, 3)]
self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=self.drtio_qpll_channel,
data_pads=[platform.request("sfp", i) for i in range(1, 3)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += self.disable_si5324_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
self.comb += [sfp_ctl.led.eq(channel.rx_ready)
for sfp_ctl, channel in zip(sfp_ctls, self.drtio_transceiver.channels)]
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
drtio_csr_group = []
drtioaux_csr_group = []
drtioaux_memory_group = []
self.drtio_cri = []
for i in range(2):
core_name = "drtio" + str(i)
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtio_csr_group.append(core_name)
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
core = cdr(DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
self.drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i
self.add_wb_slave(memory_address, 0x800,
coreaux.bus)
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtio", drtio_csr_group)
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
rtio_clk_period = 1e9/rtio_clk_freq
gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk)
for gtp in self.drtio_transceiver.gtps[1:]:
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.rxoutclk)
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform)
def __init__(self, jdcg_type, **kwargs):
SatelliteBase.__init__(self, 150e6,
identifier_suffix="." + jdcg_type,
**kwargs)
platform = self.platform
self.submodules += RTMUARTForward(platform)
# RTM bitstream upload
slave_fpga_cfg = self.platform.request("rtm_fpga_cfg")
self.submodules.slave_fpga_cfg = gpio.GPIOTristate([
slave_fpga_cfg.cclk,
slave_fpga_cfg.din,
slave_fpga_cfg.done,
slave_fpga_cfg.init_b,
slave_fpga_cfg.program_b,
])
self.csr_devices.append("slave_fpga_cfg")
self.config["SLAVE_FPGA_GATEWARE"] = 0x200000
self.rtio_channels = rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
mcx_io = platform.request("mcx_io", 0)
phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
self.comb += mcx_io.direction.eq(phy.oe)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
mcx_io = platform.request("mcx_io", 1)
phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
self.comb += mcx_io.direction.eq(phy.oe)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.jesd_crg = jesd204_tools.UltrascaleCRG(
platform, use_rtio_clock=True)
cls = {
"sawg": JDCGSAWG,
"pattern": JDCGPattern,
"syncdds": JDCGSyncDDS
}[jdcg_type]
self.submodules.jdcg_0 = cls(platform, self.crg, self.jesd_crg, 0)
self.submodules.jdcg_1 = cls(platform, self.crg, self.jesd_crg, 1)
self.csr_devices.append("jesd_crg")
self.csr_devices.append("jdcg_0")
self.csr_devices.append("jdcg_1")
self.config["HAS_JDCG"] = None
self.add_csr_group("jdcg", ["jdcg_0", "jdcg_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(rtio.Channel.from_phy(phy)
for sawg in self.jdcg_0.sawgs +
self.jdcg_1.sawgs
for phy in sawg.phys)
# FMC-VHDCI-EEM DIOs x 2 (all OUTPUTs)
platform.add_connectors(fmcdio_vhdci_eem.connectors)
output_4x = partial(ttl_serdes_ultrascale.Output, 4)
eem.DIO.add_std(self, 0,
output_4x, output_4x,
iostandard=lambda eem: IOStandard("LVDS"))
eem.DIO.add_std(self, 1,
output_4x, output_4x,
iostandard=lambda eem: IOStandard("LVDS"))
# FMC-DIO-32ch-LVDS-a Direction Control Pins (via shift register) as TTLs x 3
platform.add_extension(fmcdio_vhdci_eem.io)
print("fmcdio_vhdci_eem.[CLK, SER, LATCH] starting at RTIO channel 0x{:06x}"
.format(len(rtio_channels)))
fmcdio_dirctl = platform.request("fmcdio_dirctl", 0)
fmcdio_dirctl_phys = [
ttl_simple.Output(fmcdio_dirctl.clk),
ttl_simple.Output(fmcdio_dirctl.ser),
ttl_simple.Output(fmcdio_dirctl.latch)
]
for phy in fmcdio_dirctl_phys:
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
workaround_us_lvds_tristate(platform)
self.add_rtio(rtio_channels)
self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
platform.request("amc_fpga_sysref", 0), self.rtio_tsc.coarse_ts)
self.csr_devices.append("sysref_sampler")
self.jdcg_0.jesd.core.register_jref(self.sysref_sampler.jref)
self.jdcg_1.jesd.core.register_jref(self.sysref_sampler.jref)
if jdcg_type == "syncdds":
self.comb += [
self.jdcg_0.coarse_ts.eq(self.rtio_tsc.coarse_ts),
self.jdcg_1.coarse_ts.eq(self.rtio_tsc.coarse_ts),
]
def __init__(self, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
ident=artiq_version,
**kwargs)
platform = self.platform
rtio_channels = []
for i in range(8):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
for sma in "user_sma_gpio_p", "user_sma_gpio_n":
phy = ttl_simple.InOut(platform.request(sma))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.comb += platform.request("sfp_tx_disable_n").eq(1)
# 1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
clock_pads=platform.request("si5324_clkout"),
tx_pads=platform.request("sfp_tx"),
rx_pads=platform.request("sfp_rx"),
sys_clk_freq=self.clk_freq)
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.rx_synchronizer0 = rx0(gtx_7series.RXSynchronizer(
self.transceiver.rtio_clk_freq, initial_phase=180.0))
self.submodules.drtio0 = rx0(DRTIOSatellite(
self.transceiver.channels[0], rtio_channels, self.rx_synchronizer0))
self.csr_devices.append("rx_synchronizer0")
self.csr_devices.append("drtio0")
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
self.drtio0.aux_controller.bus)
self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", ["drtio0"])
self.add_memory_group("drtio_aux", ["drtio0_aux"])
self.config["RTIO_FREQUENCY"] = str(self.transceiver.rtio_clk_freq/1e6)
si5324_clkin = platform.request("si5324_clkin")
self.specials += \
Instance("OBUFDS",
i_I=ClockSignal("rtio_rx0"),
o_O=si5324_clkin.p, o_OB=si5324_clkin.n
)
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
platform.add_extension(ad9154_fmc_ebz)
ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi")
self.comb += [
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
]
rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
platform.lookup_request("clk200"),
self.transceiver.txoutclk, self.transceiver.rxoutclk)
def __init__(self, with_sawg, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
if with_sawg:
warnings.warn("SAWG is not implemented yet with DRTIO, ignoring.")
platform = self.platform
rtio_clk_freq = 150e6
self.submodules += Microscope(platform.request("serial", 1),
self.clk_freq)
# Si5324 used as a free-running oscillator, to avoid dependency on RTM.
self.submodules.si5324_rst_n = gpio.GPIOOut(
platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
self.comb += [
platform.request("sfp_tx_disable", i).eq(0) for i in range(2)
]
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("si5324_clkout"),
data_pads=[platform.request("sfp", i) for i in range(2)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
drtio_csr_group = []
drtio_memory_group = []
drtio_cri = []
for i in range(2):
core_name = "drtio" + str(i)
memory_name = "drtio" + str(i) + "_aux"
drtio_csr_group.append(core_name)
drtio_memory_group.append(memory_name)
core = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})(
DRTIOMaster(self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
memory_address = self.mem_map["drtio_aux"] + 0x800 * i
self.add_wb_slave(memory_address, 0x800, core.aux_controller.bus)
self.add_memory_region(memory_name,
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", drtio_csr_group)
self.add_memory_group("drtio_aux", drtio_memory_group)
rtio_clk_period = 1e9 / rtio_clk_freq
gth = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk,
gth.rxoutclk)
for gth in self.drtio_transceiver.gths[1:]:
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
gth.rxoutclk)
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(rtio_channels,
glbl_fine_ts_width=3)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri] + drtio_cri)
self.register_kernel_cpu_csrdevice("cri_con")
def __init__(self, with_sawg, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
**kwargs)
RTMCommon.__init__(self)
add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
self.config["HMC830_REF"] = "150"
platform = self.platform
rtio_clk_freq = 150e6
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(
platform, use_rtio_clock=True)
if with_sawg:
cls = AD9154
else:
cls = AD9154NoSAWG
self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
self.csr_devices.append("ad9154_crg")
self.csr_devices.append("ad9154_0")
self.csr_devices.append("ad9154_1")
self.config["HAS_AD9154"] = None
self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(rtio.Channel.from_phy(phy)
for sawg in self.ad9154_0.sawgs +
self.ad9154_1.sawgs
for phy in sawg.phys)
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.comb += platform.request("sfp_tx_disable", 0).eq(0)
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("si5324_clkout"),
data_pads=[platform.request("sfp", 0)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
self.submodules.drtiosat = rx0(DRTIOSatellite(
self.rtio_tsc, self.drtio_transceiver.channels[0],
self.rx_synchronizer))
self.csr_devices.append("drtiosat")
self.submodules.drtioaux0 = rx0(DRTIOAuxController(
self.drtiosat.link_layer))
self.csr_devices.append("drtioaux0")
self.add_wb_slave(self.mem_map["drtioaux"], 0x800,
self.drtioaux0.bus)
self.add_memory_region("drtioaux0_mem", self.mem_map["drtioaux"] | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtioaux", ["drtioaux0"])
self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
self.comb += [
self.drtiosat.cri.connect(self.local_io.cri),
self.drtiosat.async_errors.eq(self.local_io.async_errors),
]
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
si5324_clkout_fabric=platform.request("si5324_clkout_fabric"))
platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]",
mmcm_ps=self.siphaser.mmcm_ps_output)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
self.rtio_tsc.coarse_ts, self.ad9154_crg.jref)
self.csr_devices.append("sysref_sampler")
rtio_clk_period = 1e9/rtio_clk_freq
gth = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gth.txoutclk, gth.rxoutclk)
def __init__(self, with_sawg, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
RTMCommon.__init__(self)
add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
self.config["HMC830_REF"] = "100"
platform = self.platform
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["SI5324_SAYMA_REF"] = None
# ensure pins are properly biased and terminated
si5324_clkout = platform.request("si5324_clkout", 0)
self.specials += Instance(
"IBUFDS_GTE3", i_CEB=0, i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
attr={("DONT_TOUCH", "true")})
# RTIO
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
if with_sawg:
cls = AD9154
else:
cls = AD9154NoSAWG
self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
self.csr_devices.append("ad9154_crg")
self.csr_devices.append("ad9154_0")
self.csr_devices.append("ad9154_1")
self.config["HAS_AD9154"] = None
self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(rtio.Channel.from_phy(phy)
for sawg in self.ad9154_0.sawgs +
self.ad9154_1.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.clock_domains.cd_rtio = ClockDomain()
self.comb += [
self.cd_rtio.clk.eq(ClockSignal("jesd")),
self.cd_rtio.rst.eq(ResetSignal("jesd"))
]
self.submodules.rtio_tsc = rtio.TSC("async")
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(
rtio.DMA(self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri])
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri,
self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
self.rtio_tsc.coarse_ts, self.ad9154_crg.jref)
self.csr_devices.append("sysref_sampler")
def add_std(cls,
target,
fmc,
iostd_single,
iostd_diff,
with_trig=False,
adc_daq_samples=1024,
tdc_daq_samples=1024):
cls.add_extension(target, fmc, iostd_single, iostd_diff)
# CFD DAC I2C
dac_i2c = target.platform.request(cls.signal_name("dac_i2c", fmc))
bus_id = target.add_i2c_bus(dac_i2c.scl, dac_i2c.sda,
f"FMC{fmc} DAC I2C")
target.submodules.i2c = gpio.GPIOTristate([dac_i2c.scl, dac_i2c.sda])
target.csr_devices.append("i2c")
for i, address in enumerate([0x48, 0x49]):
target.register_coredevice(device_id=f"fmc{fmc}_cfd_offset_dac{i}",
module="elhep_cores.coredevice.dac7578",
class_name="DAC7578",
arguments={
"busno": 0,
"address": address << 1
}) # FIXME: use valid bus id
# IOs
for i in range(4):
pads = target.platform.request(cls.signal_name("tdc_dis", fmc), i)
phy = Output(pads.p, pads.n)
target.submodules += phy
target.add_rtio_channels(channel=rtio.Channel.from_phy(phy),
device_id=f"fmc{fmc}_tdc_dis{i}",
module="artiq.coredevice.ttl",
class_name="TTLOut")
for sn in [
"idx_in", "adc_resetn", "adc_sync", "trig_term", "trig_dir",
"ref_sel", "idx_src_sel"
]:
pads = target.platform.request(cls.signal_name(sn, fmc), 0)
if hasattr(pads, "p"):
phy = Output(pads.p, pads.n)
else:
phy = Output(pads)
target.submodules += phy
target.add_rtio_channels(channel=rtio.Channel.from_phy(phy),
device_id=f"fmc{fmc}_{sn}",
module="artiq.coredevice.ttl",
class_name="TTLOut")
# SPI Configuration interfaces
tdc_spi = target.platform.request(cls.signal_name("tdc_spi", fmc), 0)
tdc_spi_pads = Signal()
tdc_spi_pads.clk = tdc_spi.sck
tdc_spi_pads.miso = tdc_spi.miso
tdc_spi_pads.mosi = tdc_spi.mosi
tdc_spi_pads.cs_n = Signal(5)
phy = SPIMaster(tdc_spi_pads)
target.submodules += phy
target.add_rtio_channels(channel=rtio.Channel.from_phy(phy),
device_id=f"fmc{fmc}_tdc_spi",
module="artiq.coredevice.spi2",
class_name="SPIMaster")
adc_spi = target.platform.request(cls.signal_name("adc_spi", fmc), 0)
adc_spi_pads = Signal()
adc_spi_pads.clk = adc_spi.sck
adc_spi_pads.miso = adc_spi.miso
adc_spi_pads.mosi = adc_spi.mosi
adc_spi_pads.cs_n = Signal(2)
phy = SPIMaster(adc_spi_pads)
target.submodules += phy
target.add_rtio_channels(channel=rtio.Channel.from_phy(phy),
device_id=f"fmc{fmc}_adc_spi",
module="artiq.coredevice.spi2",
class_name="SPIMaster")
csn_pads = [
*[
target.platform.request(cls.signal_name("tdc_spi_csn", fmc), i)
for i in range(5)
], *[
target.platform.request(cls.signal_name("adc_spi_csn", fmc), i)
for i in range(2)
]
]
for i, pad in enumerate(csn_pads):
phy = Output(pad)
target.submodules += phy
target.add_rtio_channels(channel=rtio.Channel.from_phy(phy),
device_id=f"fmc{fmc}_csn{i}",
module="artiq.coredevice.ttl",
class_name="TTLOut")
# Clocking
target.register_coredevice(device_id=f"fmc{fmc}_clock_dist",
module="elhep_cores.coredevice.ad9528",
class_name="AD9528",
arguments={
"spi_device": f"fmc{fmc}_tdc_spi",
"chip_select": f"fmc{fmc}_csn4"
})
# ADC
for adc_id in range(2):
dclk_name = "fmc{}_adc{}_dclk".format(fmc, adc_id)
adc_lclk = target.platform.request(
cls.signal_name("adc_out_lclk", fmc), adc_id)
phy = ADS5296A_XS7(adclk_i=target.platform.request(
cls.signal_name("adc_out_adclk", fmc), adc_id),
lclk_i=adc_lclk,
dat_i=[
target.platform.request(
cls.signal_name(
"adc_out_out{}".format(i), fmc),
adc_id) for i in range(8)
])
target.platform.add_period_constraint(adc_lclk.p, 2.)
target.platform.add_period_constraint(phy.cd_adclk_clkdiv.clk, 10.)
target.platform.add_period_constraint(phy.lclk_bufio, 2.)
target.platform.add_period_constraint(phy.lclk, 10.)
phy_renamed_cd = ClockDomainsRenamer({"adclk_clkdiv":
dclk_name})(phy)
setattr(target.submodules, "fmc{}_adc{}_phy".format(fmc, adc_id),
phy_renamed_cd)
target.add_rtio_channels(
channel=rtio.Channel.from_phy(phy.csr),
device_id=f"fmc{fmc}_adc{adc_id}_phycsr",
module="elhep_cores.coredevice.rtlink_csr",
class_name="RtlinkCsr",
arguments={"regs": phy.csr.regs})
target.register_coredevice(
device_id=f"fmc{fmc}_adc{adc_id}_control",
module="elhep_cores.coredevice.ads5296a",
class_name="ADS5296A",
arguments={
"spi_device": f"fmc{fmc}_adc_spi",
"phy_csr": f"fmc{fmc}_adc{adc_id}_phycsr",
"chip_select": f"fmc{fmc}_csn{adc_id+5}",
"spi_freq": 500_000
})
# TDC
for tdc_id in range(4):
dclk_name = "fmc{}_tdc{}_dclk".format(fmc, tdc_id)
fs = [
target.platform.request(
cls.signal_name("tdc_out_frame{}".format(i), fmc), tdc_id)
for i in range(4)
]
ds = [
target.platform.request(
cls.signal_name("tdc_out_sdo{}".format(i), fmc), tdc_id)
for i in range(4)
]
phy = TdcGpx2Phy(data_clk_i=target.platform.request(
cls.signal_name("tdc_out_lclkout", fmc), tdc_id),
frame_signals_i=fs,
data_signals_i=ds)
target.platform.add_period_constraint(phy.cd_dclk.clk, 4.)
phy_renamed_cd = ClockDomainsRenamer({"dclk": dclk_name})(phy)
setattr(target.submodules, "fmc{}_tdc{}_phy".format(fmc, tdc_id),
phy_renamed_cd)
for idx, channel in enumerate(phy.phy_channels):
target.add_rtio_channels(
channel=rtio.Channel.from_phy(channel.csr),
device_id=f"fmc{fmc}_tdc{tdc_id}_phycsr_{idx}",
module="elhep_cores.coredevice.rtlink_csr",
class_name="RtlinkCsr",
arguments={"regs": channel.csr.regs})
target.register_coredevice(
device_id=f"fmc{fmc}_tdc{tdc_id}_control",
module="elhep_cores.coredevice.tdc_gpx2",
class_name="TDCGPX2",
arguments={
"spi_device": f"fmc{fmc}_tdc_spi",
"phy_csr_prefix": f"fmc{fmc}_tdc{tdc_id}_phycsr_",
"chip_select": f"fmc{fmc}_csn{tdc_id+0}",
"spi_freq": 1_000_000
})
if with_trig:
pads = target.platform.request(cls.signal_name("trig", fmc))
phy = ttl_serdes_7series.InOut_8X(pads.p, pads.n)
target.submodules += phy
target.add_rtio_channels(channel=rtio.Channel.from_phy(
phy, ififo_depth=64),
device_id=f"fmc{fmc}_trig",
module="artiq.coredevice.ttl",
class_name="TTLInOut")
# Frequency counters
clk0_m2c_pads = target.platform.request(f"fmc{fmc}_clk0_m2c")
phy_clk0_m2c = Input(clk0_m2c_pads.p, clk0_m2c_pads.n)
clk0_m2c_edge_counter = SimpleEdgeCounter(phy_clk0_m2c.input_state)
target.submodules += [phy_clk0_m2c, clk0_m2c_edge_counter]
target.add_rtio_channels(channel=rtio.Channel.from_phy(phy_clk0_m2c),
device_id=f"fmc{fmc}_clk0_m2c_ttl_input",
module="artiq.coredevice.ttl",
class_name="TTLInOut")
target.add_rtio_channels(
channel=rtio.Channel.from_phy(clk0_m2c_edge_counter),
device_id=f"fmc{fmc}_clk0_m2c_edge_counter",
module="artiq.coredevice.edge_counter",
class_name="EdgeCounter")
clk1_m2c_pads = target.platform.request(f"fmc{fmc}_clk1_m2c")
phy_clk1_m2c = Input(clk1_m2c_pads.p, clk1_m2c_pads.n)
clk1_m2c_edge_counter = SimpleEdgeCounter(phy_clk1_m2c.input_state)
target.submodules += [phy_clk1_m2c, clk1_m2c_edge_counter]
target.add_rtio_channels(channel=rtio.Channel.from_phy(phy_clk1_m2c),
device_id=f"fmc{fmc}_clk1_m2c_ttl_input",
module="artiq.coredevice.ttl",
class_name="TTLInOut")
target.add_rtio_channels(
channel=rtio.Channel.from_phy(clk1_m2c_edge_counter),
device_id=f"fmc{fmc}_clk1_m2c_edge_counter",
module="artiq.coredevice.edge_counter",
class_name="EdgeCounter")
# Debug counters
for adc_id in range(2):
adc_phy = getattr(target, f"fmc{fmc}_adc{adc_id}_phy")
phy_adc_lclk = Input(adc_phy.lclk)
phy_adc_lclk_counter = SimpleEdgeCounter(phy_adc_lclk.input_state)
target.submodules += [phy_adc_lclk, phy_adc_lclk_counter]
target.add_rtio_channels(
channel=rtio.Channel.from_phy(phy_adc_lclk),
device_id=f"fmc{fmc}_phy_adc{adc_id}_lclk_input",
module="artiq.coredevice.ttl",
class_name="TTLInOut")
target.add_rtio_channels(
channel=rtio.Channel.from_phy(phy_adc_lclk_counter),
device_id=f"fmc{fmc}_phy_adc{adc_id}_lclk_counter",
module="artiq.coredevice.edge_counter",
class_name="EdgeCounter")
# Register itself
target.register_coredevice(
device_id=f"fmc{fmc}",
module="elhep_cores.coredevice.fmc_adc100M_10b_tdc_16cha",
class_name="FmcAdc100M10bTdc16cha",
arguments={"prefix": "fmc1"})
def __init__(self, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
platform = self.platform
rtio_clk_freq = 150e6
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
self.sfp_ctl = [platform.request("sfp_ctl", i) for i in range(1, 3)]
self.comb += [sc.tx_disable.eq(0) for sc in self.sfp_ctl]
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=self.drtio_qpll_channel,
data_pads=[platform.request("sfp", i) for i in range(1, 3)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += self.disable_si5324_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
drtio_csr_group = []
drtio_memory_group = []
self.drtio_cri = []
for i in range(2):
core_name = "drtio" + str(i)
memory_name = "drtio" + str(i) + "_aux"
drtio_csr_group.append(core_name)
drtio_memory_group.append(memory_name)
core = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})(
DRTIOMaster(self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
self.drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
memory_address = self.mem_map["drtio_aux"] + 0x800*i
self.add_wb_slave(memory_address, 0x800,
core.aux_controller.bus)
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", drtio_csr_group)
self.add_memory_group("drtio_aux", drtio_memory_group)
rtio_clk_period = 1e9/rtio_clk_freq
gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk)
for gtp in self.drtio_transceiver.gtps[1:]:
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.rxoutclk)
self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
def __init__(self,
rtio_clk_freq=125e6,
enable_sata=False,
gateware_identifier_str=None,
hw_rev="v2.0",
**kwargs):
if hw_rev in ("v1.0", "v1.1"):
cpu_bus_width = 32
else:
cpu_bus_width = 64
MiniSoC.__init__(self,
cpu_type="vexriscv",
hw_rev=hw_rev,
cpu_bus_width=cpu_bus_width,
sdram_controller_type="minicon",
l2_size=128 * 1024,
integrated_sram_size=8192,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
add_identifier(self, gateware_identifier_str=gateware_identifier_str)
platform = self.platform
if platform.hw_rev == "v2.0":
self.submodules += SMAClkinForward(platform)
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
drtio_data_pads = []
if enable_sata:
drtio_data_pads.append(platform.request("sata"))
drtio_data_pads += [platform.request("sfp", i) for i in range(1, 3)]
if self.platform.hw_rev == "v2.0":
drtio_data_pads.append(platform.request("sfp", 3))
if self.platform.hw_rev in ("v1.0", "v1.1"):
sfp_ctls = [platform.request("sfp_ctl", i) for i in range(1, 3)]
self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=self.drtio_qpll_channel,
data_pads=drtio_data_pads,
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += self.disable_cdr_clk_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
if enable_sata:
sfp_channels = self.drtio_transceiver.channels[1:]
else:
sfp_channels = self.drtio_transceiver.channels
if self.platform.hw_rev in ("v1.0", "v1.1"):
self.comb += [
sfp_ctl.led.eq(channel.rx_ready)
for sfp_ctl, channel in zip(sfp_ctls, sfp_channels)
]
if self.platform.hw_rev == "v2.0":
self.comb += [
self.virtual_leds.get(i + 1).eq(channel.rx_ready)
for i, channel in enumerate(sfp_channels)
]
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
drtio_csr_group = []
drtioaux_csr_group = []
drtioaux_memory_group = []
self.drtio_cri = []
for i in range(len(self.drtio_transceiver.channels)):
core_name = "drtio" + str(i)
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtio_csr_group.append(core_name)
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
core = cdr(
DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
self.drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800 * i
self.add_wb_slave(memory_address, 0x800, coreaux.bus)
self.add_memory_region(memory_name,
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtio", drtio_csr_group)
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
rtio_clk_period = 1e9 / rtio_clk_freq
gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp.txoutclk,
gtp.rxoutclk)
for gtp in self.drtio_transceiver.gtps[1:]:
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
gtp.rxoutclk)
self.submodules.rtio_crg = RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform)
def __init__(self, with_sawg, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
platform = self.platform
# forward RTM UART to second FTDI UART channel
serial_1 = platform.request("serial", 1)
serial_rtm = platform.request("serial_rtm")
self.comb += [
serial_1.tx.eq(serial_rtm.rx),
serial_rtm.tx.eq(serial_1.rx)
]
# RTM bitstream upload
slave_fpga_cfg = self.platform.request("rtm_fpga_cfg")
self.submodules.slave_fpga_cfg = gpio.GPIOTristate([
slave_fpga_cfg.cclk,
slave_fpga_cfg.din,
slave_fpga_cfg.done,
slave_fpga_cfg.init_b,
slave_fpga_cfg.program_b,
])
self.csr_devices.append("slave_fpga_cfg")
# self.config["HAS_SLAVE_FPGA"] = None
self.config["SLAVE_FPGA_GATEWARE"] = 0x200000
# AMC/RTM serwb
serwb_pads = platform.request("amc_rtm_serwb")
serwb_phy_amc = serwb.phy.SERWBPHY(platform.device,
serwb_pads,
mode="master")
self.submodules.serwb_phy_amc = serwb_phy_amc
self.csr_devices.append("serwb_phy_amc")
serwb_core = serwb.core.SERWBCore(serwb_phy_amc,
int(self.clk_freq),
mode="slave")
self.submodules += serwb_core
self.add_wb_slave(self.mem_map["serwb"], 8192,
serwb_core.etherbone.wishbone.bus)
# RTIO
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
if with_sawg:
cls = AD9154
else:
cls = AD9154NoSAWG
self.submodules.ad9154_crg = AD9154CRG(platform)
self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
self.csr_devices.append("ad9154_crg")
self.csr_devices.append("ad9154_0")
self.csr_devices.append("ad9154_1")
self.config["HAS_AD9154"] = None
self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(
rtio.Channel.from_phy(phy)
for sawg in self.ad9154_0.sawgs + self.ad9154_1.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.clock_domains.cd_rtio = ClockDomain()
self.comb += [
self.cd_rtio.clk.eq(ClockSignal("jesd")),
self.cd_rtio.rst.eq(ResetSignal("jesd"))
]
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri])
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer(
self.rtio_core.cri, self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
def __init__(self, cpu_type="or1k", **kwargs):
MiniSoC.__init__(self,
cpu_type=cpu_type,
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
self.platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])
platform = self.platform
platform.add_extension(ad9154_fmc_ebz)
self.submodules.leds = gpio.GPIOOut(
Cat(platform.request("user_led", 0),
platform.request("user_led", 1)))
self.csr_devices.append("leds")
i2c = platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi")
self.config["CONVERTER_SPI_DAC_CS"] = 0
self.config["CONVERTER_SPI_CLK_CS"] = 1
self.config["HAS_AD9516"] = None
self.submodules.ad9154 = AD9154(platform)
self.csr_devices.append("ad9154")
rtio_channels = []
phy = ttl_serdes_7series.Inout_8X(platform.request("user_sma_gpio_n"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128))
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sysref_pads = platform.request("ad9154_sysref")
phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n)
self.submodules += phy
rtio_channels.append(
rtio.Channel.from_phy(phy, ififo_depth=32, ofifo_depth=2))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(
rtio.Channel.from_phy(phy) for sawg in self.ad9154.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_crg = _PhaserCRG(platform,
self.ad9154.jesd.cd_jesd.clk)
self.csr_devices.append("rtio_crg")
self.submodules.rtio_core = rtio.Core(rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator()
# self.submodules.rtio_dma = rtio.DMA(self.get_native_sdram_if())
self.register_kernel_cpu_csrdevice("rtio")
# self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri], # , self.rtio_dma.cri],
[self.rtio_core.cri])
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer(
self.rtio, self.rtio_core.cri.counter, self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.rtio_crg.cd_rtio.clk)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.ad9154.jesd.cd_jesd.clk)
for phy in self.ad9154.jesd.phys:
platform.add_false_path_constraints(self.crg.cd_sys.clk,
phy.gtx.cd_tx.clk)
def __init__(self, with_sawg, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ident=artiq_version,
**kwargs)
if with_sawg:
warnings.warn("SAWG is not implemented yet with DRTIO, ignoring.")
platform = self.platform
rtio_clk_freq = 150e6
self.submodules += Microscope(platform.request("serial", 1),
self.clk_freq)
self.submodules.rtio_clkmul = _RTIOClockMultiplier(
platform, rtio_clk_freq)
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_simple.Output(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_simple.InOut(sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.comb += platform.request("sfp_tx_disable", 0).eq(0)
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("si5324_clkout"),
data_pads=[platform.request("sfp", 0)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())
self.submodules.drtio0 = rx0(
DRTIOSatellite(self.drtio_transceiver.channels[0], rtio_channels,
self.rx_synchronizer))
self.csr_devices.append("drtio0")
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
self.drtio0.aux_controller.bus)
self.add_memory_region("drtio0_aux",
self.mem_map["drtio_aux"] | self.shadow_base,
0x800)
self.config["HAS_DRTIO"] = None
self.add_csr_group("drtio", ["drtio0"])
self.add_memory_group("drtio_aux", ["drtio0_aux"])
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
si5324_clkout_fabric=platform.request("si5324_clkout_fabric"))
platform.add_platform_command(
"set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {mmcm_ps}]",
mmcm_ps=self.siphaser.mmcm_ps_output)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
self.submodules.si5324_rst_n = gpio.GPIOOut(
platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
rtio_clk_period = 1e9 / rtio_clk_freq
gth = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk,
gth.rxoutclk)
def __init__(self,
rtio_clk_freq=125e6,
enable_sata=False,
*,
with_wrpll=False,
gateware_identifier_str=None,
**kwargs):
BaseSoC.__init__(self,
cpu_type="vexriscv",
sdram_controller_type="minicon",
l2_size=128 * 1024,
**kwargs)
add_identifier(self, gateware_identifier_str=gateware_identifier_str)
platform = self.platform
disable_cdr_clk_ibuf = Signal(reset=1)
disable_cdr_clk_ibuf.attr.add("no_retiming")
if self.platform.hw_rev == "v2.0":
cdr_clk_clean = self.platform.request("cdr_clk_clean")
else:
cdr_clk_clean = self.platform.request("si5324_clkout")
cdr_clk_clean_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=disable_cdr_clk_ibuf,
i_I=cdr_clk_clean.p,
i_IB=cdr_clk_clean.n,
o_O=cdr_clk_clean_buf)
qpll_drtio_settings = QPLLSettings(refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(cdr_clk_clean_buf, qpll_drtio_settings)
self.submodules += qpll
drtio_data_pads = []
if enable_sata:
drtio_data_pads.append(platform.request("sata"))
drtio_data_pads += [platform.request("sfp", i) for i in range(3)]
if self.platform.hw_rev == "v2.0":
drtio_data_pads.append(platform.request("sfp", 3))
if self.platform.hw_rev in ("v1.0", "v1.1"):
sfp_ctls = [platform.request("sfp_ctl", i) for i in range(3)]
self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0],
data_pads=drtio_data_pads,
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += disable_cdr_clk_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
if enable_sata:
sfp_channels = self.drtio_transceiver.channels[1:]
else:
sfp_channels = self.drtio_transceiver.channels
if self.platform.hw_rev in ("v1.0", "v1.1"):
self.comb += [
sfp_ctl.led.eq(channel.rx_ready)
for sfp_ctl, channel in zip(sfp_ctls, sfp_channels)
]
if self.platform.hw_rev == "v2.0":
self.comb += [
self.virtual_leds.get(i).eq(channel.rx_ready)
for i, channel in enumerate(sfp_channels)
]
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
drtioaux_csr_group = []
drtioaux_memory_group = []
drtiorep_csr_group = []
self.drtio_cri = []
for i in range(len(self.drtio_transceiver.channels)):
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
if i == 0:
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
core = cdr(
DRTIOSatellite(self.rtio_tsc,
self.drtio_transceiver.channels[i],
self.rx_synchronizer))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
else:
corerep_name = "drtiorep" + str(i - 1)
drtiorep_csr_group.append(corerep_name)
core = cdr(
DRTIORepeater(self.rtio_tsc,
self.drtio_transceiver.channels[i]))
setattr(self.submodules, corerep_name, core)
self.drtio_cri.append(core.cri)
self.csr_devices.append(corerep_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800 * i
self.add_wb_slave(memory_address, 0x800, coreaux.bus)
self.add_memory_region(memory_name,
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.add_csr_group("drtiorep", drtiorep_csr_group)
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
rtio_clk_period = 1e9 / rtio_clk_freq
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
if with_wrpll:
self.submodules.wrpll_sampler = DDMTDSamplerGTP(
self.drtio_transceiver,
platform.request("cdr_clk_clean_fabric"))
helper_clk_pads = platform.request("ddmtd_helper_clk")
self.submodules.wrpll = WRPLL(
helper_clk_pads=helper_clk_pads,
main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"),
ddmtd_inputs=self.wrpll_sampler)
self.csr_devices.append("wrpll")
# note: do not use self.wrpll.cd_helper.clk; otherwise, vivado craps out with:
# critical warning: create_clock attempting to set clock on an unknown port/pin
# command: "create_clock -period 7.920000 -waveform {0.000000 3.960000} -name
# helper_clk [get_xlnx_outside_genome_inst_pin 20 0]
platform.add_period_constraint(helper_clk_pads.p,
rtio_clk_period * 0.99)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
helper_clk_pads.p)
else:
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("cdr_clk") if platform.hw_rev
== "v2.0" else platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ref_clk=self.crg.clk125_div2,
ref_div2=True,
rtio_clk_freq=rtio_clk_freq)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gtp.txoutclk,
gtp.rxoutclk)
if with_wrpll:
platform.add_false_path_constraints(helper_clk_pads.p,
gtp.rxoutclk)
for gtp in self.drtio_transceiver.gtps[1:]:
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
gtp.rxoutclk)
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform)
def __init__(self, rtio_clk_freq=150e6, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
**kwargs)
add_identifier(self)
platform = self.platform
disable_si5324_ibuf = Signal(reset=1)
disable_si5324_ibuf.attr.add("no_retiming")
si5324_clkout = platform.request("si5324_clkout")
si5324_clkout_buf = Signal()
self.specials += Instance("IBUFDS_GTE2",
i_CEB=disable_si5324_ibuf,
i_I=si5324_clkout.p, i_IB=si5324_clkout.n,
o_O=si5324_clkout_buf)
qpll_drtio_settings = QPLLSettings(
refclksel=0b001,
fbdiv=4,
fbdiv_45=5,
refclk_div=1)
qpll = QPLL(si5324_clkout_buf, qpll_drtio_settings)
self.submodules += qpll
sfp_ctls = [platform.request("sfp_ctl", i) for i in range(3)]
self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctls]
self.submodules.drtio_transceiver = gtp_7series.GTP(
qpll_channel=qpll.channels[0],
data_pads=[platform.request("sfp", i) for i in range(3)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.sync += disable_si5324_ibuf.eq(
~self.drtio_transceiver.stable_clkin.storage)
self.comb += [sfp_ctl.led.eq(channel.rx_ready)
for sfp_ctl, channel in zip(sfp_ctls, self.drtio_transceiver.channels)]
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
drtioaux_csr_group = []
drtioaux_memory_group = []
drtiorep_csr_group = []
self.drtio_cri = []
for i in range(3):
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
if i == 0:
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
core = cdr(DRTIOSatellite(
self.rtio_tsc, self.drtio_transceiver.channels[i],
self.rx_synchronizer))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
else:
corerep_name = "drtiorep" + str(i-1)
drtiorep_csr_group.append(corerep_name)
core = cdr(DRTIORepeater(
self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, corerep_name, core)
self.drtio_cri.append(core.cri)
self.csr_devices.append(corerep_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i
self.add_wb_slave(memory_address, 0x800,
coreaux.bus)
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.add_csr_group("drtiorep", drtiorep_csr_group)
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ref_clk=self.crg.clk125_div2, ref_div2=True,
rtio_clk_freq=rtio_clk_freq)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
rtio_clk_period = 1e9/rtio_clk_freq
gtp = self.drtio_transceiver.gtps[0]
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk)
for gtp in self.drtio_transceiver.gtps[1:]:
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.rxoutclk)
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform)
def __init__(self, with_sawg, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128 * 1024,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
AMPSoC.__init__(self)
RTMCommon.__init__(self)
add_identifier(self, suffix=".without-sawg" if not with_sawg else "")
self.config["HMC830_REF"] = "100"
platform = self.platform
rtio_clk_freq = 150e6
self.submodules.si5324_rst_n = gpio.GPIOOut(
platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["SI5324_SAYMA_REF"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq / 1e6)
# ensure pins are properly biased and terminated
si5324_clkout = platform.request("cdr_clk_clean", 0)
self.specials += Instance("IBUFDS_GTE3",
i_CEB=0,
i_I=si5324_clkout.p,
i_IB=si5324_clkout.n,
attr={("DONT_TOUCH", "true")})
self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
self.csr_devices.append("ad9154_crg")
self.comb += [
platform.request("sfp_tx_disable", i).eq(0) for i in range(2)
]
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=self.ad9154_crg.refclk,
data_pads=[platform.request("sata")] +
[platform.request("sfp", i) for i in range(2)],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
drtio_csr_group = []
drtioaux_csr_group = []
drtioaux_memory_group = []
drtio_cri = []
for i in range(3):
core_name = "drtio" + str(i)
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtio_csr_group.append(core_name)
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
core = cdr(
DRTIOMaster(self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, core_name, core)
drtio_cri.append(core.cri)
self.csr_devices.append(core_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800 * i
self.add_wb_slave(memory_address, 0x800, coreaux.bus)
self.add_memory_region(memory_name,
memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtio", drtio_csr_group)
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
rtio_clk_period = 1e9 / rtio_clk_freq
gth = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth.txoutclk, rtio_clk_period / 2)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
self.drtio_transceiver.cd_rtio.clk.attr.add("keep")
platform.add_false_path_constraints(self.crg.cd_sys.clk,
self.drtio_transceiver.cd_rtio.clk,
gth.rxoutclk)
platform.add_false_path_constraints(self.crg.cd_sys.clk, gth.txoutclk)
for gth in self.drtio_transceiver.gths[1:]:
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(self.crg.cd_sys.clk,
gth.rxoutclk)
platform.add_false_path_constraints(
self.drtio_transceiver.cd_rtio.clk, gth.rxoutclk)
platform.add_false_path_constraints(self.ad9154_crg.cd_jesd.clk,
self.drtio_transceiver.cd_rtio.clk)
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 0)
self.comb += sma_io.direction.eq(1)
phy = ttl_serdes_ultrascale.Output(4, sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
sma_io = platform.request("sma_io", 1)
self.comb += sma_io.direction.eq(0)
phy = ttl_serdes_ultrascale.InOut(4, sma_io.level)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
if with_sawg:
cls = AD9154
else:
cls = AD9154NoSAWG
self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
self.csr_devices.append("ad9154_0")
self.csr_devices.append("ad9154_1")
self.config["HAS_AD9154"] = None
self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(
rtio.Channel.from_phy(phy)
for sawg in self.ad9154_0.sawgs + self.ad9154_1.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
self.csr_devices.append("rtio_core")
self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc)
self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")(rtio.DMA(
self.get_native_sdram_if()))
self.register_kernel_cpu_csrdevice("rtio")
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.rtio_core.cri] + drtio_cri,
enable_routing=True)
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
platform.request("dac_sysref"), self.rtio_tsc.coarse_ts)
self.csr_devices.append("sysref_sampler")
self.ad9154_0.jesd.core.register_jref(self.sysref_sampler.jref)
self.ad9154_1.jesd.core.register_jref(self.sysref_sampler.jref)
def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", gateware_identifier_str=None, with_sfp=False, *, with_wrpll, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
l2_size=128*1024,
integrated_sram_size=8192,
ethmac_nrxslots=4,
ethmac_ntxslots=4,
**kwargs)
add_identifier(self, suffix=identifier_suffix, gateware_identifier_str=gateware_identifier_str)
self.rtio_clk_freq = rtio_clk_freq
platform = self.platform
if with_wrpll:
clock_recout_pads = platform.request("ddmtd_rec_clk")
else:
clock_recout_pads = None
if with_sfp:
# Use SFP0 to connect to master (Kasli)
self.comb += platform.request("sfp_tx_disable", 0).eq(0)
drtio_uplink = platform.request("sfp", 0)
else:
drtio_uplink = platform.request("fat_pipe", 0)
self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("cdr_clk_clean"),
data_pads=[drtio_uplink, platform.request("rtm_amc_link")],
sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq,
clock_recout_pads=clock_recout_pads)
self.csr_devices.append("drtio_transceiver")
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
drtioaux_csr_group = []
drtioaux_memory_group = []
drtiorep_csr_group = []
self.drtio_cri = []
for i in range(len(self.drtio_transceiver.channels)):
coreaux_name = "drtioaux" + str(i)
memory_name = "drtioaux" + str(i) + "_mem"
drtioaux_csr_group.append(coreaux_name)
drtioaux_memory_group.append(memory_name)
cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
if i == 0:
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
core = cdr(DRTIOSatellite(
self.rtio_tsc, self.drtio_transceiver.channels[i],
self.rx_synchronizer))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
else:
corerep_name = "drtiorep" + str(i-1)
drtiorep_csr_group.append(corerep_name)
core = cdr(DRTIORepeater(
self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, corerep_name, core)
self.drtio_cri.append(core.cri)
self.csr_devices.append(corerep_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i
self.add_wb_slave(memory_address, 0x800,
coreaux.bus)
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None
self.config["HAS_DRTIO_ROUTING"] = None
self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.add_csr_group("drtiorep", drtiorep_csr_group)
rtio_clk_period = 1e9/rtio_clk_freq
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
if with_wrpll:
self.comb += [
platform.request("filtered_clk_sel").eq(0),
platform.request("ddmtd_main_dcxo_oe").eq(1),
platform.request("ddmtd_helper_dcxo_oe").eq(1)
]
self.submodules.wrpll_sampler = DDMTDSamplerExtFF(
platform.request("ddmtd_inputs"))
self.submodules.wrpll = WRPLL(
helper_clk_pads=platform.request("ddmtd_helper_clk"),
main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"),
ddmtd_inputs=self.wrpll_sampler)
self.csr_devices.append("wrpll")
platform.add_period_constraint(self.wrpll.cd_helper.clk, rtio_clk_period*0.99)
platform.add_false_path_constraints(self.crg.cd_sys.clk, self.wrpll.cd_helper.clk)
else:
self.comb += platform.request("filtered_clk_sel").eq(1)
self.submodules.siphaser = SiPhaser7Series(
si5324_clkin=platform.request("si5324_clkin"),
rx_synchronizer=self.rx_synchronizer,
ultrascale=True,
rtio_clk_freq=rtio_clk_freq)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
gth = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth.txoutclk, rtio_clk_period/2)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
gth.txoutclk, gth.rxoutclk)
def __init__(self, with_sawg, **kwargs):
SatelliteBase.__init__(
self,
150e6,
identifier_suffix=".without-sawg" if not with_sawg else "",
**kwargs)
platform = self.platform
self.submodules += RTMUARTForward(platform)
# RTM bitstream upload
slave_fpga_cfg = self.platform.request("rtm_fpga_cfg")
self.submodules.slave_fpga_cfg = gpio.GPIOTristate([
slave_fpga_cfg.cclk,
slave_fpga_cfg.din,
slave_fpga_cfg.done,
slave_fpga_cfg.init_b,
slave_fpga_cfg.program_b,
])
self.csr_devices.append("slave_fpga_cfg")
self.config["SLAVE_FPGA_GATEWARE"] = 0x200000
rtio_channels = []
for i in range(4):
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
mcx_io = platform.request("mcx_io", 0)
phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
self.comb += mcx_io.direction.eq(phy.oe)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
mcx_io = platform.request("mcx_io", 1)
phy = ttl_serdes_ultrascale.InOut(4, mcx_io.level)
self.comb += mcx_io.direction.eq(phy.oe)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.jesd_crg = jesd204_tools.UltrascaleCRG(
platform, use_rtio_clock=True)
if with_sawg:
cls = JDCG
else:
cls = JDCGNoSAWG
self.submodules.jdcg_0 = cls(platform, self.crg, self.jesd_crg, 0)
self.submodules.jdcg_1 = cls(platform, self.crg, self.jesd_crg, 1)
self.csr_devices.append("jesd_crg")
self.csr_devices.append("jdcg_0")
self.csr_devices.append("jdcg_1")
self.config["HAS_JDCG"] = None
self.add_csr_group("jdcg", ["jdcg_0", "jdcg_1"])
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(
rtio.Channel.from_phy(phy)
for sawg in self.jdcg_0.sawgs + self.jdcg_1.sawgs
for phy in sawg.phys)
self.add_rtio(rtio_channels)
self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
platform.request("amc_fpga_sysref", 0), self.rtio_tsc.coarse_ts)
self.csr_devices.append("sysref_sampler")
self.jdcg_0.jesd.core.register_jref(self.sysref_sampler.jref)
self.jdcg_1.jesd.core.register_jref(self.sysref_sampler.jref)
# DDMTD
# https://github.com/sinara-hw/Sayma_RTM/issues/68
sysref_pads = platform.request("amc_fpga_sysref", 1)
self.submodules.sysref_ddmtd = jesd204_tools.DDMTD(
sysref_pads, self.rtio_clk_freq)
self.csr_devices.append("sysref_ddmtd")