def driver(design):
for i in range(128):
design[i] = i * i << 30
yield from do_nothing(10)
for i in reversed(range(128)):
self.assertEqual(design[i], i * i << 30)
yield from do_nothing(10)
def driver(design):
design.source.write_packet(test_packet)
yield from do_nothing(20)
design.source.write_packet(test_packet)
yield from do_nothing(20)
self.assertEqual(test_packet, design.sink.read_packet())
yield from do_nothing(20)
self.assertEqual(test_packet, design.sink.read_packet())
def write_frame_to_stream(stream, frame, timeout=100, pause=False):
random = Random(0)
for y, line in enumerate(frame):
for x, px in enumerate(line):
if (random.random() < 0.3) and pause:
yield from do_nothing()
yield from write_to_stream(
stream,
payload=int(px),
timeout=timeout,
line_last=(x == (len(line) - 1)),
frame_last=(y == (len(frame) - 1)) & (x == (len(line) - 1)),
)
if (random.random() < 0.3) and pause:
yield from do_nothing()
def reader():
last_count = 0
for i in range(200):
last_count += (yield from read_from_stream(dut.output, extract="last"))
if i % 10 == 0:
yield from do_nothing()
self.assertEqual(last_count, 10)
def reader():
for i in range(100):
got = (yield from read_from_stream(dut.output, extract="payload"))
print(got)
self.assertEqual(got, i)
if i % 3 == 0:
yield from do_nothing()
def writer():
last_count_gold = 0
for i in range(50):
last = (i % 5 == 0)
last_count_gold += last
yield from write_to_stream(input, payload=0, last=(i % 5 == 0))
if i % 3 == 0:
yield from do_nothing()
self.assertEqual(last_count_gold, 10)
def testbench():
self.assertEqual(1, (yield stage1))
yield from do_nothing(10)
self.assertEqual(0, (yield stage1))
self.assertEqual(1, (yield stage2))
yield stage3_barrier.eq(1)
yield
yield
self.assertEqual(1, (yield end))
def testbench():
for i in range(10):
yield from write_to_stream(input, payload=i)
# async fifos need some time due to cdc
yield from do_nothing()
assert (yield fifo.r_level) == 10
for i in range(10):
assert (yield from read_from_stream(fifo.output)) == i, "read data doesnt match written data"
def reader():
last_count = 0
for i in range(100):
last = (yield from read_from_stream(dut.output, extract="last"))
last_count += last
if i % 10 == 1:
assert last
else:
assert not last
if i % 3 == 0:
yield from do_nothing()
self.assertEqual(last_count, 10)
def driver(design):
design.ila.arm()
yield from do_nothing(1000)
ila_trace = list(design.ila.get_values())
last_up = 150
last_down = 1000 - 150
assert len(ila_trace) == 100
for up, down in ila_trace:
assert up == last_up + 1, (up, last_up)
last_up = up
assert down == last_down - 1, (down, last_down)
last_down = down
def read_frame_from_stream(stream, timeout=100, pause=False):
random = Random(1)
frame = [[]]
while True:
if (random.random() < 0.3) and pause:
yield from do_nothing()
px, line_last, frame_last = (yield from read_from_stream(
stream,
timeout=timeout,
extract=("payload", "line_last", "frame_last")))
frame[-1].append(px)
if frame_last:
return frame
if line_last:
frame.append([])
def testbench():
yield from do_nothing(100000)
def write_process():
for i in range(2):
yield from write_frame_to_stream(input, image, pause=False)
yield Passive()
yield from do_nothing(100)
def writer():
for i in range(0, 100, 2):
yield from write_to_stream(input, payload=(((i + 1) << 8) | i))
if i % 7 == 0:
yield from do_nothing()
def writer():
for packet in packets:
yield from write_packet_to_stream(dut.hs_input,
packet,
timeout=400)
yield from do_nothing(400)
def testbench():
axi: AxiEndpoint = platform.axi_lite_master
yield axi.read_address.payload.eq(0x4000_0000)
yield axi.read_address.valid.eq(1)
yield from do_nothing()
