def test_convertLine(self):
from netConverter import verilog2vhdl
with self.subTest(key="Valid 1"):
line = "DFFSR Q_int1_reg ( .D(serial_in), .CLK(clk), .R(1), .S(n5), .Q(Q_int1) )"
expectedValue = "Q_int1_reg: DFFSR PORT MAP(D=>serial_in, CLK=>clk, R=>1, S=>n5, Q=>Q_int1);"
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
with self.subTest(key="Valid 2"):
line = " OAI22X1 U11 (.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25))"
expectedValue = "U11: OAI22X1 PORT MAP(A=>n32, B=>n5, C=>n3, D=>n6, Y=>n25);"
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
with self.subTest(key="Missing Instance"):
line = "BAD(.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25))"
expectedValue = "Error: Bad Line."
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
with self.subTest(key="Missing Component"):
line = ".A(n32),.B(n5),.C(n3),.D(n6),.Y(n25)"
expectedValue = "Error: Bad Line."
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
with self.subTest(key="Extra Parentheses"):
line = "First U22 ((.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25)))"
expectedValue = "Error: Bad Line."
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
with self.subTest(key="Invalid Names"):
line = "First $U22 ((.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25)))"
expectedValue = "Error: Bad Line."
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
with self.subTest(key="Extra Closing Parenthesis"):
line = "First U22 (.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25)))"
expectedValue = "Error: Bad Line."
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
with self.subTest(key="Bad Assignment"):
line = "First U22 (.A(n32),.B(n?),.C(n3),.D(n6),.Y(n25))"
expectedValue = "Error: Bad Line."
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
def test_convertLine(self):
from netConverter import verilog2vhdl
with self.subTest(key="Valid 1"):
line = "DFFSR Q_int1_reg ( .D(serial_in), .CLK(clk), .R(1), .S(n5), .Q(Q_int1) )"
expectedValue = "Q_int1_reg: DFFSR PORT MAP(D=>serial_in, CLK=>clk, R=>1, S=>n5, Q=>Q_int1);"
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
with self.subTest(key="Valid 2"):
line = " OAI22X1 U11 (.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25))"
expectedValue = "U11: OAI22X1 PORT MAP(A=>n32, B=>n5, C=>n3, D=>n6, Y=>n25);"
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
with self.subTest(key="Missing Instance"):
line = "BAD(.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25))"
expectedValue = "Error: Bad Line."
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
with self.subTest(key="Missing Component"):
line = ".A(n32),.B(n5),.C(n3),.D(n6),.Y(n25)"
expectedValue = "Error: Bad Line."
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
with self.subTest(key="Extra Parentheses"):
line = "First U22 ((.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25)))"
expectedValue = "Error: Bad Line."
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
with self.subTest(key="Invalid Names"):
line = "First $U22 ((.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25)))"
expectedValue = "Error: Bad Line."
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
with self.subTest(key="Extra Closing Parenthesis"):
line = "First U22 (.A(n32),.B(n5),.C(n3),.D(n6),.Y(n25)))"
expectedValue = "Error: Bad Line."
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)
with self.subTest(key="Bad Assignment"):
line = "First U22 (.A(n32),.B(n?),.C(n3),.D(n6),.Y(n25))"
expectedValue = "Error: Bad Line."
actualValue = verilog2vhdl(line)
self.assertEqual(expectedValue, actualValue)