def check_fixtures():
m = Module()
m.submodules.alu = alu = AluIdeal()
sim = Simulator(m)
num_checks = 0
def process():
nonlocal num_checks
for op in isa.AluOp:
yield alu.op.eq(op)
for a in blip.gen_fixtures(32, 24, 2):
yield alu.a.eq(a)
for b in blip.gen_fixtures(32, 12, 2):
if op == isa.AluOp.DIV and b == 0: continue
yield alu.b.eq(b)
yield Delay(1e-9)
ref_out, ref_ext, ref_flags = isa.emu.eval_alu(op, a, b)
out = yield alu.out
assert out == ref_out
num_checks += 1
sim.add_process(process)
sim.run()
blip.info(f"Checked {num_checks} inputs")
def test_one_rule(self):
calc = CalcLifeCell()
def process():
for i in range(512):
yield calc.input.eq(i)
yield Settle()
expected = life_cell(to_bit_list(i, width=9))
self.assertEqual((yield calc.output), expected)
sim = Simulator(calc)
#sim.add_clock(1) # 1Hz for simplicity of counting
sim.add_process(process)
sim.run()
def check(self, inputs):
c = CalcLifeWord()
sim = Simulator(c)
expected = life_row(*(to_bit_list(i, 18) for i in inputs))
def process():
for ci, val in zip(c.input, inputs):
yield ci.eq(val)
yield Settle()
actual = yield c.output
self.assertEqual(to_bit_list(actual), expected)
sim.add_process(process)
sim.run()
def simulate(self, m):
adder = self
dump_inputs(adder, m)
sim = Simulator(m)
def timings():
yield adder.x.eq(0x1)
yield adder.y.eq(0x2)
yield Delay(1 * muS)
sim.add_process(timings)
os.chdir("waves")
with sim.write_vcd("test.vcd", "test.gtkw", traces = adder.ports()):
sim.run()
fix_gtkw_win("test.gtkw")
def test_one_rule(self):
r = Rules1D(1, Rules1DConfig(30, InitStyle.SINGLE))
e = Calc1DCell(r)
def process():
expected = [0, 1, 1, 1, 1, 0, 0, 0]
for i, o in enumerate(expected):
yield e.input.eq(i)
yield Settle()
self.assertEqual(o, (yield e.output))
sim = Simulator(e)
#sim.add_clock(1) # 1Hz for simplicity of counting
sim.add_process(process)
sim.run()
def simulate():
from nmigen.back.pysim import Simulator, Delay, Settle
uart_baud = 9600
sim_clock_freq = uart_baud * 32
m = Module()
uart_tx = Signal()
uart_rx = Signal()
m.submodules.uart_high_speed = uart_high_speed = LowHighSpeedLoopback(
divisor=int(sim_clock_freq / uart_baud))
m.d.comb += uart_tx.eq(uart_high_speed.uart_tx)
m.d.comb += uart_high_speed.uart_rx.eq(uart_rx)
sim = Simulator(m)
sim.add_clock(1 / sim_clock_freq, domain="sync")
uart_tick = Delay(1 / uart_baud)
def process():
rx = uart_rx
yield rx.eq(1)
yield uart_tick
for i in range(4):
# start bit
yield rx.eq(0)
yield uart_tick
# 8 data bits
for i in range(1, 9):
yield rx.eq(i % 2 == 1)
yield uart_tick
# one stop bit
yield rx.eq(1)
yield uart_tick
# pause
for i in range(30):
yield uart_tick
sim.add_process(process) # or sim.add_sync_process(process), see below
# with sim.write_vcd("test.vcd", "test.gtkw", traces=[uart_tx, uart_rx]):
with sim.write_vcd("test.vcd", "test.gtkw",
traces=uart_high_speed.ports()):
sim.run()
def test_one_rule(self):
r = Rules1D(1, Rules1DConfig(30, InitStyle.SINGLE))
e = Calc1DWord(r)
def process():
# 18 bits in, 16 bits out
in_bits = [1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 1]
expected = [1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0]
def to_num(a):
return sum(b << i for i, b in enumerate(a))
yield e.input.eq(to_num(in_bits))
yield Settle()
self.assertEqual(to_num(expected), (yield e.output))
sim = Simulator(e)
#sim.add_clock(1) # 1Hz for simplicity of counting
sim.add_process(process)
sim.run()
def simulate(self, m: Module):
uut = self
dump_inputs(uut, m)
sim = Simulator(m)
def timings():
yield uut.a.eq(0x3)
yield Delay(1 * muS)
yield uut.a.eq(0x4)
yield Delay(1 * muS)
yield uut.a.eq(0x5)
yield Delay(1 * muS)
yield uut.a.eq(0x7)
yield Delay(1 * muS)
sim.add_process(timings)
os.chdir("waves")
with sim.write_vcd("test.vcd", "test.gtkw", traces=uut.ports()):
sim.run()
fix_gtkw_win("test.gtkw")
m.d.comb += adder.x.eq(x)
m.d.comb += adder.y.eq(y)
sim = Simulator(m)
def timings():
yield adder.x.eq(0x00)
yield adder.y.eq(0x00)
yield Delay(muS)
yield adder.x.eq(0xFF)
yield adder.y.eq(0xFF)
yield Delay(muS)
yield adder.x.eq(0x00)
yield Delay(muS)
sim.add_process(timings)
with sim.write_vcd("test.vcd", "test.gtkw", traces=[x, y] + adder.ports()):
sim.run()
fix_gtkw_win("test.gtkw")
#main_runner(parser, args, m, ports=[]+adder.ports())
#if __name__ == "__main__":
# parser = main_parser()
# args = parser.parse_args()
# m = Module()
# m.submodules.adder = adder = Adder()
#
# main_runner(parser, args, m, ports=[]+adder.ports())
def print_leds(leds):
line_top = [" ", " _ "]
line_mid = [" ", " │", " _ ", " _│", "│ ", "│ │", "│_ ", "│_│"]
line_bot = line_mid
a = leds & 1
fgb = ((leds >> 1) & 1) | ((leds >> 5) & 2) | ((leds >> 3) & 4)
edc = ((leds >> 2) & 1) | ((leds >> 2) & 2) | ((leds >> 2) & 4)
print(line_top[a])
print(line_mid[fgb])
print(line_bot[edc])
if __name__ == '__main__':
# seg = SevenSegment()
seg = SevenSegController()
sim = Simulator(seg)
def process():
for i in range(16):
yield seg.val.eq(i)
yield Delay()
result = yield seg.leds
print_leds(result)
sim.add_process(process)
with sim.write_vcd('output.vcd'):
sim.run()
from nmigen.build import *
import sys
if sys.argv[1] == "program":
platform = TinyFPGABxPlatform()
platform.add_resources([
Resource("glitch_trig", 0, Pins("A2", dir="o"),
Attrs(IO_STANDARD="SB_LVCMOS33"))
])
platform.add_resources([
Resource("target_reset", 0, Pins("A1", dir="o"),
Attrs(IO_STANDARD="SB_LVCMOS33"))
])
platform.build(Glitcher(), do_program=True)
else:
from nmigen import *
from nmigen.back.pysim import Simulator, Delay, Settle
glitcher = Glitcher()
sim = Simulator(glitcher)
sim.add_clock(1 / (16e6), domain="sync")
def process():
# To be defined
yield Delay(100e-3)
sim.add_process(process) # or sim.add_sync_process(process), see below
with sim.write_vcd("test.vcd", "test.gtkw", traces=glitcher.ports()):
sim.run()
