class BB(plat):
resources = plat.resources + [
# FTDI link back to pc
UARTResource(0,
rx="A8",
tx="B8",
attrs=Attrs(IO_STANDARD="SB_LVCMOS", PULLUP=1)),
*LEDResources("blinky",
pins="J1 H2 H9 D9",
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
# CTS on the board ued as reset
#Resource("status", 0, Pins("12", conn=("gpio", 0), dir="o")),
Resource("reset_pin", 0, Pins("18", conn=("gpio", 0), dir="i")),
Resource("pwm", 0, Pins("5", conn=("gpio", 0), dir="o")),
]
clock = "clk16"
flashmap = {
"device": "AT25SF081-SSHD-B",
"addrmap": {
"bootloader": (0x00000, 0x2FFFF),
"userimage": (0x30000, 0x4FFFF),
"userdata": (0x50000, 0xFBFFF),
"desc.tgz": (0xFC000, 0xFFFFF),
},
}
def freq(self):
clk = self.lookup(self.clock)
return clk.clock.frequency
def connect_mainboard(self):
self.add_connectors([
Connector(
"plugin",
"south",
gen_plugin_connector(lvds=[
"94 96", "95 93", "97 99", "87 89", "81 83", "73 75"
]),
conn=("expansion", 1),
),
Connector(
"plugin",
"north",
gen_plugin_connector(lvds=[
"68 70", "74 76", "82 84", "94 92", "93 91", "89 87"
]),
conn=("expansion", 0),
),
])
# TODO: add ext & shield connectors (but how?)
# best would be a way to (transpranetly) handle the routing fabrics
self.add_resources([
Resource("routing", 'east',
DiffPairs('29', '31', dir='io', conn=("expansion", 1)),
Attrs(IOSTANDARD="LVCMOS33")),
Resource("routing", 'west',
Pins("56", dir='o', conn=("expansion", 0)),
Attrs(IOSTANDARD="LVCMOS33")),
])
def assemble_platform():
platform = ICEBreakerPlatform()
i2s_conn = ('pmod', 0)
seg7_conn = ('pmod', 1)
i2s = Resource(
'i2s',
0,
Subsignal('mclk', Pins('1', conn=i2s_conn, dir='o')),
Subsignal('lrck', Pins('2', conn=i2s_conn, dir='o')),
Subsignal('sck', Pins('3', conn=i2s_conn, dir='o')),
Subsignal('sd', Pins('4', conn=i2s_conn, dir='o')),
)
seg7 = Resource(
'seg7', 0,
Subsignal('segs', Pins('1 2 3 4 7 8 9', conn=seg7_conn, dir='o')),
Subsignal('digit', Pins('10', conn=seg7_conn, dir='o')))
midi = UARTResource(1,
rx='39',
tx='40',
attrs=Attrs(IO_STANDARD='SB_LVCMOS'))
dbg = Resource(
'dbg',
0,
Subsignal('dbg', Pins('7 8 9 10', conn=i2s_conn, dir='o')),
)
platform.add_resources((i2s, seg7, midi, dbg))
return platform
class BB(TinyFPGABXPlatform):
resources = TinyFPGABXPlatform.resources + [
# FTDI link back to pc
Resource(
"serial",
0,
Subsignal("tx", Pins("19", conn=("gpio", 0), dir="o")),
Subsignal("rx", Pins("20", conn=("gpio", 0), dir="i")),
),
Resource("user_led", 1, Pins("12", conn=("gpio", 0), dir="o")),
Resource("user_led", 2, Pins("13", conn=("gpio", 0), dir="o")),
Resource("user_led", 3, Pins("14", conn=("gpio", 0), dir="o")),
Resource("user_led", 4, Pins("15", conn=("gpio", 0), dir="o")),
]
def blinky(self):
leds = []
for n in itertools.count():
try:
l = self.request("user_led", n)
print(l)
leds.append(l)
except ResourceError:
break
leds_cat = Cat(led.o for led in leds)
return leds_cat
class OvioCorePlatform(LatticeECP5Platform):
device = "LFE5U-85F"
package = "BG381"
speed = 8
resources = [
# This clock can only be an input to the PLL
Resource(
"pll_clk25",
0,
Pins("U16", dir="i"), # Input to LRC_GPLLOT
Clock(25e6),
Attrs(IO_TYPE="LVCMOS33")),
*LEDResources(pins="B17 C17 A17 B18",
invert=False,
attrs=Attrs(IO_TYPE="LVCMOS33")),
Resource(
"ft600",
0,
Subsignal("clk", Pins("J19", dir="i"), Clock(100e6),
Attrs(IO_TYPE="LVCMOS33")),
Subsignal(
"data",
Pins(
"C20 C18 D20 D19 E20 E19 F20 F19 G20 G19 H20 J17 J16 H16 H18 G18",
dir="io"), Attrs(IO_TYPE="LVCMOS33", DRIVE="16")),
Subsignal("be", Pins("H17 G16", dir="io"),
Attrs(IO_TYPE="LVCMOS33", DRIVE="16")),
Subsignal("read", PinsN("E18", dir="o"),
Attrs(IO_TYPE="LVCMOS33", DRIVE="16")),
Subsignal("write", PinsN("F17", dir="o"),
Attrs(IO_TYPE="LVCMOS33", DRIVE="16")),
Subsignal("oe", PinsN("E17", dir="o"),
Attrs(IO_TYPE="LVCMOS33", DRIVE="16")),
Subsignal("txe", PinsN("F16", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("rxf", PinsN("F18", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
Subsignal("reset", PinsN("D18", dir="o"),
Attrs(IO_TYPE="LVCMOS33")),
Subsignal("gpio0", Pins("D17", dir="i"),
Attrs(IO_TYPE="LVCMOS33")),
Subsignal("gpio1", Pins("E16", dir="i"),
Attrs(IO_TYPE="LVCMOS33")),
),
# The board has pseudo power pins, connect these with a constant `1`
Resource(
"pseudo_power",
0,
Subsignal("ft", Pins("J18", dir="o"),
Attrs(IO_TYPE="LVCMOS33", DRIVE="16")),
Subsignal("ddr", Pins("J5 M5 L3 N1 A3 D3 D2 H3", dir="o"),
Attrs(IO_TYPE="LVCMOS15")),
),
]
connectors = []
def toolchain_program(self, products, name):
raise NotImplementedError("Not implemented")
def LaserscannerResource(*args,
laser0,
laser1,
photodiode,
pwm,
enable,
number=None,
conn=None,
attrs=None):
""" Resource for laser scanner
The enable pin is currently activated via the Linux host
I/O signals:
O: laser0 -- laser channel 0
O: laser1 -- laser channel 1
I: photodiode -- photodiode used to measure position of laser
O: pwm -- polygon is rotated with pwm
O: en -- on low polygon motor is enabled (depends on type)
"""
io = []
io.append(
Subsignal("laser0", Pins(laser0, dir="o", conn=conn, assert_width=1)))
io.append(
Subsignal("laser1", Pins(laser1, dir="o", conn=conn, assert_width=1)))
io.append(
Subsignal("photodiode",
Pins(photodiode, dir="i", conn=conn, assert_width=1)))
io.append(Subsignal("pwm", Pins(pwm, dir="o", conn=conn, assert_width=1)))
io.append(
Subsignal("en", PinsN(enable, dir="o", conn=conn, assert_width=1)))
if attrs is not None:
io.append(attrs)
return Resource.family(*args, number, default_name="laserscanner", ios=io)
def hdmi_plugin_connect(platform, plugin_number):
if "plugin_{}:gpio0".format(plugin_number) in platform._conn_pins:
lowspeed_signals = [
# i2c to read edid data from the monitor
Subsignal("sda", Pins("lvds5_n", dir='io', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS25")),
Subsignal("scl", Pins("lvds5_p", dir='io', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS25")),
# hdmi plugin-module specific signals
Subsignal("output_enable", PinsN("gpio6", dir='o', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS33")),
Subsignal("equalizer", Pins("gpio1 gpio4", dir='o', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS33")),
Subsignal("dcc_enable", Pins("gpio5", dir='o', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS33")),
Subsignal("vcc_enable", Pins("gpio7", dir='o', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS33")),
Subsignal("ddet", Pins("gpio3", dir='o', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS33")),
Subsignal("ihp", Pins("gpio2", dir='i', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS33")),
]
else:
lowspeed_signals = []
platform.add_resources([
Resource("hdmi", plugin_number,
Subsignal("clock", PluginDiffPair(platform, plugin_number, pin=3, dir='o', serdes=True), Attrs(IOSTANDARD="LVDS_25")),
Subsignal("b", PluginDiffPair(platform, plugin_number, pin=2, dir='o', serdes=True), Attrs(IOSTANDARD="LVDS_25")),
Subsignal("g", PluginDiffPair(platform, plugin_number, pin=1, dir='o', serdes=True), Attrs(IOSTANDARD="LVDS_25")),
Subsignal("r", PluginDiffPair(platform, plugin_number, pin=0, dir='o', serdes=True), Attrs(IOSTANDARD="LVDS_25")),
*lowspeed_signals
)
])
def hdmi_plugin_connect(platform, plugin_number):
if "plugin_{}:gpio0".format(plugin_number) in platform._conn_pins:
lowspeed_signals = [
# i2c to read edid data from the monitor
Subsignal("sda", Pins("lvds5_n", dir='io', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS18")),
Subsignal("scl", Pins("lvds5_p", dir='io', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS18")),
# hdmi plugin-module specific signals
Subsignal("output_enable", PinsN("gpio6", dir='o', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS33")),
Subsignal("equalizer", Pins("gpio1 gpio4", dir='o', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS33")),
Subsignal("dcc_enable", Pins("gpio5", dir='o', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS33")),
Subsignal("vcc_enable", Pins("gpio7", dir='o', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS33")),
Subsignal("ddet", Pins("gpio3", dir='o', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS33")),
Subsignal("ihp", Pins("gpio2", dir='i', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="LVCMOS33")),
]
else:
lowspeed_signals = []
platform.add_resources([
Resource("hdmi", plugin_number,
Subsignal("clock", DiffPairs("lvds3_p", "lvds3_n", dir='o', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="DIFF_SSTL18_I")),
Subsignal("data_b", DiffPairs("lvds2_p", "lvds2_n", dir='o', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="DIFF_SSTL18_I")),
Subsignal("data_g", DiffPairs("lvds1_p", "lvds1_n", dir='o', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="DIFF_SSTL18_I")),
Subsignal("data_r", DiffPairs("lvds0_p", "lvds0_n", dir='o', conn=("plugin", plugin_number)), Attrs(IOSTANDARD="DIFF_SSTL18_I")),
*lowspeed_signals
)
])
def elaborate(self, platform):
platform.add_resources([
Resource("speaker", 0, Pins("1 2", dir='o', conn=("j", "1")),
Attrs(IO_TYPE="LVCMOS33"))
])
speaker = platform.request("speaker", 0)
led = platform.request("led", 0)
m = Module()
pll = m.submodules.pll = Pll(25e6, 20, 1, reset_less_input=True)
pll.output_domain("eth", 4)
os.environ["NMIGEN_nextpnr_opts"] = "--timing-allow-fail"
eth = m.submodules.eth = DomainRenamer("eth")(LiteEth(
platform.request(
"eth",
0,
dir={io.name: "-"
for io in platform.lookup("eth", 0).ios}),
platform.request("eth_clocks",
0,
dir={
io.name: "-"
for io in platform.lookup("eth_clocks", 0).ios
})))
pwm = m.submodules.pwm = Pwm(0)
m.d.comb += speaker.o[0].eq(pwm.output)
m.d.comb += speaker.o[1].eq(~pwm.output)
m.submodules.clocking_i2s = ClockDebug("eth")
m.submodules.clocking_sync = ClockDebug("sync", reset_less=True)
return m
class STEVE(TinyFPGABXPlatform):
resources = TinyFPGABXPlatform.resources + [
# FTDI link back to pc
Resource(
"serial",
0,
Subsignal("tx", Pins("19", conn=("gpio", 0), dir="o")),
Subsignal("rx", Pins("20", conn=("gpio", 0), dir="i")),
),
# Serial to AVR
Resource(
"serial",
1,
Subsignal("tx", Pins("14", conn=("gpio", 0), dir="o")),
Subsignal("rx", Pins("15", conn=("gpio", 0), dir="i")),
),
]
class FomuEVTPlatform(LatticeICE40Platform, LUNAPlatform):
""" Platform for the Fomu EVT platforms. """
default_clk = "clk48"
name = "Fomu EVT"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = FomuDomainGenerator
# We only have a direct connection on our USB lines, so use that for USB comms.
default_usb_connection = "usb"
device = "iCE40UP5K"
package = "SG48"
default_clk = "clk48"
resources = [
Resource("clk48", 0, Pins("44", dir="i"), Clock(48e6),
Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")),
Resource("led", 0, PinsN("41"), Attrs(IO_STANDARD="SB_LVCMOS")),
Resource(
"rgb_led",
0,
Subsignal("r", PinsN("40"), Attrs(IO_STANDARD="SB_LVCMOS")),
Subsignal("g", PinsN("39"), Attrs(IO_STANDARD="SB_LVCMOS")),
Subsignal("b", PinsN("41"), Attrs(IO_STANDARD="SB_LVCMOS")),
),
Resource(
"usb",
0,
Subsignal("d_p", Pins("34")),
Subsignal("d_n", Pins("37")),
Subsignal("pullup", Pins("35", dir="o")),
Attrs(IO_STANDARD="SB_LVCMOS"),
),
# PMOD
Resource("user_io", 0, PinsN("25"), Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_io", 1, PinsN("26"), Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_io", 2, PinsN("27"), Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("user_io", 3, PinsN("28"), Attrs(IO_STANDARD="SB_LVCMOS")),
]
connectors = []
def toolchain_program(self, products, name):
""" Program the FPGA of an Fomu EVT board. """
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.check_call(["fomu-flash", "-f", bitstream_filename])
def toolchain_flash(self, products, name="top"):
""" Flash the SPI flash of an Fomu EVT board. """
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.check_call(["fomu-flash", "-w", bitstream_filename])
class FomuHackerPlatform(LatticeICE40Platform, LUNAPlatform):
""" Base class for Fomu platforms. """
default_clk = "clk48"
name = "Fomu Hacker"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = FomuDomainGenerator
# We only have a direct connection on our USB lines, so use that for USB comms.
default_usb_connection = "usb"
device = "iCE40UP5K"
package = "UWG30"
default_clk = "clk48"
resources = [
Resource("clk48", 0, Pins("F5", dir="i"), Clock(48e6),
Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")),
Resource("led", 0, PinsN("C5"), Attrs(IO_STANDARD="SB_LVCMOS")),
Resource(
"rgb_led",
0,
Subsignal("r", PinsN("C5"), Attrs(IO_STANDARD="SB_LVCMOS")),
Subsignal("g", PinsN("B5"), Attrs(IO_STANDARD="SB_LVCMOS")),
Subsignal("b", PinsN("A5"), Attrs(IO_STANDARD="SB_LVCMOS")),
),
Resource(
"usb",
0,
Subsignal("d_p", Pins("A4")),
Subsignal("d_n", Pins("A2")),
Subsignal("pullup", Pins("D5", dir="o")),
Attrs(IO_STANDARD="SB_LVCMOS"),
),
]
connectors = []
def toolchain_program(self, products, name):
""" Program the flash of a FomuHacker board. """
# Use the DFU bootloader to program the ECP5 bitstream.
dfu_util = os.environ.get("DFU_UTIL", "dfu-util")
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.check_call(
[dfu_util, "-d", "1209:5bf0", "-D", bitstream_filename])
class SensorPlatform(LatticeICE40Platform):
device = "iCE40HX8K"
package = "BG121"
resources = [
Resource("clk25", 0, Pins("B6", dir="i"), Clock(25e6)),
Resource("user_led", 0, Pins("A10", dir="o")),
Resource("user_led", 1, Pins("A11", dir="o")),
Resource("user_sw", 0, Pins("L1", dir="i")),
Resource("user_sw", 1, Pins("L7", dir="i")),
Resource(
"adc",
0,
Subsignal("cs", Pins("L2", dir="o")),
Subsignal("dout", Pins("L3", dir="o")),
Subsignal("sclk", Pins("L4", dir="o")),
),
Resource(
"daqnet",
0,
Subsignal("led1", Pins("A3", dir="o")),
Subsignal("led2", Pins("A4", dir="o")),
Subsignal("txp", Pins("C2", dir="o")),
Subsignal("txn", Pins("C1", dir="o")),
Subsignal("rx", Pins("B2", dir="i")),
),
]
connectors = []
class ICE40HX8KBEVNPlatform(LatticeICE40Platform):
device = "iCE40HX8K"
package = "CT256"
# Resets should be on GBIN0/2/4/6. Clocks may be on any GBIN.
resources: List[Resource] = [
Resource(
"clk1",
0,
Pins("J3", dir="i"),
Clock(12e6),
Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS"),
), # GBIN6
Resource(
"clk2",
0,
Pins("G1", dir="i"),
Clock(12e6),
Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS"),
), # GBIN7
Resource("rst", 0, Pins("K9", dir="i"),
Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")), # GBIN4
*Bus(
default_name="addr",
pins="B1 B2 C1 C2 D1 D2 E2 F1 F2 G2 H1 H2 J2 J1 K3 K1",
dir="oe",
attrs=Attrs(IO_STANDARD="SB_LVCMOS"),
),
*Bus(
default_name="data",
pins="M3 L5 N3 P1 M4 P2 M5 R1",
dir="io",
attrs=Attrs(IO_STANDARD="SB_LVCMOS"),
),
*Bus(
default_name="led",
pins="C3 B3 C4 C5 A1 A2 B4 B5",
dir="o",
attrs=Attrs(IO_STANDARD="SB_LVCMOS"),
),
Resource("ba", 0, Pins("M1", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("rw", 0, Pins("E4", dir="oe"),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("n_irq", 0, Pins("L3", dir="i"),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("n_nmi", 0, Pins("L1", dir="i"),
Attrs(IO_STANDARD="SB_LVCMOS")),
]
default_clk = "clk1"
default_rst = "rst"
connectors: List[Connector] = []
def toolchain_program(self, products, name):
iceprog = os.environ.get("ICEPROG", "iceprog")
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.check_call([iceprog, "-S", bitstream_filename])
def __init__(self):
super().__init__()
self.add_resources([
Resource("sensor", 0,
Subsignal("shutter", Pins("25", dir='o', conn=("expansion", 0)), Attrs(IOSTANDARD="LVCMOS18")),
Subsignal("trigger", Pins("27", dir='o', conn=("expansion", 0)), Attrs(IOSTANDARD="LVCMOS18")),
Subsignal("reset", PinsN("31", dir='o', conn=("expansion", 0)), Attrs(IOSTANDARD="LVCMOS18")),
Subsignal("clk", Pins("33", dir='o', conn=("expansion", 0)), Attrs(IOSTANDARD="LVCMOS18")),
Subsignal("lvds_clk", DiffPairs("51", "53", dir='i', conn=("expansion", 0)), Attrs(IOSTANDARD="DIFF_SSTL18_I", IN_TERM="UNTUNED_SPLIT_50")),
Subsignal("lvds", DiffPairsN("41 45 55 65", "43 47 57 67", dir='i', conn=("expansion", 0)), Attrs(IOSTANDARD="DIFF_SSTL18_I", IN_TERM="UNTUNED_SPLIT_50")),
),
Resource("i2c", 0,
Subsignal("scl", Pins("35", dir='io', conn=("expansion", 0)), Attrs(IOSTANDARD="LVCMOS18")),
Subsignal("sda", Pins("37", dir='io', conn=("expansion", 0)), Attrs(IOSTANDARD="LVCMOS18")),
),
Resource("ws2812", 0, Pins("56", dir='o', conn=("expansion", 0)), Attrs(IOSTANDARD="LVCMOS18")),
Resource("encoder", 0,
Subsignal("quadrature", Pins("58 68", dir='i', conn=("expansion", 0))),
Subsignal("push", Pins("66", dir='i', conn=("expansion", 0)))
),
])
self.add_connectors([
Connector("plugin", "south",
gen_plugin_connector(
lvds=["21 23", "3 5", "9 11", "13 15", "4 6", "10 12"],
gpio=[71, 73, 63, 61, 64, 62, 75, 77],
i2c=[46, 48]),
conn=("expansion", 0),
),
Connector("plugin", "north",
gen_plugin_connector(
lvds=["14 16", "22 24", "26 28", "32 34", "36 38", "42 44"],
gpio=[76, 78, 80, 84, 86, 88, 90, 74],
i2c=[52, 54]),
conn=("expansion", 0),
),
Connector("pmod", "north", "110 106 100 96 - - 108 104 98 94 - -", conn=("expansion", 0), ),
Connector("pmod", "south", "97 95 89 85 - - 99 93 87 83 - -", conn=("expansion", 0), ),
Connector("pmod", "east", "103 105 107 109 - -", conn=("expansion", 0), ),
])
def ULPIResource(name, data_sites, clk_site, dir_site, nxt_site, stp_site,
reset_site):
""" Generates a set of resources for a ULPI-connected USB PHY. """
return Resource(name, 0, Subsignal("data", Pins(data_sites, dir="io")),
Subsignal("clk", Pins(clk_site, dir="o")),
Subsignal("dir", Pins(dir_site, dir="i")),
Subsignal("nxt", Pins(nxt_site, dir="i")),
Subsignal("stp", Pins(stp_site, dir="o")),
Subsignal("rst", PinsN(reset_site, dir="o")),
Attrs(IO_TYPE="LVCMOS33", SLEWRATE="FAST"))
class TinyFPGABxPlatform(LatticeICE40Platform, LUNAPlatform):
device = "iCE40LP8K"
package = "CM81"
default_clk = "clk16"
name = "TinyFPGA Bx"
# Provide the type that'll be used to create our clock domains.
clock_domain_generator = TinyFPGABxDomainGenerator
# We only have a direct connection on our USB lines, so use that for USB comms.
default_usb_connection = "usb"
resources = [
Resource("clk16", 0, Pins("B2", dir="i"), Clock(16e6),
Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("led", 0, Pins("B3"), Attrs(IO_STANDARD="SB_LVCMOS")),
Resource("usb", 0, Subsignal("d_p", Pins("B4", dir="io")),
Subsignal("d_n", Pins("A4", dir="io")),
Subsignal("pullup", Pins("A3", dir="o")),
Attrs(IO_STANDARD="SB_LVCMOS")),
]
connectors = [
Connector(
"gpio",
0,
# Left side of the board
# 1 2 3 4 5 6 7 8 9 10 11 12 13
" A2 A1 B1 C2 C1 D2 D1 E2 E1 G2 H1 J1 H2 "
# Right side of the board
# 14 15 16 17 18 19 20 21 22 23 24
" H9 D9 D8 C9 A9 B8 A8 B7 A7 B6 A6 "
# Bottom of the board
# 25 26 27 28 29 30 31
"G1 J3 J4 G9 J9 E8 J2"),
]
def toolchain_program(self, products, name):
tinyprog = os.environ.get("TINYPROG", "tinyprog")
with products.extract("{}.bin".format(name)) as bitstream_filename:
subprocess.check_call([tinyprog, "-p", bitstream_filename])
class Ulx3sPlatform(ULX3S_85F_Platform):
resources: List[Resource] = [
Resource("clk25", 0, Pins("G2", dir="i"), Clock(25e6),
Attrs(IO_TYPE="LVCMOS33")),
Resource("rst", 0, Pins("D6", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
*Bus(
default_name="addr",
pins="B11 C11 A10 A11 A9 B10 B9 C10 A7 A8 C8 B8 C6 C7 A6 B6",
dir="oe",
attrs=Attrs(IO_TYPE="LVCMOS33"),
),
*Bus(
default_name="data",
pins="A4 A5 A2 B1 C4 B4 F4 E3",
dir="io",
attrs=Attrs(IO_TYPE="LVCMOS33"),
),
*Bus(
default_name="led",
pins="H3 E1 E2 D1 D2 C1 C2 B2",
dir="o",
attrs=Attrs(IO_TYPE="LVCMOS33"),
),
Resource("ba", 0, Pins("G3", dir="o"), Attrs(IO_TYPE="LVCMOS33")),
Resource("rw", 0, Pins("F3", dir="oe"), Attrs(IO_TYPE="LVCMOS33")),
Resource("n_irq", 0, Pins("H4", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
Resource("n_nmi", 0, Pins("G5", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
]
default_rst = "rst"
def extend(self):
print("EXTEND")
# FTDI link back to pc
self.add_resources([
Resource(
"serial",
0,
Subsignal("tx", Pins("B8", dir="o")),
Subsignal("rx", Pins("A8", dir="i")),
),
Resource(
"serial",
1,
Subsignal("tx", Pins("J1", dir="o")),
Subsignal("rx", Pins("H2", dir="i")),
),
Resource("user_led",
1,
Pins("J1", dir="o"),
extras=["IO_STANDARD=SB_LVCMOS33"]),
Resource("user_led",
2,
Pins("H1", dir="o"),
extras=["IO_STANDARD=SB_LVCMOS33"]),
Resource("user_led",
3,
Pins("H9", dir="o"),
extras=["IO_STANDARD=SB_LVCMOS33"]),
Resource("user_led",
4,
Pins("D9", dir="o"),
extras=["IO_STANDARD=SB_LVCMOS33"]),
])
def assemble_platform():
platform = ICEBreakerPlatform()
seg7_conn = ('pmod', 1)
seg7 = Resource(
'seg7', 0,
Subsignal('segs', Pins('1 2 3 4 7 8 9', conn=seg7_conn, dir='o')),
Subsignal('digit', Pins('10', conn=seg7_conn, dir='o')))
midi = UARTResource(1,
rx='39',
tx='40',
attrs=Attrs(IO_STANDARD='SB_LVCMOS'))
platform.add_resources((seg7, midi))
return platform
def __init__(self, device_name: str, variant: str):
super().__init__()
self.toolchain = "" # don't really need this.
self.device = ATF15xxDevice(device_name, variant)
ionum = 0
for pin, mc in self.device.pin_to_mc.items():
if mc in self.device.mc_to_jtag:
continue
self.device.add_gpiobuf(ionum, mc)
self.add_resources([Resource("$gpiobuf", ionum, Pins(str(pin)))])
ionum += 1
print(f"Total available pins: {ionum}")
def __init__(self):
lvcmos = self.lvcmos
# Create resources for each LED header
for jidx, pins in enumerate(self.leds):
self.resources += [
Resource("led_rgb", jidx,
Subsignal("r0", Pins(pins[0], dir="o"), lvcmos),
Subsignal("g0", Pins(pins[1], dir="o"), lvcmos),
Subsignal("b0", Pins(pins[2], dir="o"), lvcmos),
Subsignal("r1", Pins(pins[3], dir="o"), lvcmos),
Subsignal("g1", Pins(pins[4], dir="o"), lvcmos),
Subsignal("b1", Pins(pins[5], dir="o"), lvcmos))
]
# Create resources for each unknown pin
for pin in self.outputs:
self.resources += [Resource(pin, 0, Pins(pin, dir="o"), lvcmos)]
for pin in self.inputs:
self.resources += [Resource(pin, 0, Pins(pin, dir="i"), lvcmos)]
for pin in self.bidis:
self.resources += [Resource(pin, 0, Pins(pin, dir="io"), lvcmos)]
super().__init__()
def generate(top):
from nmigen_boards.icestick import ICEStickPlatform
platform = ICEStickPlatform()
platform.add_resources([
Resource(
'sound_out',
0,
Subsignal('pin', Pins('3', conn=('j', 1), dir='o')),
)
])
platform.build(top, do_program=args.program or args.interactive)
class TinyBoneless(TinyFPGABXPlatform):
resources = TinyFPGABXPlatform.resources + [
# FTDI link for now
Resource(
"uart",
0,
Subsignal("tx", Pins("19", conn=("gpio", 0), dir="o")),
Subsignal("rx", Pins("20", conn=("gpio", 0), dir="i")),
Subsignal("dtr", Pins("21", conn=("gpio", 0), dir="i")),
),
*LEDResources("blinky",
pins="J1 H2 H9 D9",
attrs=Attrs(IO_STANDARD="SB_LVCMOS")),
]
user_flash = (0x50000, 0xFBFFF)
class PaintController(TinyFPGABXPlatform):
resources = TinyFPGABXPlatform.resources + [
Resource(
"spi",
0,
Subsignal("clk", Pins("4", conn=("gpio", 0), dir="i")),
Subsignal("ss", Pins("5", conn=("gpio", 0), dir="i")),
Subsignal("miso", Pins("6", conn=("gpio", 0), dir="o")),
Subsignal("mosi", Pins("7", conn=("gpio", 0), dir="i")),
),
Resource(
"dispenser",
0,
Subsignal("stepper", Pins("8", conn=("gpio", 0), dir="o")),
Subsignal("limit_top", Pins("9", conn=("gpio", 0), dir="i")),
Subsignal("limit_bottom", Pins("10", conn=("gpio", 0), dir="i")),
),
Resource(
"dispenser",
1,
Subsignal("stepper", Pins("11", conn=("gpio", 0), dir="o")),
Subsignal("limit_top", Pins("12", conn=("gpio", 0), dir="i")),
Subsignal("limit_bottom", Pins("13", conn=("gpio", 0), dir="i")),
),
Resource(
"dispenser",
2,
Subsignal("stepper", Pins("14", conn=("gpio", 0), dir="o")),
Subsignal("limit_top", Pins("15", conn=("gpio", 0), dir="i")),
Subsignal("limit_bottom", Pins("16", conn=("gpio", 0), dir="i")),
),
Resource(
"dispenser",
3,
Subsignal("stepper", Pins("17", conn=("gpio", 0), dir="o")),
Subsignal("limit_top", Pins("18", conn=("gpio", 0), dir="i")),
Subsignal("limit_bottom", Pins("19", conn=("gpio", 0), dir="i")),
),
Resource(
"dispenser",
4,
Subsignal("stepper", Pins("20", conn=("gpio", 0), dir="o")),
Subsignal("limit_top", Pins("21", conn=("gpio", 0), dir="i")),
Subsignal("limit_bottom", Pins("22", conn=("gpio", 0), dir="i")),
),
Resource(
"motor_enable",
0,
Pins("23", conn=("gpio", 0), dir="o"),
)
]
def ULPIResource(name,
data_sites,
clk_site,
dir_site,
nxt_site,
stp_site,
reset_site,
extras=()):
""" Generates a set of resources for a ULPI-connected USB PHY. """
return Resource(
name, 0, Subsignal("data", Pins(data_sites, dir="io")),
Subsignal("clk", Pins(clk_site, dir="i"), Attrs(PULLDOWN="TRUE"),
Clock(60e6)), Subsignal("dir", Pins(dir_site, dir="i")),
Subsignal("nxt", Pins(nxt_site, dir="i")),
Subsignal("stp", Pins(stp_site, dir="o")),
Subsignal("rst", PinsN(reset_site, dir="o")), Attrs(SLEW="FAST"))
def Bus(*args, pins, invert=False, conn=None, attrs=None, default_name, dir):
"""Adds a bus resource. Add to resources using *Bus(...)."""
assert isinstance(pins, (str, list, dict))
if isinstance(pins, str):
pins = pins.split()
if isinstance(pins, list):
pins = dict(enumerate(pins))
resources = []
for number, pin in pins.items():
ios = [Pins(pin, dir=dir, invert=invert, conn=conn)]
if attrs is not None:
ios.append(attrs)
resources.append(
Resource.family(*args, number, default_name=default_name, ios=ios))
return resources
def elaborate(self, platform):
m = Module()
resources = [
Resource("wishbone", 0,
Subsignal("adr", Pins("ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7"
" ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15"
" ADDR16 ADDR17 ADDR18 ADDR19 ADDR20 ADDR21 ADDR22 ADDR23"
" ADDR24 ADDR25 ADDR26 ADDR27 ADDR28 ADDR29 ADDR30 ADDR31", dir="i")),
Subsignal("dat_r", Pins("DATR0 DATR1 DATR2 DATR3 DATR4 DATR5 DATR6 DATR7"
" DATR8 DATR9 DATR10 DATR11 DATR12 DATR13 DATR14 DATR15"
" DATR16 DATR17 DATR18 DATR19 DATR20 DATR21 DATR22 DATR23"
" DATR24 DATR25 DATR26 DATR27 DATR28 DATR29 DATR30 DATR31", dir="o")),
Subsignal("dat_w", Pins("DATW0 DATW1 DATW2 DATW3 DATW4 DATW5 DATW6 DATW7"
" DATW8 DATW9 DATW10 DATW11 DATW12 DATW13 DATW14 DATW15"
" DATW16 DATW17 DATW18 DATW19 DATW20 DATW21 DATW22 DATW23"
" DATW24 DATW25 DATW26 DATW27 DATW28 DATW29 DATW30 DATW31", dir="i")),
Subsignal("cyc", Pins("CYC", dir="i")),
Subsignal("stb", Pins("STB", dir="i")),
Subsignal("sel", Pins("SEL0 SEL1 SEL2 SEL3", dir="i")),
Subsignal("ack", Pins("ACK", dir="o")),
Subsignal("we", Pins("WE", dir="i"))),
]
platform.add_resources(resources)
m.submodules.sysclk = self.crg
m.submodules.decoder = self._decoder
m.submodules.ddrphy = self.ddrphy
m.submodules.dramcore = self.dramcore
m.submodules.drambone = self.drambone
ext_bus = platform.request("wishbone", 0)
m.d.comb += [
self._decoder.bus.adr.eq(ext_bus.adr.i),
self._decoder.bus.dat_w.eq(ext_bus.dat_w.i),
ext_bus.dat_r.o.eq(self._decoder.bus.dat_r),
self._decoder.bus.cyc.eq(ext_bus.cyc.i),
self._decoder.bus.stb.eq(ext_bus.stb.i),
self._decoder.bus.sel.eq(ext_bus.sel.i),
ext_bus.ack.o.eq(self._decoder.bus.ack),
self._decoder.bus.we.eq(ext_bus.we.i),
]
return m
def load():
from boards.qmtech_wukong import Platform as wukong
wukong.resources += [
Resource("clk_n", 0, Pins("AB13", dir="i")),
Resource("clk_p", 0, Pins("AA13", dir="i")),
Resource("tx_n", 0, Pins("AD10")),
Resource("tx_p", 0, Pins("AC10")),
Resource("rx_n", 0, Pins("AD12")),
Resource("rx_p", 0, Pins("AC12"))
]
return (wukong, XilinxGTPSerdes)
def ULPIResource(name,
data_sites,
clk_site,
dir_site,
nxt_site,
stp_site,
reset_site,
extras=(),
attrs=None):
""" Generates a set of resources for a ULPI-connected USB PHY. """
attrs = Attrs() if attrs is None else attrs
return Resource(name, 0, Subsignal("data", Pins(data_sites, dir="io")),
Subsignal("clk", Pins(clk_site, dir="i"), Clock(60e6)),
Subsignal("dir", Pins(dir_site, dir="i")),
Subsignal("nxt", Pins(nxt_site, dir="i")),
Subsignal("stp", Pins(stp_site, dir="o")),
Subsignal("rst", Pins(reset_site, dir="o")), attrs)