def initialize_slave_lists(self):
        bus_type = self.controller.get_bus()
        paths = utils.get_local_verilog_paths()
        slave_list = utils.get_slave_list(bus_type, paths)

        peripheral_dict = {}
        memory_dict = {}

        for slave in slave_list:
            tags = vutils.get_module_tags(  filename = slave,
                                            keywords=["SDB_ABI_VERSION_MAJOR", "SDB_NAME"],
                                            bus = self.controller.get_bus(),
                                            user_paths = paths)
            #print "Tags: %s" % str(tags)
            #core_id = int(tags["keywords"]["SDB_NAME"])
            device_abi_major = int(tags["keywords"]["SDB_ABI_VERSION_MAJOR"], 0)
            memory_abi_major = device_manager.get_device_id_from_name("memory")
            if device_abi_major == memory_abi_major:
                memory_dict[tags["module"]] = tags
            else:
                peripheral_dict[tags["module"]] = tags

        self.project_actions.setup_peripheral_bus_list.emit(peripheral_dict)
        self.project_actions.setup_memory_bus_list.emit(memory_dict)
        #self.project_view.get_designer_scene().view.fit_in_view()
        self.project_actions.update_project_name.connect(self.actions.update_project_name)
        self.project_actions.add_constraint_file.connect(self.add_constraint)
        self.project_actions.remove_constraint_file.connect(self.remove_constraint)
        self.project_actions.add_default_board_constraint.connect(self.add_default_board_constraint)
        self.project_actions.remove_default_board_constraint.connect(self.remove_default_board_constraint)
        self.project_actions.commit_slave_parameters.connect(self.commit_slave_parameters)
        self.project_actions.commit_slave_integration_list.connect(self.commit_slave_integration_list)
    def test_get_slave_list_usr_loc(self):
        loc = os.path.join(os.path.dirname(__file__), os.path.pardir, "fake")

        slave_list = utils.get_slave_list(user_paths=[loc], debug=self.dbg)
        #print "slave list: %s" % str(slave_list)
        p = False
        for slave in slave_list:
            if "test_wb_slave.v" in slave:
                p = True
        self.assertTrue(p)
 def test_get_slave_list(self):
     #print "slave path: %s" % SLAVE_PATH
     slave_list = utils.get_slave_list(  bus = "wishbone",
                                         user_paths = [SLAVE_PATH],
                                         debug = False)
     #print "slave list: %s" % str(slave_list)
     p = False
     for slave in slave_list:
         if "wb_gpio.v" in slave:
             p = True
     self.assertTrue(p)
 def test_get_slave_list(self):
     #print "slave path: %s" % SLAVE_PATH
     slave_list = utils.get_slave_list(bus="wishbone",
                                       user_paths=[SLAVE_PATH],
                                       debug=False)
     #print "slave list: %s" % str(slave_list)
     p = False
     for slave in slave_list:
         if "wb_gpio.v" in slave:
             p = True
     self.assertTrue(p)
    def test_get_slave_list_usr_loc(self):
        loc = os.path.join(os.path.dirname(__file__),
                           os.path.pardir,
                           "fake")

        slave_list = utils.get_slave_list(user_paths = [loc], debug = self.dbg)
        #print "slave list: %s" % str(slave_list)
        p = False
        for slave in slave_list:
            if "test_wb_slave.v" in slave:
                p = True
        self.assertTrue(p)