def programOKBoard(self): prog = self.xem.ConfigureFPGA(self.okDeviceFile) if prog: raise ("Not able to program FPGA") pll = ok.PLL22150() self.xem.GetEepromPLL22150Configuration(pll) pll.SetDiv1(pll.DivSrc_VCO, 4) self.xem.SetPLL22150Configuration(pll)
def programOKBoard(self): print 'Programming FPGA' prog = self.xem.ConfigureFPGA('photon.bit') if prog: raise ("Not able to program FPGA") pll = ok.PLL22150() self.xem.GetEepromPLL22150Configuration(pll) pll.SetDiv1(pll.DivSrc_VCO, 4) self.xem.SetPLL22150Configuration(pll)
def programOKBoard(self): prog = self.xem.ConfigureFPGA(self.okDeviceFile) if prog: raise Exception("Not able to program FPGA") # this configure the PLL for the XEM6010. Probably need to change for other OK module pll = ok.PLL22150() self.xem.GetEepromPLL22150Configuration(pll) pll.SetDiv1(pll.DivSrc_VCO, 4) self.xem.SetPLL22150Configuration(pll)
def set_frequency(self, vco, src): #assert src in [2, 3, 5] PLL = ok.PLL22150() self.xem.GetPLL22150Configuration(PLL) PLL.SetVCOParameters(vco, 48) PLL.SetOutputSource(0, src) PLL.SetOutputEnable(0, 1) self.xem.SetPLL22150Configuration(PLL) self.PLL = PLL
def __init__(self): try: self.xem = ok.FrontPanel() self.xem.OpenBySerial(DEVICESERIAL) print "Found device called %s" % (self.xem.GetDeviceID()) bitfile = './XEM6001_275bins.bit' DEVICE = 'XEM6001' print "Loading PLL config" pll = ok.PLL22150() self.xem.GetEepromPLL22150Configuration(pll) print "FREQUENCY=%d" % (FREQUENCY) pll.SetVCOParameters(int(FREQUENCY), 48) pll.SetDiv1(pll.DivSrc_VCO, 4) pll.SetDiv2(pll.DivSrc_VCO, 4) pll.SetOutputSource(0, pll.ClkSrc_Div1By2) pll.SetOutputSource(1, pll.ClkSrc_Div1By2) for i in range(6): pll.SetOutputEnable(i, (i == 0)) print "Ref is at %gMHz, PLL is at %gMHz" % (pll.GetReference(), pll.GetVCOFrequency()) for i in range(6): if (pll.IsOutputEnabled(i)): print "Clock %d at %gMHz" % (i, pll.GetOutputFrequency(i)) print "Programming PLL" self.xem.SetPLL22150Configuration(pll) print "Programming FPGA with:", bitfile if (self.xem.ConfigureFPGA(bitfile) < 0): print "Programming failed. Quitting..." sys.exit() except Exception as e: print "initialization error" + str(e) sys.exit(1) self.internal_state = {} self.internal_state["Count"] = 0 self.internal_state["IntTime"] = 250 # in ms self.internal_state["SampFreq"] = 300.0 # in MHz self.internal_state["MMAmp"] = 0.0 self.internal_state["MMPhase"] = 0.0 self.internal_state["Data"] = 0 self.internal_state["DataState"] = False self.internal_state["Background"] = True self.internal_state["OverCount"] = False self.used_bins = NBINS self.clk_div = 1.0 self.background_count = 0. # initialization self.SampFreq(30.0) self.IntTime(250)
def programOKBoard(self, xem): print 'Programming FPGA' basepath = os.environ.get('LABRADPATH', None) if not basepath: raise Exception('Please set your LABRADPATH environment variable') path = os.path.join(basepath, 'lattice/okfpgaservers/led.bit') prog = xem.ConfigureFPGA(path) if prog: raise ("Not able to program FPGA") pll = ok.PLL22150() xem.GetEepromPLL22150Configuration(pll) pll.SetDiv1(pll.DivSrc_VCO, 4) xem.SetPLL22150Configuration(pll)
def __init__(self, serial=''): xem = ok.FrontPanel() if (xem.OpenBySerial(serial) != 0): raise RuntimeError, 'Failed to open USB connection.' PLL = ok.PLL22150() xem.GetPLL22150Configuration(PLL) PLL.SetVCOParameters(333,48) #set VCO to 333MHz PLL.SetOutputSource(0,5) #clk0@166MHz PLL.SetDiv1(1,6) #needs to be set for DIV1=3 PLL.SetOutputEnable(0,1) logging.getLogger().info('Pulser base clock input (clk2xin, stage two): '+str(PLL.GetOutputFrequency(0))) xem.SetPLL22150Configuration(PLL) if (xem.ConfigureFPGA(bitfile) != 0): raise RuntimeError, 'Failed to upload bit file to fpga.' self.xem = xem
def __init__(self): try: maxLoadAttempts = 10 #Allow for repeated loading to fix a bug I saw once loadedBitfile = 1 #Bitfile not yet loaded self.xem = ok.FrontPanel() devices = self.xem.GetDeviceCount() print "Found %d attached FPGAs" % (devices) if (devices > 0): if (self.xem.OpenBySerial(DEVICESERIAL) == 0): print "Opened an FPGA known as %s" % ( self.xem.GetDeviceID()) print "Now loading PLL configuration..." pll = ok.PLL22150() self.xem.GetEepromPLL22150Configuration(pll) pll.SetVCOParameters( int(SYSTEMCLOCK), 24) # NOTE - make sure this gives the right frequency pll.SetDiv1(pll.DivSrc_VCO, 4) pll.SetOutputSource(0, pll.ClkSrc_Div1By2) pll.SetOutputSource(1, pll.ClkSrc_Div1By2) pll.SetOutputEnable(1, True) print "System clock to be set @ %gMHz" % ( pll.GetOutputFrequency(0)) print "SPI clock to be set @ %gMHz" % ( pll.GetOutputFrequency(1)) self.xem.SetPLL22150Configuration(pll) print "Loading the bitfile..." attempts = 0 while (attempts <= maxLoadAttempts): loadedBitfile = self.xem.ConfigureFPGA(BITFILE) if (loadedBitfile == 0): print "Bitfile loaded!" break attempts += 1 except Exception as e: print "Initialization error" + str(e) sys.exit(1) try: self.internal_state = {} for i in range(8): self.internal_state["QuADDaughterType_%i" % i] = "DAC" self.internal_state["QuADDaughterOutputMode_%i" % i] = "Single" self.internal_state["QuADDaughterRangeMode_%i" % i] = "Positive" self.internal_state["QuADDaughterSource_%i" % i] = "ADC0" self.internal_state["QuADDaughterPositiveRail_%i" % i] = 5.0 self.internal_state["QuADDaughterNegativeRail_%i" % i] = 0.0 self.internal_state["QuADDaughterVoltage_%i" % i] = 0 for i in range(5): self.internal_state["QuADFilterType_%i" % i] = "P" self.internal_state["QuADFilterSource_%i" % i] = "ADC0" self.internal_state["QuADFilterCutoff_%i" % i] = 20000.0 self.internal_state["QuADFilterGain_%i" % i] = 1.0 self.internal_state["QuADFilterOffset_%i" % i] = 0.0 self.internal_state["QuADRampAmplitude"] = 1.0 self.internal_state["QuADRampFrequency"] = 100.0 self.internal_state["QuADRampStatus"] = "Off" #Populate functions try: for i, key in enumerate(self.internal_state): if 'QuADDaughter' in key: FuncID, ind = (key.split('QuADDaughter')[1]).split('_') FuncID = 'self.' + FuncID setattr(self, key, lambda x, self=self, ind=ind, FuncID=FuncID: eval(FuncID)(ind, x)) elif 'QuADFilter' in key: FuncID, ind = (key.split('QuAD')[1]).split('_') FuncID = 'self.' + FuncID setattr(self, key, lambda x, self=self, ind=ind, FuncID=FuncID: eval(FuncID)(ind, x)) if DEBUG: print FuncID, ind except Exception as e: print 'ERROR in populating functions: \n\n', e # Now run initialization methods to reach a common start state print "Engaging default state..." # All daughters initialize as DACs self.setRegister(0x0000, 0x00) # All daughters initialize into non_feedback mode self.setRegister(0x0002, 0x00) # Set all DACs into positive mode and write 0 V to each for i in range(8): self.setRegister(0x0080 + i, SOURCE_LIST["ADC0"]) self.setRegister(0x0010 + 2 * i, 0x0002) self.setRegister(0x0011 + 2 * i, 0x0020) self.xem.ActivateTriggerIn(0x40, i) # In positive mode, the code to set zero volts is 0x180000 self.setRegister(0x0010 + 2 * i, 0x0000) self.setRegister(0x0011 + 2 * i, 0x0018) self.xem.ActivateTriggerIn(0x40, i) print "Writing 0.0 to DAC at position " + str(i) # Set all of the feedback modes to positive only self.setRegister(0x0004, 0x00) #Set the rail voltages for each DAC for i in range(8): self.PositiveRail( i, self.internal_state["QuADDaughterPositiveRail_%i" % i]) self.NegativeRail( i, self.internal_state["QuADDaughterNegativeRail_%i" % i]) # Update each of the filters to the internal state configuration # NOTE - need to replace configureFilter() here to get rid of the extra function for i in range(5): self.configureFilter(i, self.internal_state["QuADFilterType_%i"%i], \ self.internal_state["QuADFilterSource_%i"%i], self.internal_state["QuADFilterCutoff_%i"%i], \ self.internal_state["QuADFilterGain_%i"%i], self.internal_state["QuADFilterOffset_%i"%i]) #Add initialization for the ramp self.QuADRampFrequency(self.internal_state["QuADRampFrequency"]) self.QuADRampAmplitude(self.internal_state["QuADRampAmplitude"]) self.QuADRampStatus(self.internal_state["QuADRampStatus"]) print "Default state set. Welcome to the QuADCon!" #sanity checking... #self.setRegister(0x0000, 0x01) #self.setRegister(0x0084, 0x0010) except Exception as e: print 'Could not run intialize: \n\n', e
def __init__(self): try: maxLoadAttempts = 10 #Allow for repeated loading to fix a bug I saw once loadedBitfile = 1 #Bitfile not yet loaded self.xem = ok.FrontPanel() devices = self.xem.GetDeviceCount() print "Found %d attached FPGAs" % (devices) if (devices > 0): if (self.xem.OpenBySerial(DEVICESERIAL) == 0): print "Opened an FPGA known as %s" % ( self.xem.GetDeviceID()) print "Now loading PLL configuration..." pll = ok.PLL22150() self.xem.GetEepromPLL22150Configuration(pll) pll.SetVCOParameters( int(FREQUENCY), 24) # NOTE - make sure this gives the right frequency pll.SetDiv1(pll.DivSrc_VCO, 4) pll.SetOutputSource(0, pll.ClkSrc_Div1By2) pll.SetOutputSource(1, pll.ClkSrc_Div1By2) pll.SetOutputEnable(1, True) print "System clock to be set @ %gMHz" % ( pll.GetOutputFrequency(0)) print "SPI clock to be set @ %gMHz" % ( pll.GetOutputFrequency(1)) self.xem.SetPLL22150Configuration(pll) print "Loading the bitfile..." attempts = 0 while (attempts <= maxLoadAttempts): loadedBitfile = self.xem.ConfigureFPGA(BITFILE) if (loadedBitfile == 0): print "Bitfile loaded!" break attempts += 1 except Exception as e: print "Initialization error" + str(e) sys.exit(1) try: self.internal_state = {} for i in range(8): self.internal_state["QuADDaughterType_%i" % i] = "DAC" self.internal_state["QuADDaughterOutputMode_%i" % i] = "Single" self.internal_state["QuADDaughterRangeMode_%i" % i] = "Positive" self.internal_state["QuADDaughterSource_%i" % i] = "ADC0" self.internal_state["QuADDaughterPositiveRail_%i" % i] = 5.0 self.internal_state["QuADDaughterNegativeRail_%i" % i] = 0.0 self.internal_state["QuADDaughterVoltage_%i" % i] = 0 for i in range(5): self.internal_state["QuADFilterType_%i" % i] = "P" self.internal_state["QuADFilterSource_%i" % i] = "ADC0" self.internal_state["QuADFilterCutoff_%i" % i] = 20000.0 self.internal_state["QuADFilterGain_%i" % i] = 1.0 self.internal_state["QuADFilterOffset_%i" % i] = 0.0 #Populate functions try: self.func_dict = {} for i, key in enumerate(self.internal_state): if 'QuADDaughter' in key: FuncID, ind = (key.split('QuADDaughter')[1]).split('_') FuncID = 'self.' + FuncID if DEBUG: print FuncID, ind setattr(self, key, lambda x, self=self, ind=ind, FuncID=FuncID: eval(FuncID)(ind, x)) except Exception as e: print 'ERROR in populating functions: \n\n', e # Now run initialization methods to reach a common start state print "Engaging default state..." # All daughters initialize as DACs self.setRegister(0x0000, 0x00) # All daughters initialize into non_feedback mode self.setRegister(0x0002, 0x00) # Update DAC source registers and set each into binary offset mode; RBUF configured for unity for i in range(8): self.setRegister(0x0080 + i, SOURCE_LIST["ADC0"]) self.setRegister(0x0010 + 2 * i, 0x0012) self.setRegister(0x0011 + 2 * i, 0x0020) self.xem.ActivateTriggerIn(0x40, i) print "Setting DAC at position " + str( i) + " to binary offset mode" # NOTE - the following zeroing is not necessary if you start in positive only mode # Write 0.0 volts to each of the DACs #code = int((10.0)/20.0 * 2**20) #code = code | 0x100000 #bottomBits = code & 0x00FFFF #topBits = (code & 0xFF0000) >> 16 self.setRegister(0x0010 + 2 * i, 0x0000) self.setRegister(0x0011 + 2 * i, 0x0010) self.xem.ActivateTriggerIn(0x40, i) print "Writing 0.0 to DAC at position " + str(i) # Set all of the feedback modes to positive only self.setRegister(0x0004, 0x00) # Set all of the filters to the on state # NOTE - I removed the control for the filter on/off; need to check this more thoroughly #self.setRegister(0x0003, 0x003F) # Update each of the filters to the internal state configuration for i in range(5): self.configureFilter(i, self.internal_state["QuADFilterType_%i"%i], \ self.internal_state["QuADFilterSource_%i"%i], self.internal_state["QuADFilterCutoff_%i"%i], \ self.internal_state["QuADFilterGain_%i"%i], self.internal_state["QuADFilterOffset_%i"%i]) print "Default state set. Welcome to the QuADCon!" except Exception as e: print 'Could not run intialize: \n\n', e
def __init__(self, passedmodule=0): self.lock = threading.Lock() xem = ok.FrontPanel() module_count = xem.GetDeviceCount() print "Found %d modules" % (module_count) if (module_count == 0): raise DeviceError("No XEMS found!") serial = [-1] * module_count for i in range(module_count): serial[i] = xem.GetDeviceListSerial(i) tmp = ok.FrontPanel() tmp.OpenBySerial(serial[i]) print "Module %d: XEM3001v%s.%s, ID: %s, serial #: %s " % ( i, tmp.GetDeviceMajorVersion(), tmp.GetDeviceMinorVersion(), tmp.GetDeviceID(), tmp.GetSerialNumber()) tmp = None if (module_count > 1): if passedmodule != 0: module = passedmodule else: print "Choose a module: " module = int(raw_input()) else: module = 0 print "module %d selected" % (module) xem.OpenBySerial(serial[module]) print "Loading PLL config" pll = ok.PLL22150() xem.GetEepromPLL22150Configuration(pll) pll.SetVCOParameters(200, 48) pll.SetDiv1(pll.DivSrc_VCO, 4) pll.SetDiv2(pll.DivSrc_VCO, 4) pll.SetOutputSource(0, pll.ClkSrc_Div1By2) for i in range(6): pll.SetOutputEnable(i, (i == 0)) print "Ref is at %gMHz, PLL is at %gMHz" % (pll.GetReference(), pll.GetVCOFrequency()) for i in range(6): if (pll.IsOutputEnabled(i)): print "Clock %d at %gMHz" % (i, pll.GetOutputFrequency(i)) print "Programming PLL" #xem.SetEepromPLL22150Configuration(pll) xem.SetPLL22150Configuration(pll) print "Programming FPGA" prog = xem.ConfigureFPGA('monocontroller.bit') if (prog != 0): print 'failed! code:', prog raise self.xem = xem self.name = xem.GetDeviceID() self.err1f = self.err3f = self.photodiode = self.trace = 0.0 self.netport = 13004 self.state = { 'DAC0wave': [0.0, 0.0, 200.0], 'DAC1wave': [0.0, 0.0, 200.0], 'FREQ': 0x07ae, 'DAC2wave': [0.0, 0.0, 200.0], 'DAC3wave': [0.0, 0.0, 200.0], 'DAC2wave': [0.0, 0.0, 200.0], 'DAC3wave': [0.0, 0.0, 200.0], 'DAC0lock': [1, 0, 0.00001, 0.00001, 0.00001, 0.01, 0], 'DAC1lock': [1, 0, 0.00001, 0.00001, 0.00001, 0.01, 0], 'DAC2lock': [1, 0, 0.00001, 0.00001, 0.00001, 0.01, 0], 'DAC3lock': [1, 0, 0.00001, 0.00001, 0.00001, 0.01, 0] } self.read_config() print "Initialization of hardware done"
def __init__(self): try: maxLoadAttempts = 10 #Allow for repeated loading to fix a bug I saw once loadedBitfile = 1 #Bitfile not yet loaded self.xem = ok.FrontPanel() devices = self.xem.GetDeviceCount() print "Found %d attached FPGAs" % (devices) if (devices > 0): if (self.xem.OpenBySerial(DEVICESERIAL) == 0): print "Opened an FPGA known as %s" % ( self.xem.GetDeviceID()) print "Now loading PLL configuration..." pll = ok.PLL22150() self.xem.GetEepromPLL22150Configuration(pll) pll.SetVCOParameters( int(FREQUENCY), 24) # NOTE - make sure this gives the right frequency pll.SetDiv1(pll.DivSrc_VCO, 4) pll.SetOutputSource(0, pll.ClkSrc_Div1By2) pll.SetOutputSource(1, pll.ClkSrc_Div1By2) pll.SetOutputEnable(1, True) print "System clock to be set @ %gMHz" % ( pll.GetOutputFrequency(0)) print "SPI clock to be set @ %gMHz" % ( pll.GetOutputFrequency(1)) self.xem.SetPLL22150Configuration(pll) print "Loading the bitfile..." attempts = 0 while (attempts <= maxLoadAttempts): loadedBitfile = self.xem.ConfigureFPGA(BITFILE) if (loadedBitfile == 0): print "Bitfile loaded!" break attempts += 1 except Exception as e: print "Initialization error" + str(e) sys.exit(1) self.internal_state = {} self.internal_state["QuAD674DaughterType"] = [ "DAC", "DAC", "DAC", "DAC", "DAC", "DAC", "DAC", "DAC" ] self.internal_state["QuAD674DaughterOutputMode"] = [ "Single", "Single", "Single", "Single", "Single", "Single", "Single", "Single" ] self.internal_state["QuAD674DaughterRangeMode"] = [ "Positive", "Positive", "Positive", "Positive", "Positive", "Positive", "Positive", "Positive" ] self.internal_state["QuAD674DaughterSource"] = [ "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0" ] self.internal_state['QuAD674DaughterPositiveRail'] = [ 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0 ] self.internal_state['QuAD674DaughterNegativeRail'] = [ 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 ] self.internal_state["QuAD674DaughterVoltage"] = [ 0, 0, 0, 0, 0, 0, 0, 0 ] self.internal_state["QuAD674FilterType"] = [ "P", "P", "P", "P", "P", "P" ] self.internal_state["QuAD674FilterSource"] = [ "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0" ] self.internal_state["QuAD674FilterCutoff"] = [ 20000.0, 20000.0, 20000.0, 20000.0, 20000.0, 20000.0 ] self.internal_state["QuAD674FilterGain"] = [ 1.0, 1.0, 1.0, 1.0, 1.0, 1.0 ] self.internal_state["QuAD674FilterOffset"] = [ 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 ] # Private internal states for distinguishing ADC voltages from DAC voltages self.internal_state["DACVoltage"] = [0, 0, 0, 0, 0, 0, 0, 0] self.internal_state["ADCVoltage"] = [0, 0, 0, 0, 0, 0, 0, 0] #Stuff for testing the scope interface self.internal_state["SCOPEDATA"] = [[0, 0], [1, 1], [1, 2]] #Settings for the ramp controller self.internal_state["QuAD674RampTarget"] = "DAC0" self.internal_state["QuAD674RampFrequency"] = 1000.0 self.internal_state["QuAD674RampStatus"] = "Off" # Now run initialization methods to reach a common start state print "Engaging default state..." # All daughters initialize as DACs self.setRegister(0x0000, 0x00) # All daughters initialize into non-feedback mode self.setRegister(0x0002, 0x00) # Update DAC source registers and set each into binary offset mode; RBUF configured for unity #ISSUE - Here is where I need to change the initialization into binary offset mode for i in range(8): self.setDaughterRails(i, self.internal_state['QuAD674DaughterNegativeRail'][i], \ self.internal_state['QuAD674DaughterPositiveRail'][i]) self.setRegister(0x0080 + i, SOURCE_LIST["ADC0"]) self.setRegister(0x0010 + 2 * i, 0x0002) self.setRegister(0x0011 + 2 * i, 0x0020) self.xem.ActivateTriggerIn(0x40, i) print "Setting DAC at position " + str( i) + " to twos complement mode" self.setRegister(0x0010 + 2 * i, 0x0000) self.setRegister(0x0011 + 2 * i, 0x0018) self.xem.ActivateTriggerIn(0x40, i) print "Writing 0.0 to DAC at position " + str(i) # Set all of the feedback modes to positive only self.setRegister(0x0004, 0x00) # Set all of the filters to the on state # ISSUE - I removed the control for the filter on/off; need to check this more thoroughly #self.setRegister(0x0003, 0x003F) # Update each of the filters to the internal state configuration for i in range(5): self.configureFilter(i, self.internal_state["QuAD674FilterType"][i], \ self.internal_state["QuAD674FilterSource"][i], self.internal_state["QuAD674FilterCutoff"][i], \ self.internal_state["QuAD674FilterGain"][i], self.internal_state["QuAD674FilterOffset"][i]) # Update the ramp to the internal state configuration self.configureRamp(self.internal_state["QuAD674RampTarget"], self.internal_state["QuAD674RampFrequency"]) print "Default state set. Welcome to the QuAD674Con!"
def configure(self, bit_file='OSC1_LITE_Control.bit', ignore_hash_error=False): """ Configure OSC1Lite. Should be called right after connected to the device :param ignore_hash_error: Allow bit file integrity check to fail :type ignore_hash_error: bool :param bit_file: Path to bit file of FPGA :type bit_file: str """ # Integrity check for bit file sha256 = self._sha256sum(bit_file) if sha256 != self._bit_file_sha256sum: logging.getLogger('OSC1Lite').error('Bit file hash mismatch') if not ignore_hash_error: raise ValueError( 'Bit file corrupted. ' + 'Expected SHA256: ' + self._bit_file_sha256sum + ', ' + 'Got: ' + sha256) # Configure the FPGA with self.device_lock: ret = self.dev.ConfigureFPGA(bit_file) if ret == ok.okCFrontPanel.NoError: pass elif ret == ok.okCFrontPanel.DeviceNotOpen: msg = 'ConfigureFPGA() returned DeviceNotOpen' logging.getLogger('OSC1Lite').fatal(msg) raise OSError(msg) elif ret == ok.okCFrontPanel.FileError: msg = 'ConfigureFPGA() returned FileError' logging.getLogger('OSC1Lite').fatal(msg) raise OSError(msg) elif ret == ok.okCFrontPanel.InvalidBitstream: msg = 'ConfigureFPGA() returned InvalidBitstream' logging.getLogger('OSC1Lite').fatal(msg) raise OSError(msg) elif ret == ok.okCFrontPanel.DoneNotHigh: msg = 'ConfigureFPGA() returned DoneNotHigh' logging.getLogger('OSC1Lite').fatal(msg) raise OSError(msg) elif ret == ok.okCFrontPanel.TransferError: msg = 'ConfigureFPGA() returned TransferError' logging.getLogger('OSC1Lite').fatal(msg) raise OSError(msg) elif ret == ok.okCFrontPanel.CommunicationError: msg = 'ConfigureFPGA() returned CommunicationError' logging.getLogger('OSC1Lite').fatal(msg) raise OSError(msg) elif ret == ok.okCFrontPanel.UnsupportedFeature: msg = 'ConfigureFPGA() returned UnsupportedFeature' logging.getLogger('OSC1Lite').fatal(msg) raise OSError(msg) else: msg = 'ConfigureFPGA() returned' + str(ret) logging.getLogger('OSC1Lite').fatal(msg) raise OSError(msg) # Configure the PLL clock used by FPGA # CLK = Ref / Q * P / div # Constraint: Ref / Q >= 0.25 MHz, Ref / Q * P >= 100 MHz pll = ok.PLL22150() # MHz pll.SetReference(48.0, False) # P Q P: [8, 2055], Q: [2, 129] pll.SetVCOParameters(125, 12) # pll.SetVCOParameters(512, 125) # div div: [4, 127] pll.SetDiv1(pll.DivSrc_VCO, 67) # pll.SetDiv1(pll.DivSrc_VCO, 15) pll.SetOutputSource(0, pll.ClkSrc_Div1ByN) pll.SetOutputEnable(0, True) self.dev.SetPLL22150Configuration(pll) logging.getLogger('OSC1Lite.PLL').debug( 'PLL output freq = {freq}MHz'.format( freq=pll.GetOutputFrequency(0))) self._freq = pll.GetOutputFrequency(0) * (10 ** 6) logging.getLogger('OSC1Lite').info('OSC1Lite configured.')
def __init__(self): try: maxLoadAttempts = 10 #Allow for repeated loading to fix a bug I saw once loadedBitfile = 1 #Bitfile not yet loaded self.xem = ok.FrontPanel() devices = self.xem.GetDeviceCount() print "Found %d attached FPGAs" % (devices) if (devices > 0): if (self.xem.OpenBySerial(DEVICESERIAL) == 0): print "Opened an FPGA known as %s" % ( self.xem.GetDeviceID()) print "Now loading PLL configuration..." pll = ok.PLL22150() self.xem.GetEepromPLL22150Configuration(pll) pll.SetVCOParameters( int(FREQUENCY), 24) # NOTE - make sure this gives the right frequency pll.SetDiv1(pll.DivSrc_VCO, 4) pll.SetOutputSource(0, pll.ClkSrc_Div1By2) pll.SetOutputSource(1, pll.ClkSrc_Div1By2) pll.SetOutputEnable(1, True) print "System clock to be set @ %gMHz" % ( pll.GetOutputFrequency(0)) print "SPI clock to be set @ %gMHz" % ( pll.GetOutputFrequency(1)) self.xem.SetPLL22150Configuration(pll) print "Loading the bitfile..." attempts = 0 while (attempts <= maxLoadAttempts): loadedBitfile = self.xem.ConfigureFPGA(BITFILE) if (loadedBitfile == 0): print "Bitfile loaded!" break attempts += 1 except Exception as e: print "Initialization error" + str(e) sys.exit(1) self.internal_state = {} self.internal_state["QuADDaughterType"] = [ "DAC", "DAC", "DAC", "DAC", "DAC", "DAC", "DAC", "DAC" ] self.internal_state["QuADDaughterOutputMode"] = [ "Single", "Single", "Single", "Single", "Single", "Single", "Single", "Single" ] self.internal_state["QuADDaughterRangeMode"] = [ "Positive", "Positive", "Positive", "Positive", "Positive", "Positive", "Positive", "Positive" ] self.internal_state["QuADDaughterSource"] = [ "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0" ] self.internal_state['QuADDaughterPositiveRail'] = [ 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0, 5.0 ] self.internal_state['QuADDaughterNegativeRail'] = [ 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 ] self.internal_state["QuADDaughterVoltage"] = [0, 0, 0, 0, 0, 0, 0, 0] self.internal_state["QuADFilterType"] = ["P", "P", "P", "P", "P", "P"] self.internal_state["QuADFilterSource"] = [ "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0", "ADC0" ] self.internal_state["QuADFilterCutoff"] = [ 20000.0, 20000.0, 20000.0, 20000.0, 20000.0, 20000.0 ] self.internal_state["QuADFilterGain"] = [1.0, 1.0, 1.0, 1.0, 1.0, 1.0] self.internal_state["QuADFilterOffset"] = [ 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 ] # Private internal states for distinguishing ADC voltages from DAC voltages self.internal_state["DACVoltage"] = [0, 0, 0, 0, 0, 0, 0, 0] self.internal_state["ADCVoltage"] = [0, 0, 0, 0, 0, 0, 0, 0] # Private internal states for controlling ouptut statuses #self.internal_state["RBUF"] = 0xFF #state of the ouput amplifier; controls the output rails #self.internal_state["2CM # Now run initialization methods to reach a common start state print "Engaging default state..." # All daughters initialize as DACs self.setRegister(0x0000, 0x00) # All daughters initialize into non-feedback mode self.setRegister(0x0002, 0x00) # Update DAC source registers and set each into binary offset mode; RBUF configured for unity for i in range(8): self.setRegister(0x0080 + i, SOURCE_LIST["ADC0"]) self.setRegister(0x0010 + 2 * i, 0x0012) self.setRegister(0x0011 + 2 * i, 0x0020) self.xem.ActivateTriggerIn(0x40, i) print "Setting DAC at position " + str( i) + " to binary offset mode" # NOTE - the following zeroing is not necessary if you start in positive only mode # Write 0.0 volts to each of the DACs #code = int((10.0)/20.0 * 2**20) #code = code | 0x100000 #bottomBits = code & 0x00FFFF #topBits = (code & 0xFF0000) >> 16 self.setRegister(0x0010 + 2 * i, 0x0000) self.setRegister(0x0011 + 2 * i, 0x0010) self.xem.ActivateTriggerIn(0x40, i) print "Writing 0.0 to DAC at position " + str(i) # Set all of the feedback modes to positive only self.setRegister(0x0004, 0x00) # Set all of the filters to the on state # NOTE - I removed the control for the filter on/off; need to check this more thoroughly #self.setRegister(0x0003, 0x003F) # Update each of the filters to the internal state configuration for i in range(5): self.configureFilter(i, self.internal_state["QuADFilterType"][i], \ self.internal_state["QuADFilterSource"][i], self.internal_state["QuADFilterCutoff"][i], \ self.internal_state["QuADFilterGain"][i], self.internal_state["QuADFilterOffset"][i]) print "Default state set. Welcome to the QuADCon!"
for i in range(module_count): serial = xem.GetDeviceListSerial(i) tmp = ok.FrontPanel() tmp.OpenBySerial(serial) id = tmp.GetDeviceID() tmp = None if (id == 'Photon Counter'): break if (id != 'Photon Counter'): raise "Didn't find Photon Counter in module list!" xem.OpenBySerial(serial) print "Found device called %s"%(xem.GetDeviceID()) print "Loading PLL config" pll = ok.PLL22150() xem.GetEepromPLL22150Configuration(pll) pll.SetVCOParameters(FREQUENCY, 48) pll.SetDiv1(pll.DivSrc_VCO,4) pll.SetDiv2(pll.DivSrc_VCO,4) pll.SetOutputSource(0, pll.ClkSrc_Div1By2) pll.SetOutputSource(1, pll.ClkSrc_Div1By2) for i in range(6): pll.SetOutputEnable(i, (i == 0)) print "Ref is at %gMHz, PLL is at %gMHz"%(pll.GetReference(), pll.GetVCOFrequency()) for i in range(6): if (pll.IsOutputEnabled(i)): print "Clock %d at %gMHz"%(i, pll.GetOutputFrequency(i)) print "Programming PLL" #xem.SetEepromPLL22150Configuration(pll)
def connect(self): self.device = ok.okCFrontPanel() devCount = 0 devCount = self.device.GetDeviceCount() # Print out list to user for decision. self.ctrl.log("Which of the following is the DAC FPGA?") for i in range(devCount): self.ctrl.log("{0}: Device Model: {1}, Device Serial: {2}".format(i + 1, getDeviceModelFromID(self.device.GetDeviceListModel(i)), self.device.GetDeviceListSerial(i))) cont = True intChoice = 0 # Make sure that the response is an integer within the correct range. while cont: cont = False self.ctrl.log("Enter an integer from 1 to {0}:".format(devCount)) choice = self.ctrl.getUserInput() try: intChoice = int(choice) except ValueError: cont = True self.ctrl.log("Not an integer.") if (intChoice > devCount) or (intChoice < 1): self.ctrl.log("Out of Range") cont = True self.device.OpenBySerial(self.device.GetDeviceListSerial(intChoice - 1)) self.device.ConfigureFPGA(self.BITFILE_NAME) if self.device.IsFrontPanelEnabled(): self.ctrl.log("FrontPanel host interface enabled.") self.ctrl.enableGUI() else: self.ctrl.log("ERROR: FrontPanel host interface not detected.") return self.ctrl.enableGUI() pll22150 = ok.PLL22150() # Get the existing settings to modify them self.device.GetPLL22150Configuration(pll22150) # Modify the PLL settings pll22150.SetReference(48.0, False) pll22150.SetVCOParameters(400, 48) pll22150.SetDiv1(ok.PLL22150.DivSrc_VCO, 400) pll22150.SetOutputSource(0, ok.PLL22150.ClkSrc_Div1ByN) pll22150.SetOutputEnable(0, True) # Output Current Settings self.ctrl.log("Details for pll:") self.ctrl.log("Reference: " + str(pll22150.GetReference()) + "\nVCO Freq: " + str(pll22150.GetVCOFrequency())) self.ctrl.log("Div1: " + str(pll22150.GetDiv1Divider()) + "\nSource: " + str(pll22150.GetDiv1Source())) self.ctrl.log("Output Freq: " + str(pll22150.GetOutputFrequency(0)) + "\nOutput Source: " + str(pll22150.GetOutputSource(0))) self.ctrl.log("VCO P: " + str(pll22150.GetVCOP()) + "\nVCO Q: "+ str(pll22150.GetVCOQ()) + '\n') # Save new settings to the device self.device.SetPLL22150Configuration(pll22150) self.device.EnableAsynchronousTransfers(True) self.setWire0InputBit(8, 0) self.setWire1InputBit(0, 0) self.updateIns() thread.start_new_thread(GUI.initAllDacListener, (self.ctrl.gui,)) thread.start_new_thread(FPGACom.startShift, (self,)) thread.start_new_thread(FPGACom.startFPChecker, (self,)) self.setDacState('idle')
import threading, time import ok import struct import numpy import analysis.fitting as fitting from tools.utility import GetSetItemsMixin #from pi3diamond import pi3d, CloseHandler xem = ok.FrontPanel() if (xem.OpenBySerial('') != 0): raise RuntimeError, 'Failed to open USB connection.' PLL = ok.PLL22150() xem.GetPLL22150Configuration(PLL) PLL.SetVCOParameters(100, 48) PLL.SetOutputSource(0, 2) PLL.SetOutputEnable(0, 2) #PLL.SetDiv1(1,10) xem.SetPLL22150Configuration(PLL) import datetime if (xem.ConfigureFPGA(r'D:\pi3diamondnew\toplevel.bit') != 0): raise RuntimeError, 'Failed to upload bit file to fpga.' class Flopper(SingletonHasTraits, GetSetItemsMixin): BufferLength = Range(low=1, high=512, value=512)