def outputreg(self, args):
srcaddr = args[0]
destreg = args[1]
return opcodes.portop(1, srcaddr, destreg, True)
def input(self, args):
srcaddr = args[0]
destreg = args[1]
return opcodes.portop(0, srcaddr, destreg)
def output(self, args):
destaddr = args[0]
srcreg = args[1]
return opcodes.portop(1, destaddr, srcreg)
oplist.append( opcodes.immop("MOVBTOHLOW", 0xF0, 5))
# and them
oplist.append( opcodes.aluop("AANDB", 5, 0) )
#load R6 with 0xF0F0
oplist.append( opcodes.immop("PASSB", 0xF0, 6))
oplist.append( opcodes.immop("MOVBTOHLOW", 0xF0, 6))
# or them
oplist.append( opcodes.aluop("AORB", 6, 0) )
# now test the event interface
#
# load Eaddr0 to register 7
oplist.append( opcodes.aluop("PASSA", 7, 0, True, 0))
oplist.append( opcodes.aluop("PASSA", 8, 0, True, 7))
for i in range(16):
oplist.append( opcodes.portop(1, 0x80 + i, i))
### ADDITION AND ADDITION WITH CARRY
# load register 0 with 0x1234
oplist.append(opcodes.immop("PASSB", 0x34, 0))
oplist.append(opcodes.immop("MOVBTOHLOW", 0x12, 0))
# load register 1 with 0x5678
oplist.append(opcodes.immop("PASSB", 0x78, 1))
oplist.append(opcodes.immop("MOVBTOHLOW", 0x56, 1))
# now add!
oplist.append(opcodes.aluop("PASSB", 2, 0))
oplist.append(opcodes.aluop("ADD", 2, 1))
# try an add with a carry bit
oplist.append(opcodes.immop("PASSB", 0xFF, 3))
oplist.append(opcodes.immop("MOVBTOHLOW", 0xFF, 3))
oplist.append(opcodes.immop("PASSB", 1, 4))