def test_portgraph_connect():
pg = PortGraph()
vid1 = pg.add_vertex()
vid2 = pg.add_vertex()
# invalid ports
assert_raises(InvalidPort, lambda: pg.connect(0, 1))
# invalid source port
pid1 = pg.add_in_port(vid1, "in")
assert_raises(InvalidPort, lambda: pg.connect(pid1 + 1, pid1))
# invalid out port
pid2 = pg.add_out_port(vid2, "out")
assert_raises(InvalidPort, lambda: pg.connect(pid2, pid1 + pid2 + 1))
# edge connection from in to out raise error
assert_raises(InvalidPort, lambda: pg.connect(pid1, pid2))
eid = pg.connect(pid2, pid1)
assert pg.source_port(eid) == pid2
assert pg.target_port(eid) == pid1
assert tuple(pg.connected_edges(pid1)) == (eid,)
assert tuple(pg.connected_edges(pid2)) == (eid,)
assert pid1 in pg.connected_ports(pid2)
assert pid2 in pg.connected_ports(pid1)
# can not duplicate edge
assert_raises(InvalidEdge, lambda: pg.connect(pid2, pid1, eid))
def test_portgraph_connect():
pg = PortGraph()
vid1 = pg.add_vertex()
vid2 = pg.add_vertex()
# invalid ports
assert_raises(InvalidPort, lambda: pg.connect(0, 1))
# invalid source port
pid1 = pg.add_in_port(vid1, "in")
assert_raises(InvalidPort, lambda: pg.connect(pid1 + 1, pid1))
# invalid out port
pid2 = pg.add_out_port(vid2, "out")
assert_raises(InvalidPort, lambda: pg.connect(pid2, pid1 + pid2 + 1))
# edge connection from in to out raise error
assert_raises(InvalidPort, lambda: pg.connect(pid1, pid2))
eid = pg.connect(pid2, pid1)
assert pg.source_port(eid) == pid2
assert pg.target_port(eid) == pid1
assert tuple(pg.connected_edges(pid1)) == (eid,)
assert tuple(pg.connected_edges(pid2)) == (eid,)
assert pid1 in pg.connected_ports(pid2)
assert pid2 in pg.connected_ports(pid1)
# can not duplicate edge
assert_raises(InvalidEdge, lambda: pg.connect(pid2, pid1, eid))
def test_portgraph_edge_connected_to_ports():
pg = PortGraph()
vid1 = pg.add_vertex()
vid2 = pg.add_vertex()
# method add_edge is forbidden
assert_raises(UserWarning, lambda: pg.add_edge((vid1, vid2)))
# connect to None port raises InvalidPort
assert_raises(InvalidPort, lambda: pg.connect(None, None))
pid1 = pg.add_out_port(vid1, "out")
pid2 = pg.add_in_port(vid2, "in")
assert_raises(InvalidPort, lambda: pg.connect(pid1, None))
assert_raises(InvalidPort, lambda: pg.connect(None, pid2))
# connect from in port to out port raises InvalidPort
assert_raises(InvalidPort, lambda: pg.connect(pid2, pid1))
# test connect is working
eid = pg.connect(pid1, pid2)
assert pg.source_port(eid) == pid1
assert pg.target_port(eid) == pid2
def test_portgraph_edge_connected_to_ports():
pg = PortGraph()
vid1 = pg.add_vertex()
vid2 = pg.add_vertex()
# method add_edge is forbidden
assert_raises(UserWarning, lambda: pg.add_edge((vid1, vid2)))
# connect to None port raises InvalidPort
assert_raises(InvalidPort, lambda: pg.connect(None, None))
pid1 = pg.add_out_port(vid1, "out")
pid2 = pg.add_in_port(vid2, "in")
assert_raises(InvalidPort, lambda: pg.connect(pid1, None))
assert_raises(InvalidPort, lambda: pg.connect(None, pid2))
# connect from in port to out port raises InvalidPort
assert_raises(InvalidPort, lambda: pg.connect(pid2, pid1))
# test connect is working
eid = pg.connect(pid1, pid2)
assert pg.source_port(eid) == pid1
assert pg.target_port(eid) == pid2
def test_portgraph_big():
pg = PortGraph()
vid1 = pg.add_vertex()
pid11 = pg.add_out_port(vid1, "out")
vid2 = pg.add_vertex()
pid21 = pg.add_out_port(vid2, "out")
vid3 = pg.add_vertex()
pid31 = pg.add_in_port(vid3, "in1")
pid32 = pg.add_in_port(vid3, "in2")
pid33 = pg.add_out_port(vid3, "res")
vid4 = pg.add_vertex()
pid41 = pg.add_in_port(vid4, "in")
eid1 = pg.connect(pid11, pid31)
eid2 = pg.connect(pid21, pid32)
pg.connect(pid33, pid41)
assert pg.source_port(eid1) == pid11
assert pg.target_port(eid2) == pid32
assert set(pg.out_ports(vid1)) == {pid11}
assert set(pg.in_ports(vid3)) == {pid31, pid32}
assert set(pg.ports(vid3)) == {pid31, pid32, pid33}
assert pg.is_in_port(pid31)
assert pg.is_out_port(pid11)
assert pg.vertex(pid11) == vid1
assert set(pg.connected_ports(pid11)) == {pid31}
assert set(pg.connected_edges(pid21)) == {eid2}
assert pg.out_port(vid1, "out") == pid11
assert pg.in_port(vid3, "in1") == pid31
assert_raises(InvalidPort, lambda: pg.connect(pid11, pid33))
pg.remove_port(pid33)
assert set(pg.connected_ports(pid41)) == set()
assert set(pg.out_edges(vid3)) == set()
assert_raises(InvalidPort, lambda: pg.is_in_port(pid33))
def test_portgraph_big():
pg = PortGraph()
vid1 = pg.add_vertex()
pid11 = pg.add_out_port(vid1, "out")
vid2 = pg.add_vertex()
pid21 = pg.add_out_port(vid2, "out")
vid3 = pg.add_vertex()
pid31 = pg.add_in_port(vid3, "in1")
pid32 = pg.add_in_port(vid3, "in2")
pid33 = pg.add_out_port(vid3, "res")
vid4 = pg.add_vertex()
pid41 = pg.add_in_port(vid4, "in")
eid1 = pg.connect(pid11, pid31)
eid2 = pg.connect(pid21, pid32)
pg.connect(pid33, pid41)
assert pg.source_port(eid1) == pid11
assert pg.target_port(eid2) == pid32
assert set(pg.out_ports(vid1)) == {pid11}
assert set(pg.in_ports(vid3)) == {pid31, pid32}
assert set(pg.ports(vid3)) == {pid31, pid32, pid33}
assert pg.is_in_port(pid31)
assert pg.is_out_port(pid11)
assert pg.vertex(pid11) == vid1
assert set(pg.connected_ports(pid11)) == {pid31}
assert set(pg.connected_edges(pid21)) == {eid2}
assert pg.out_port(vid1, "out") == pid11
assert pg.in_port(vid3, "in1") == pid31
assert_raises(InvalidPort, lambda: pg.connect(pid11, pid33))
pg.remove_port(pid33)
assert set(pg.connected_ports(pid41)) == set()
assert set(pg.out_edges(vid3)) == set()
assert_raises(InvalidPort, lambda: pg.is_in_port(pid33))
