class Root(RestController):
config = Config()
crush = Crush()
doc = Doc()
mon = Mon()
osd = Osd()
pool = Pool()
request = Request()
server = Server()
@expose(template='json')
def get(self, **kwargs):
"""
Show the basic information for the REST API
This includes values like api version or auth method
"""
return {
'api_version':
1,
'auth':
'Use "ceph tell mgr restful create_key <key>" to create a key pair, '
'pass it as HTTP Basic auth to authenticate',
'doc':
'See /doc endpoint',
'info':
"Ceph Manager RESTful API server",
}
def __init__(self, config_data):
device = config_data['device']
stations = config_data['stations']
devices = []
if device.lower() == 'auto':
devices = scan_for_devices()
else:
devices = [device]
self._devices = devices
self._device = devices[0]
self._tuners = []
for dev in self._devices:
tuner = Tuner(dev)
tuner.init_stations(stations)
self._tuners.append(tuner)
self._tuner = self._tuners[0]
self._osd = Osd()
self._sleep_time = 0.2
self._osd_time = None
self._first_digit = None
self._show_digit_time = 0
self._show_shutdown_message = False
def elaborate(self, platform):
m = Module()
# Read in the tilemap
tile_map = readhex(self.char_file)
tile_data = Memory(width=8 + self.inverse, depth=len(tile_map))
tile_data.init = tile_map
m.submodules.tr = tr = tile_data.read_port()
m.submodules.tw = tw = tile_data.write_port()
# Read in the font
font = readbin(self.font_file)
font_data = Memory(width=8, depth=4096)
font_data.init = font
m.submodules.fr = fr = font_data.read_port()
ram_wr = Signal()
ram_addr = Signal(32)
ram_di = Signal(8)
ram_do = Signal(8)
osd_en = Signal(reset=self.init_on)
osd_x = Signal(10)
osd_y = Signal(10)
dout = Signal(8)
tile_addr = Signal(12)
dout_align = Signal()
osd_pixel = Signal()
osd_r = Signal(8)
osd_g = Signal(8)
osd_b = Signal(8)
m.submodules.spimem = spimem = SpiMem(addr_bits=32)
m.d.comb += [
# Connect spimem
spimem.csn.eq(self.i_csn),
spimem.sclk.eq(self.i_sclk),
spimem.copi.eq(self.i_copi),
spimem.din.eq(ram_di),
self.o_cipo.eq(spimem.cipo),
ram_do.eq(spimem.dout),
ram_addr.eq(spimem.addr),
ram_wr.eq(spimem.wr),
# Connect tilemap
tw.addr.eq(ram_addr),
tw.en.eq(ram_wr & ram_addr[24:] == self.addr_display),
tw.data.eq(Mux(self.inverse, Cat(ram_di, ram_addr[16]), ram_di)),
]
with m.If(ram_wr & ram_addr[24:] == self.addr_enable):
m.d.pixel += osd_en.eq(ram_di[0])
m.d.comb += [
tile_addr.eq((osd_y >> 4) * self.chars_y + (osd_x >> 3)),
fr.data.eq(dout)
]
if (self.inverse):
m.d.comb += fr.addr.eq(
Cat(osd_y[4], tr.data) ^ Repl(tr.data[8], 8))
else:
m.d.comb += fr.addr.eq(Cat(osd_y[:4], tr.data))
m.submodules.osd = osd = Osd(
x_start=self.start_x,
x_stop=self.start_x + (8 * self.chars_x) - 1,
y_start=self.start_y,
y_stop=self.start_y + (8 * self.chars_y) - 1)
m.d.comb += [
osd.clk_ena.eq(1),
osd.i_r.eq(self.i_r),
osd.i_g.eq(self.i_g),
osd.i_b.eq(self.i_b),
osd.i_hsync.eq(self.i_hsync),
osd.i_vsync.eq(self.i_vsync),
osd.i_blank.eq(self.i_blank),
osd.i_osd_ena.eq(osd_en),
osd.i_osd_r.eq(osd_r),
osd.i_osd_g.eq(osd_g),
osd.i_osd_b.eq(osd_b),
osd_x.eq(osd.o_osd_x),
osd_y.eq(osd.o_osd_y),
osd_r.eq(osd.o_r),
osd_g.eq(osd.o_g),
osd_b.eq(osd.o_b),
self.o_hsync.eq(osd.o_hsync),
self.o_vsync.eq(osd.o_vsync),
self.o_blank.eq(osd.o_blank)
]
return m
