def test_InOutValRdyQueues( dump_vcd, qsize, pipeq, bypassq,
src_delay, sink_delay ):
msgs = range( 10 )
model = InOutValRdyQueueHarness( Bits( 8 ), qsize, pipeq, bypassq )
model.vcd_file = dump_vcd
sim = TestSrcSinkSim( model, msgs, msgs, src_delay, sink_delay )
sim.run_test()
def test_ValRdyPipeline(dump_vcd, stages, pipeq, bypassq, src_delay,
sink_delay):
msgs = range(20)
model = ValRdyPipelineHarness(Bits(8), stages, pipeq, bypassq)
model.vcd_file = dump_vcd
sim = TestSrcSinkSim(model, msgs, msgs, src_delay, sink_delay)
sim.run_test()
def test_InOutValRdyQueues(dump_vcd, qsize, pipeq, bypassq, src_delay,
sink_delay):
msgs = range(10)
model = InOutValRdyQueueHarness(Bits(8), qsize, pipeq, bypassq)
model.vcd_file = dump_vcd
sim = TestSrcSinkSim(model, msgs, msgs, src_delay, sink_delay)
sim.run_test()
def test_TestSrcSinkSim(dump_vcd, src_delay, sink_delay):
'Test with various source and sink delays.'
# Create some messages
src_msgs = sink_msgs = range(15)
# Instantiate the model
model = ValRdyBuffer(8)
# Dump a vcd if enabled
model.vcd_file = dump_vcd
# Create the simulator
sim = TestSrcSinkSim(model, src_msgs, sink_msgs, src_delay, sink_delay)
# Run the test
sim.run_test()
def test_TestSrcSinkSim( dump_vcd, src_delay, sink_delay ):
'Test with various source and sink delays.'
# Create some messages
src_msgs = sink_msgs = range( 15 )
# Instantiate the model
model = ValRdyBuffer( 8 )
# Dump a vcd if enabled
model.vcd_file = dump_vcd
# Create the simulator
sim = TestSrcSinkSim( model, src_msgs, sink_msgs,
src_delay, sink_delay )
# Run the test
sim.run_test()
def test_BundleExample():
# need this only because different input/output names
class BundleHarness( Model ):
vcd_file = '' # TestSrcSinkSim needs this defined
def __init__( s, dtype ):
s.in_ = InValRdyBundle ( dtype )
s.out = OutValRdyBundle( dtype )
s.m = BundleExample( dtype )
s.connect( s.in_, s.m.req )
s.connect( s.out, s.m.resp )
model = BundleHarness( 8 )
sim = TestSrcSinkSim( model, range(10), range(10), 2, 5 )
sim.run_test()
def test_BundleExample():
# need this only because different input/output names
class BundleHarness(Model):
vcd_file = '' # TestSrcSinkSim needs this defined
def __init__(s, dtype):
s.in_ = InValRdyBundle(dtype)
s.out = OutValRdyBundle(dtype)
s.m = BundleExample(dtype)
s.connect(s.in_, s.m.req)
s.connect(s.out, s.m.resp)
model = BundleHarness(8)
sim = TestSrcSinkSim(model, range(10), range(10), 2, 5)
sim.run_test()
def test_ValRdyPipeline(dump_vcd, stages, pipeq, bypassq, src_delay, sink_delay):
msgs = range(20)
model = ValRdyPipelineHarness(Bits(8), stages, pipeq, bypassq)
model.vcd_file = dump_vcd
sim = TestSrcSinkSim(model, msgs, msgs, src_delay, sink_delay)
sim.run_test()
