Beispiel #1
0
def run_valrdy_test(dump_vcd, test_verilog, test_vectors, model):

    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):

        model.enq.val.value = test_vector[0]
        model.enq.msg.value = test_vector[2]
        model.deq.rdy.value = test_vector[4]

    def tv_out(model, test_vector):

        assert model.enq.rdy.value == test_vector[1]
        assert model.deq.val.value == test_vector[3]
        if not test_vector[5] == '?':
            assert model.deq.msg.value == test_vector[5]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
def test_basics(dump_vcd):

    # Test vectors

    test_vectors = [
        # in      out
        [0x0000, 0x0001],
        [0x0001, 0x0002],
        [0x000a, 0x000b],
        [0x0401, 0x0402],
        [0xffff, 0x0000],
    ]

    # Instantiate and elaborate the model

    model = Incrementer()
    model.vcd_file = dump_vcd
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):
        model.in_.value = test_vector[0]

    def tv_out(model, test_vector):
        if test_vector[1] != '?':
            assert model.out == test_vector[1]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #3
0
def run_test_crossbar( model, test_vectors ):

  # Instantiate and elaborate the model

  model.elaborate()

  # Define functions mapping the test vector to ports in model

  num_inputs = len( model.in_ )

  def tv_in( model, test_vector ):
    n = num_inputs
    for i in range(num_inputs):
      model.in_[i].value = test_vector[i]
      model.sel[i].value = test_vector[n+i]

  def tv_out( model, test_vector ):
    n = 2*num_inputs
    for i in range(num_inputs):
      assert model.out[i].value == test_vector[n+i]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
def test_FindMax_2( test_verilog, dump_vcd ):

  test_vectors = [
    # in0   in1   out
    [ 0x01, 0x02, 0x02 ],
    [ 0x05, 0x02, 0x05 ],
    [ 0x00, 0x04, 0x04 ],
    [ 0x02, 0x03, 0x03 ],
    [ 0x06, 0x06, 0x06 ],
    [ 0x07, 0x03, 0x07 ],
    [ 0x08, 0x08, 0x08 ],
    [ 0x00, 0x00, 0x00 ],
    [ 0x32, 0x32, 0x32 ],
    [ 0x30, 0x31, 0x31 ],
  ]

  model = FindMax( 6, 2 )
  model.vcd_file = dump_vcd
  if test_verilog:
     model = TranslationTool( model )
  model.elaborate()

  def tv_in( model, test_vector ):
    model.in_[0].value = test_vector[0]
    model.in_[1].value = test_vector[1]

  def tv_out( model, test_vector ):
    if test_vector[2] != '?':
      assert model.out.value == test_vector[2]

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
def test_basics(dump_vcd):

    # Test vectors

    test_vectors = [
        # in      out
        [0x0000, 0x0001],
        [0x0001, 0x0002],
        [0x000A, 0x000B],
        [0x0401, 0x0402],
        [0xFFFF, 0x0000],
    ]

    # Instantiate and elaborate the model

    model = Incrementer()
    model.vcd_file = dump_vcd
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):
        model.in_.value = test_vector[0]

    def tv_out(model, test_vector):
        if test_vector[1] != "?":
            assert model.out == test_vector[1]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
def test_LeadingOne(test_verilog, dump_vcd):

    test_vectors = [
        # msg_in            , pos_out , msg_out
        [0b0111111111111111, 0b001110, 0b0111111111111111],
        [0b0000001110000000, 0b001001, 0b0000001110000000],
        [0b0000010000000000, 0b001010, 0b0000010000000000],
        [0b0000000000000000, 0b000000, 0b0000000000000000],
        [0b0000000000001000, 0b000011, 0b0000000000001000],
        [0b0000110000000010, 0b001001, 0b0000110000000010],
    ]

    # Instantiate and elaborate the model

    model = LeadingOne(16, 6)
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):
        model.msg_in.value = test_vector[0]

    def tv_out(model, test_vector):
        assert model.pos_out.value == test_vector[1]
        assert model.msg_out.value == test_vector[2]

# Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
def test_FindMaxIdx_3( test_verilog, dump_vcd ):

  test_vectors = [
    # in0   in1   in2   out   idx
    [ 0x01, 0x02, 0x03, 0x03, 0x2 ],
    [ 0x05, 0x02, 0x03, 0x05, 0x0 ],
    [ 0x00, 0x04, 0x03, 0x04, 0x1 ],
    [ 0x02, 0x03, 0x03, 0x03, 0x1 ],
    [ 0x06, 0x06, 0x05, 0x06, 0x0 ],
    [ 0x07, 0x03, 0x07, 0x07, 0x0 ],
    [ 0x08, 0x08, 0x08, 0x08, 0x0 ],
    [ 0x00, 0x00, 0x00, 0x00, 0x0 ],
    [ 0x32, 0x32, 0x32, 0x32, 0x0 ],
    [ 0x30, 0x30, 0x31, 0x31, 0x2 ],
  ]

  model = FindMaxIdx( 6, 3 )
  model.vcd_file = dump_vcd
  if test_verilog:
     model = TranslationTool( model )
  model.elaborate()

  def tv_in( model, test_vector ):
    model.in_[0].value = test_vector[0]
    model.in_[1].value = test_vector[1]
    model.in_[2].value = test_vector[2]

  def tv_out( model, test_vector ):
    if test_vector[3] != '?':
      assert model.out.value == test_vector[3]
    if test_vector[4] != '?':
      assert model.idx.value == test_vector[4]

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
def test_mapper( test_verilog, dump_vcd ):

  a = random.randint(0,0x1ffffffffffff)
  b = random.randint(0,0x1ffffffffffff)
  c = Bits(49,a ^ b)
  d = Bits(49,0)
  for i in xrange(49):
    d += c[i:i+1]

  test_vectors = [
     # in0              in1              out
     [ 0x1ffffffffffff, 0x0000000000000, 0x31],
     [ a,               b,               d   ]
  ]

  model = MapperPRTL()
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  def tv_in( model, test_vector ):
    model.in0.value = test_vector[0]
    model.in1.value = test_vector[1]
  
  def tv_out( model, test_vector ):
    if test_vector[2] != '?':
      assert model.out.value == test_vector[2]

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #9
0
def run_test_bus(model, test_vectors):

    # Instantiate and elaborate the model

    model.elaborate()

    # Define functions mapping the test vector to ports in model

    num_inputs = len(model.in_)

    def tv_in(model, test_vector):
        n = num_inputs
        for i in range(num_inputs):
            model.in_[i].value = test_vector[i]
        model.sel.value = test_vector[n]

    def tv_out(model, test_vector):
        n = num_inputs + 1
        for i in range(num_inputs):
            assert model.out[i].value == test_vector[n + i]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
def test_adder(test_verilog):

    # Test vectors

    test_vectors = [
        # in0     in1      out
        [0x0001, 0x0010, 0x0011],
    ]

    # Instantiate and elaborate the model

    model = Adder()
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):
        model.in0.value = test_vector[0]
        model.in1.value = test_vector[1]

    def tv_out(model, test_vector):
        if test_vector[2] != '?':
            assert model.out.value == test_vector[2]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #11
0
def test_mapper(test_verilog, dump_vcd):

    a = random.randint(0, 0x1ffffffffffff)
    b = random.randint(0, 0x1ffffffffffff)
    c = Bits(49, a ^ b)
    d = Bits(49, 0)
    for i in xrange(49):
        d += c[i:i + 1]

    test_vectors = [
        # in0              in1              out
        [0x1ffffffffffff, 0x0000000000000, 0x31],
        [a, b, d]
    ]

    model = MapperPRTL()
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    def tv_in(model, test_vector):
        model.in0.value = test_vector[0]
        model.in1.value = test_vector[1]

    def tv_out(model, test_vector):
        if test_vector[2] != '?':
            assert model.out.value == test_vector[2]

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #12
0
def run_valrdy_test(dump_vcd, test_verilog, test_vectors, model):

    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):

        model.enq.val.value = test_vector[0]
        model.enq.msg.value = test_vector[2]
        model.deq.rdy.value = test_vector[4]

    def tv_out(model, test_vector):

        assert model.enq.rdy.value == test_vector[1]
        assert model.deq.val.value == test_vector[3]
        if not test_vector[5] == "?":
            assert model.deq.msg.value == test_vector[5]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #13
0
def test_FindMax_2(test_verilog, dump_vcd):

    test_vectors = [
        # in0   in1   out
        [0x01, 0x02, 0x02],
        [0x05, 0x02, 0x05],
        [0x00, 0x04, 0x04],
        [0x02, 0x03, 0x03],
        [0x06, 0x06, 0x06],
        [0x07, 0x03, 0x07],
        [0x08, 0x08, 0x08],
        [0x00, 0x00, 0x00],
        [0x32, 0x32, 0x32],
        [0x30, 0x31, 0x31],
    ]

    model = FindMax(6, 2)
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    def tv_in(model, test_vector):
        model.in_[0].value = test_vector[0]
        model.in_[1].value = test_vector[1]

    def tv_out(model, test_vector):
        if test_vector[2] != '?':
            assert model.out.value == test_vector[2]

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #14
0
def test_LaneManager_TwoLanes(dump_vcd, test_verilog):

    # Select and elaborate the model under test

    model = LaneManager(2)
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    data_nbits = 32

    # Define test input and output functions

    def tv_in(model, test_vector):
        model.from_cpu.val.value = test_vector[0]
        model.from_cpu.msg[data_nbits:].value = test_vector[1]
        model.from_cpu.msg[:data_nbits].value = test_vector[2]
        model.done[0].value = test_vector[3]
        model.done[1].value = test_vector[4]

    def tv_out(model, test_vector):
        assert model.from_cpu.rdy == test_vector[5]
        assert model.go == test_vector[6]
        assert model.size == test_vector[7]
        assert model.r_baddr == test_vector[8]
        assert model.v_baddr == test_vector[9]
        assert model.d_baddr == test_vector[10]
        assert model.to_cpu == test_vector[11]

    # Define the test vectors
    test_vectors = [
        # Inputs---------------  Outputs------------------------------------
        # val addr data   dones  rdy go sz rb    vb    db    to_cpu
        [0, 1, 0x77, 0, 0, 1, 0, 0, 0x00, 0x00, 0x00, 0],
        [0, 0, 0x77, 0, 0, 1, 0, 0, 0x00, 0x00, 0x00, 0],
        [1, 1, 0x08, 0, 0, 1, 0, 0, 0x00, 0x00, 0x00, 0],
        [1, 1, 0x06, 0, 0, 1, 0, 8, 0x00, 0x00, 0x00, 0],
        [1, 2, 0x20, 0, 0, 1, 0, 6, 0x00, 0x00, 0x00, 0],
        [1, 3, 0x30, 0, 0, 1, 0, 6, 0x20, 0x00, 0x00, 0],
        [1, 4, 0x50, 0, 0, 1, 0, 6, 0x20, 0x30, 0x00, 0],
        [1, 0, 0x50, 0, 0, 1, 0, 6, 0x20, 0x30, 0x50, 0],
        [1, 0, 0x01, 0, 0, 1, 0, 6, 0x20, 0x30, 0x50, 0],
        [0, 0, 0x01, 0, 0, 0, 1, 6, 0x20, 0x30, 0x50, 0],
        [0, 0, 0x01, 0, 0, 0, 0, 6, 0x20, 0x30, 0x50, 0],
        [0, 0, 0x01, 0, 0, 0, 0, 6, 0x20, 0x30, 0x50, 0],
        [0, 0, 0x01, 0, 0, 0, 0, 6, 0x20, 0x30, 0x50, 0],
        [0, 0, 0x01, 1, 0, 0, 0, 6, 0x20, 0x30, 0x50, 0],
        [0, 0, 0x01, 0, 1, 0, 0, 6, 0x20, 0x30, 0x50, 0],
        [0, 0, 0x01, 0, 1, 0, 0, 6, 0x20, 0x30, 0x50, 0],
        [0, 0, 0x01, 0, 0, 0, 0, 6, 0x20, 0x30, 0x50, 1],
        [0, 0, 0x01, 0, 0, 1, 0, 6, 0x20, 0x30, 0x50, 0],
        [0, 0, 0x01, 0, 0, 1, 0, 6, 0x20, 0x30, 0x50, 0],
    ]

    # Create the simulator and configure it
    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)

    # Run the simulator
    sim.run_test()
Beispiel #15
0
def test_LaneManager_TwoLanes( dump_vcd, test_verilog ):

  # Select and elaborate the model under test

  model = LaneManager( 2 )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  data_nbits = 32

  # Define test input and output functions

  def tv_in( model, test_vector ):
    model.from_cpu.val             .value = test_vector[0]
    model.from_cpu.msg[data_nbits:].value = test_vector[1]
    model.from_cpu.msg[:data_nbits].value = test_vector[2]
    model.done[0]                  .value = test_vector[3]
    model.done[1]                  .value = test_vector[4]

  def tv_out( model, test_vector ):
    assert model.from_cpu.rdy == test_vector[5]
    assert model.go           == test_vector[6]
    assert model.size         == test_vector[7]
    assert model.r_baddr      == test_vector[8]
    assert model.v_baddr      == test_vector[9]
    assert model.d_baddr      == test_vector[10]
    assert model.to_cpu       == test_vector[11]

  # Define the test vectors
  test_vectors = [
    # Inputs---------------  Outputs------------------------------------
    # val addr data   dones  rdy go sz rb    vb    db    to_cpu
    [ 0,  1,   0x77,  0, 0,  1,  0, 0, 0x00, 0x00, 0x00, 0 ],
    [ 0,  0,   0x77,  0, 0,  1,  0, 0, 0x00, 0x00, 0x00, 0 ],
    [ 1,  1,   0x08,  0, 0,  1,  0, 0, 0x00, 0x00, 0x00, 0 ],
    [ 1,  1,   0x06,  0, 0,  1,  0, 8, 0x00, 0x00, 0x00, 0 ],
    [ 1,  2,   0x20,  0, 0,  1,  0, 6, 0x00, 0x00, 0x00, 0 ],
    [ 1,  3,   0x30,  0, 0,  1,  0, 6, 0x20, 0x00, 0x00, 0 ],
    [ 1,  4,   0x50,  0, 0,  1,  0, 6, 0x20, 0x30, 0x00, 0 ],
    [ 1,  0,   0x50,  0, 0,  1,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 1,  0,   0x01,  0, 0,  1,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 0,  0,  1, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 0,  0,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 0,  0,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 0,  0,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  1, 0,  0,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 1,  0,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 1,  0,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 0,  0,  0, 6, 0x20, 0x30, 0x50, 1 ],
    [ 0,  0,   0x01,  0, 0,  1,  0, 6, 0x20, 0x30, 0x50, 0 ],
    [ 0,  0,   0x01,  0, 0,  1,  0, 6, 0x20, 0x30, 0x50, 0 ],
  ]

  # Create the simulator and configure it
  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )

  # Run the simulator
  sim.run_test()
def test_adder( test_verilog ):

  # Test vectors

  test_vectors = [
    # in0     in1      out   
    [ 0x0001, 0x0010,  0x0011],
  ]

  # Instantiate and elaborate the model

  model = Adder()
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.in0.value = test_vector[0]
    model.in1.value = test_vector[1]

  def tv_out( model, test_vector ):
    if test_vector[2] != '?':
      assert model.out.value == test_vector[2]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #17
0
def test_AdderTree( test_verilog, dump_vcd ):

  test_vectors = [
    # in0   in1   in2   out
    [ 0x01, 0x02, 0x02, 0x05 ],
    [ 0x05, 0x02, 0x05, 0x0c ],
    [ 0x00, 0x04, 0x04, 0x08 ],
    [ 0x02, 0x03, 0x03, 0x08 ],
    [ 0x06, 0x06, 0x06, 0x12 ],
    [ 0x07, 0x03, 0x07, 0x11 ],
    [ 0x08, 0x08, 0x08, 0x18 ],
    [ 0x00, 0x00, 0x00, 0x00 ],
    [ 0x32, 0x32, 0x32, 0x96 ],
    [ 0x30, 0x31, 0x31, 0x92 ],
  ]

  model = AdderTree( 6, 3 )
  model.vcd_file = dump_vcd
  if test_verilog:
     model = TranslationTool( model )
  model.elaborate()

  def tv_in( model, test_vector ):
    model.in_[0].value = test_vector[0]
    model.in_[1].value = test_vector[1]
    model.in_[2].value = test_vector[2]

  def tv_out( model, test_vector ):
    if test_vector[3] != '?':
      assert model.out.value == test_vector[3]

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #18
0
def run_test_queue( dump_vcd, test_verilog, ModelType, num_entries,
                    test_vectors ):
  """Tests for Multiple Entry Queues."""

  # Instantiate and elaborate the model

  model = ModelType( num_entries, 16 )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):

    model.enq.val.value = test_vector[0]
    model.enq.msg.value = test_vector[2]
    model.deq.rdy.value = test_vector[4]

  def tv_out( model, test_vector ):

    assert model.enq.rdy.value   == test_vector[1]
    assert model.deq.val.value   == test_vector[3]
    if not test_vector[5] == '?':
      assert model.deq.msg.value == test_vector[5]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #19
0
def test_FindMaxIdx_3(test_verilog, dump_vcd):

    test_vectors = [
        # in0   in1   in2   out   idx
        [0x01, 0x02, 0x03, 0x03, 0x2],
        [0x05, 0x02, 0x03, 0x05, 0x0],
        [0x00, 0x04, 0x03, 0x04, 0x1],
        [0x02, 0x03, 0x03, 0x03, 0x1],
        [0x06, 0x06, 0x05, 0x06, 0x0],
        [0x07, 0x03, 0x07, 0x07, 0x0],
        [0x08, 0x08, 0x08, 0x08, 0x0],
        [0x00, 0x00, 0x00, 0x00, 0x0],
        [0x32, 0x32, 0x32, 0x32, 0x0],
        [0x30, 0x30, 0x31, 0x31, 0x2],
    ]

    model = FindMaxIdx(6, 3)
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    def tv_in(model, test_vector):
        model.in_[0].value = test_vector[0]
        model.in_[1].value = test_vector[1]
        model.in_[2].value = test_vector[2]

    def tv_out(model, test_vector):
        if test_vector[3] != '?':
            assert model.out.value == test_vector[3]
        if test_vector[4] != '?':
            assert model.idx.value == test_vector[4]

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
def  test_LeadingOne( test_verilog, dump_vcd ):

   test_vectors = [
      # msg_in            , pos_out , msg_out
      [ 0b0111111111111111, 0b001110, 0b0111111111111111 ],
      [ 0b0000001110000000, 0b001001, 0b0000001110000000 ],
      [ 0b0000010000000000, 0b001010, 0b0000010000000000 ],
      [ 0b0000000000000000, 0b000000, 0b0000000000000000 ],
      [ 0b0000000000001000, 0b000011, 0b0000000000001000 ],
      [ 0b0000110000000010, 0b001001, 0b0000110000000010 ],
   ]

  # Instantiate and elaborate the model

   model = LeadingOne(16,6)
   model.vcd_file = dump_vcd
   if test_verilog:
     model = TranslationTool( model )
   model.elaborate()

  # Define functions mapping the test vector to ports in model

   def tv_in( model, test_vector ):
     model.msg_in.value = test_vector[0]

   def tv_out( model, test_vector ):
     assert model.pos_out.value     == test_vector[1]
     assert model.msg_out.value == test_vector[2]

  # Run the test

   sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
   sim.run_test()
def test_AdderTree(test_verilog, dump_vcd):

    test_vectors = [
        # in0   in1   in2   out
        [0x01, 0x02, 0x02, 0x05],
        [0x05, 0x02, 0x05, 0x0C],
        [0x00, 0x04, 0x04, 0x08],
        [0x02, 0x03, 0x03, 0x08],
        [0x06, 0x06, 0x06, 0x12],
        [0x07, 0x03, 0x07, 0x11],
        [0x08, 0x08, 0x08, 0x18],
        [0x00, 0x00, 0x00, 0x00],
        [0x32, 0x32, 0x32, 0x96],
        [0x30, 0x31, 0x31, 0x92],
    ]

    model = AdderTree(6, 3)
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    def tv_in(model, test_vector):
        model.in_[0].value = test_vector[0]
        model.in_[1].value = test_vector[1]
        model.in_[2].value = test_vector[2]

    def tv_out(model, test_vector):
        if test_vector[3] != "?":
            assert model.out.value == test_vector[3]

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #22
0
def run_test_mux( dump_vcd, test_verilog,
                  ModelType, num_inputs, test_vectors ):

  # Instantiate and elaborate the model

  model = ModelType(16, num_inputs)
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    for i in range(num_inputs):
      model.in_[i].value = test_vector[i]
    model.sel.value = test_vector[num_inputs]

  def tv_out( model, test_vector ):
    if test_vector[num_inputs] != '?':
      assert model.out.value == test_vector[num_inputs+1]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #23
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def test_SRAMBytesSync_rst_1rw(dump_vcd, test_verilog):

    # Test vectors

    test_vectors = [

        #  wen,  wben,    addr, wdata,      rdata
        [0, 0b0000, 0, 0x00000000, '?'],
        [0, 0b0000, 0, 0x00000000, 0xa0a0a0a0],
        [1, 0b1111, 0, 0x00000000, 0xa0a0a0a0],
        [0, 0b0000, 0, 0x00000000, '?'],
        [0, 0b0000, 0, 0x00000000, 0x00000000],
        [1, 0b0001, 0, 0xdeadbeef, 0x00000000],
        [0, 0b0000, 0, 0x00000000, '?'],
        [0, 0b0000, 0, 0x00000000, 0x000000ef],
        [1, 0b0110, 0, 0xabcdefab, 0x000000ef],
        [0, 0b0000, 0, 0x00000000, '?'],
        [0, 0b0000, 0, 0x00000000, 0x00cdefef],
        [1, 0b1011, 0, 0xff000000, 0x00cdefef],
        [0, 0b0000, 0, 0x00000000, '?'],
        [0, 0b0000, 0, 0x00000000, 0xffcd0000],
        [1, 0b1111, 0, 0xdeadbeef, 0xffcd0000],
        [0, 0b0000, 0, 0x00000000, '?'],
        [0, 0b0000, 0, 0x00000000, 0xdeadbeef],
        [1, 0b1111, 0, 0xffffffff, 0xdeadbeef],
        [0, 0b0000, 0, 0x00000000, '?'],
        [0, 0b0000, 0, 0x00000000, 0xffffffff],
        [0, 0b0000, 12, 0x00000000, 0xffffffff],
        [1, 0b1111, 12, 0xdeadbeef, 0xa0a0a0a0],
        [0, 0b1111, 12, 0xbbbbcccc, '?'],
        [0, 0b0000, 12, 0x00000000, 0xdeadbeef],
    ]

    # Instantiate and elaborate the model

    model = SRAMBytesSync_rst_1rw(16, 4, reset_value=0xa0a0a0a0)
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):
        model.wen.value = test_vector[0]
        model.wben.value = test_vector[1]
        model.addr.value = test_vector[2]
        model.wdata.value = test_vector[3]

    def tv_out(model, test_vector):
        if test_vector[4] != '?':
            assert model.rdata.value == test_vector[4]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #24
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def test_1entry_normal_queue_tv( dump_vcd, test_verilog ):
  '''Single-Element Normal Queue Test Vector Tests

  Directed performance tests for single element queue. We use the
  TestVectorSimulator to do some white box testing.
  '''

  test_vectors = [

    # Enqueue one element and then dequeue it
    # enq.val enq.rdy enq.msg  deq.val deq.rdy deq.msg
    [ 1,      1,      0x0001,  0,      1,      '?'    ],
    [ 0,      0,      0x0000,  1,      1,      0x0001 ],
    [ 0,      1,      0x0000,  0,      0,      '?'    ],

    # Fill in the queue and enq/deq at the same time
    # enq.val enq.rdy enq.msg  deq.val deq.rdy deq.msg
    [ 1,      1,      0x0002,  0,      0,      '?'    ],
    [ 1,      0,      0x0003,  1,      0,      0x0002 ],
    [ 0,      0,      0x0003,  1,      0,      0x0002 ],
    [ 1,      0,      0x0003,  1,      1,      0x0002 ],
    [ 1,      1,      0x0003,  0,      1,      '?'    ],
    [ 1,      0,      0x0004,  1,      1,      0x0003 ],
    [ 1,      1,      0x0004,  0,      1,      '?'    ],
    [ 0,      0,      0x0004,  1,      1,      0x0004 ],
    [ 0,      1,      0x0004,  0,      1,      '?'    ],

  ]

  # Instantiate and elaborate the model

  model = SingleElementNormalQueue( 16 )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):

    model.enq.val.value = test_vector[0]
    model.enq.msg.value = test_vector[2]
    model.deq.rdy.value = test_vector[4]

  def tv_out( model, test_vector ):

    assert model.enq.rdy.value   == test_vector[1]
    assert model.deq.val.value   == test_vector[3]
    if not test_vector[5] == '?':
      assert model.deq.msg.value == test_vector[5]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #25
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def test_portbundle_bitstruct_param_queue_sim( dump_vcd ):

  test_vectors = [

    # Enqueue one element and then dequeue it
    # enq_val enq_rdy enq_bits deq_val deq_rdy deq_bits
    [ 1,      1,      0x0001,  0,      1,      '?'    ],
    [ 0,      0,      0x0000,  1,      1,      0x0001 ],
    [ 0,      1,      0x0000,  0,      0,      '?'    ],

    # Fill in the queue and enq/deq at the same time
    # enq_val enq_rdy enq_bits deq_val deq_rdy deq_bits
    [ 1,      1,      0x0002,  0,      0,      '?'    ],
    [ 1,      0,      0x0003,  1,      0,      0x0002 ],
    [ 0,      0,      0x0003,  1,      0,      0x0002 ],
    [ 1,      0,      0x0003,  1,      1,      0x0002 ],
    [ 1,      1,      0x0003,  0,      1,      '?'    ],
    [ 1,      0,      0x0004,  1,      1,      0x0003 ],
    [ 1,      1,      0x0004,  0,      1,      '?'    ],
    [ 0,      0,      0x0004,  1,      1,      0x0004 ],
    [ 0,      1,      0x0004,  0,      1,      '?'    ],

  ]

  # Instantiate and elaborate the model

  nports = 4
  model  = ParameterizablePortBundleBitStructQueue( 16, nports )
  model.vcd_file = dump_vcd
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):

    for i in range( nports ):
      model.enq[i].val.v = test_vector[0]
      model.enq[i].msg.v = test_vector[2]
      model.deq[i].rdy.v = test_vector[4]

  def tv_out( model, test_vector ):

    for i in range( nports ):
      assert model.enq[i].rdy.v   == test_vector[1]
      assert model.deq[i].val.v   == test_vector[3]
      if not test_vector[5] == '?':
        assert model.deq[i].msg.v == test_vector[5]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #26
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def test_portbundle_bitstruct_param_queue_sim(dump_vcd):

    test_vectors = [

        # Enqueue one element and then dequeue it
        # enq_val enq_rdy enq_bits deq_val deq_rdy deq_bits
        [1, 1, 0x0001, 0, 1, '?'],
        [0, 0, 0x0000, 1, 1, 0x0001],
        [0, 1, 0x0000, 0, 0, '?'],

        # Fill in the queue and enq/deq at the same time
        # enq_val enq_rdy enq_bits deq_val deq_rdy deq_bits
        [1, 1, 0x0002, 0, 0, '?'],
        [1, 0, 0x0003, 1, 0, 0x0002],
        [0, 0, 0x0003, 1, 0, 0x0002],
        [1, 0, 0x0003, 1, 1, 0x0002],
        [1, 1, 0x0003, 0, 1, '?'],
        [1, 0, 0x0004, 1, 1, 0x0003],
        [1, 1, 0x0004, 0, 1, '?'],
        [0, 0, 0x0004, 1, 1, 0x0004],
        [0, 1, 0x0004, 0, 1, '?'],
    ]

    # Instantiate and elaborate the model

    nports = 4
    model = ParameterizablePortBundleBitStructQueue(16, nports)
    model.vcd_file = dump_vcd
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):

        for i in range(nports):
            model.enq[i].val.v = test_vector[0]
            model.enq[i].msg.v = test_vector[2]
            model.deq[i].rdy.v = test_vector[4]

    def tv_out(model, test_vector):

        for i in range(nports):
            assert model.enq[i].rdy.v == test_vector[1]
            assert model.deq[i].val.v == test_vector[3]
            if not test_vector[5] == '?':
                assert model.deq[i].msg.v == test_vector[5]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #27
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def test_regfile_2R2W( dump_vcd, test_verilog ):

  # Test vectors

  test_vectors = [
    # ---read 0---  ---read 1---  -----write 0-----  -----write 1-----
    # addr    data  addr    data  en  addr     data  en  addr     data
    [   10, '?',      14, '?',     0,   10,  0x0000,  0,   10,  0x0000],
    [   13, '?',      14, '?',     1,   14,  0x0005,  0,   14,  0x0005],
    [   12, '?',      14, 0x0005,  0,   10,  0x0006,  1,   12,  0x0006],
    [   12, 0x0006,   12, 0x0006,  0,   13,  0x0008,  1,   13,  0x0009],
    [   12, 0x0006,   12, 0x0006,  0,   13,  0x0007,  0,   13,  0x000a],
    [   17, '?',      13, 0x0009,  0,   17,  0x0090,  1,   17,  0x0010],
    [   14, 0x0005,   17, 0x0010,  0,   17,  0x0090,  0,   17,  0x0020],
    [   16, '?',      17, 0x0010,  1,   17,  0x0090,  1,   16,  0x0090],
    [   16, 0x0090,   17, 0x0090,  1,   17,  0x0011,  0,   16,  0x0011],
    [   16, 0x0090,   17, 0x0011,  0,   10,  0x0000,  0,   10,  0x0000],
  ]

  # Instantiate and elaborate the model

  model = RegisterFile( dtype=16, nregs=32, rd_ports=2, wr_ports=2 )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model, verilator_xinit=test_verilog )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.rd_addr[0].value = test_vector[0]
    model.rd_addr[1].value = test_vector[2]
    model.wr_en  [0].value = test_vector[4]
    model.wr_addr[0].value = test_vector[5]
    model.wr_data[0].value = test_vector[6]
    model.wr_en  [1].value = test_vector[7]
    model.wr_addr[1].value = test_vector[8]
    model.wr_data[1].value = test_vector[9]

  def tv_out( model, test_vector ):
    if test_vector[1] != '?':
      assert model.rd_data[0].value == test_vector[1]
    if test_vector[3] != '?':
      assert model.rd_data[1].value == test_vector[3]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #28
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def test_regfile_2R2W(dump_vcd, test_verilog):

    # Test vectors

    test_vectors = [
        # ---read 0---  ---read 1---  -----write 0-----  -----write 1-----
        # addr    data  addr    data  en  addr     data  en  addr     data
        [10, '?', 14, '?', 0, 10, 0x0000, 0, 10, 0x0000],
        [13, '?', 14, '?', 1, 14, 0x0005, 0, 14, 0x0005],
        [12, '?', 14, 0x0005, 0, 10, 0x0006, 1, 12, 0x0006],
        [12, 0x0006, 12, 0x0006, 0, 13, 0x0008, 1, 13, 0x0009],
        [12, 0x0006, 12, 0x0006, 0, 13, 0x0007, 0, 13, 0x000a],
        [17, '?', 13, 0x0009, 0, 17, 0x0090, 1, 17, 0x0010],
        [14, 0x0005, 17, 0x0010, 0, 17, 0x0090, 0, 17, 0x0020],
        [16, '?', 17, 0x0010, 1, 17, 0x0090, 1, 16, 0x0090],
        [16, 0x0090, 17, 0x0090, 1, 17, 0x0011, 0, 16, 0x0011],
        [16, 0x0090, 17, 0x0011, 0, 10, 0x0000, 0, 10, 0x0000],
    ]

    # Instantiate and elaborate the model

    model = RegisterFile(dtype=16, nregs=32, rd_ports=2, wr_ports=2)
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model, verilator_xinit=test_verilog)
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):
        model.rd_addr[0].value = test_vector[0]
        model.rd_addr[1].value = test_vector[2]
        model.wr_en[0].value = test_vector[4]
        model.wr_addr[0].value = test_vector[5]
        model.wr_data[0].value = test_vector[6]
        model.wr_en[1].value = test_vector[7]
        model.wr_addr[1].value = test_vector[8]
        model.wr_data[1].value = test_vector[9]

    def tv_out(model, test_vector):
        if test_vector[1] != '?':
            assert model.rd_data[0].value == test_vector[1]
        if test_vector[3] != '?':
            assert model.rd_data[1].value == test_vector[3]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #29
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def test_memreq_from_bits( dump_vcd ):

  # Create parameters

  memreq_params = mem_msgs.MemReqParams( 32, 32 )

  # Test vectors

  req = memreq_params.mk_req
  r   = memreq_params.type_read
  w   = memreq_params.type_write

  test_vectors = [
    # bits                                 type addr        len data

    [ req( r, 0x00001000, 1, 0x00000000 ), r,   0x00001000, 1,  0x00000000 ],
    [ req( r, 0x00001004, 2, 0x00000000 ), r,   0x00001004, 2,  0x00000000 ],
    [ req( r, 0x00001008, 3, 0x00000000 ), r,   0x00001008, 3,  0x00000000 ],
    [ req( r, 0x0000100c, 0, 0x00000000 ), r,   0x0000100c, 0,  0x00000000 ],

    [ req( w, 0x00001000, 1, 0x000000ab ), w,   0x00001000, 1,  0x000000ab ],
    [ req( w, 0x00001004, 2, 0x0000abcd ), w,   0x00001004, 2,  0x0000abcd ],
    [ req( w, 0x00001008, 3, 0x00abcdef ), w,   0x00001008, 3,  0x00abcdef ],
    [ req( w, 0x0000100c, 0, 0xabcdef01 ), w,   0x0000100c, 0,  0xabcdef01 ],

  ]

  # Instantiate and elaborate the model

  model = mem_msgs.MemReqFromBits( memreq_params )
  model.vcd_file = dump_vcd
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.bits.value = test_vector[0]

  def tv_out( model, test_vector ):
    assert model.type_.value == test_vector[1]
    assert model.addr.value  == test_vector[2]
    assert model.len_.value  == test_vector[3]
    assert model.data.value  == test_vector[4]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #30
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def test_SRAMBitsComb_rst_1rw(dump_vcd, test_verilog):

    # Test vectors

    test_vectors = [

        #  wen, addr, wdata,    rdata
        [0, 0, 0x000000, 0xa0a0a0],
        [1, 0, 0x000000, '?'],
        [0, 0, 0x000000, 0x000000],
        [1, 0, 0xadbeef, '?'],
        [0, 0, 0x000000, 0xadbeef],
        [1, 0, 0xcdefab, '?'],
        [0, 0, 0x000000, 0xcdefab],
        [1, 0, 0x112233, '?'],
        [0, 0, 0x000000, 0x112233],
        [1, 0, 0xadbeef, '?'],
        [0, 0, 0x000000, 0xadbeef],
        [1, 0, 0xffffff, '?'],
        [0, 0, 0x000000, 0xffffff],
        [1, 12, 0xadbeef, '?'],
        [0, 12, 0xbbcccc, 0xadbeef],
    ]

    # Instantiate and elaborate the model

    model = SRAMBitsComb_rst_1rw(16, 26, reset_value=0xa0a0a0)
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):
        model.wen.value = test_vector[0]
        model.addr.value = test_vector[1]
        model.wdata.value = test_vector[2]

    def tv_out(model, test_vector):
        if test_vector[3] != '?':
            assert model.rdata.value == test_vector[3]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #31
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def test_regfile_1R1W( dump_vcd, test_verilog ):

  # Test vectors

  test_vectors = [
    # rd_addr0  rd_data0  wr_en  wr_addr  wr_data
    [       0,   '?',        0,       0,   0x0000 ],
    [       1,   '?',        0,       1,   0x0008 ],
    # Write followed by Read
    [       3,   '?',        1,       2,   0x0005 ],
    [       2,   0x0005,     0,       2,   0x0000 ],
    # Simultaneous Write and Read
    [       3,   '?',        1,       3,   0x0007 ],
    [       3,   0x0007,     1,       7,   0x0090 ],
    [       7,   0x0090,     1,       3,   0x0007 ],
    # Write to zero
    [       0,   '?',        1,       0,   0x0FFF ],
    [       0,   0x0FFF,     1,       4,   0x0FFF ],
    [       0,   0x0FFF,     0,       4,   0x0BBB ],
    [       0,   0x0FFF,     0,       4,   0x0FFF ],
    [       4,   0x0FFF,     0,       0,   0x0000 ],
  ]

  # Instantiate and elaborate the model

  model = RegisterFile( dtype = 16, nregs = 8, rd_ports = 1 )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model, verilator_xinit=test_verilog )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.rd_addr[0].value = test_vector[0]
    model.wr_en.value      = test_vector[2]
    model.wr_addr.value    = test_vector[3]
    model.wr_data.value    = test_vector[4]

  def tv_out( model, test_vector ):
    if test_vector[1] != '?':
      assert model.rd_data[0].value == test_vector[1]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #32
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def test_regfile_1R1W(dump_vcd, test_verilog):

    # Test vectors

    test_vectors = [
        # rd_addr0  rd_data0  wr_en  wr_addr  wr_data
        [0, '?', 0, 0, 0x0000],
        [1, '?', 0, 1, 0x0008],
        # Write followed by Read
        [3, '?', 1, 2, 0x0005],
        [2, 0x0005, 0, 2, 0x0000],
        # Simultaneous Write and Read
        [3, '?', 1, 3, 0x0007],
        [3, 0x0007, 1, 7, 0x0090],
        [7, 0x0090, 1, 3, 0x0007],
        # Write to zero
        [0, '?', 1, 0, 0x0FFF],
        [0, 0x0FFF, 1, 4, 0x0FFF],
        [0, 0x0FFF, 0, 4, 0x0BBB],
        [0, 0x0FFF, 0, 4, 0x0FFF],
        [4, 0x0FFF, 0, 0, 0x0000],
    ]

    # Instantiate and elaborate the model

    model = RegisterFile(dtype=16, nregs=8, rd_ports=1)
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model, verilator_xinit=test_verilog)
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):
        model.rd_addr[0].value = test_vector[0]
        model.wr_en.value = test_vector[2]
        model.wr_addr.value = test_vector[3]
        model.wr_data.value = test_vector[4]

    def tv_out(model, test_vector):
        if test_vector[1] != '?':
            assert model.rd_data[0].value == test_vector[1]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #33
0
def test_regfile_2R2W( dump_vcd, test_verilog ):

  # Test vectors

  test_vectors = [
    # ---read 0---  ---read 1---  -----write 0-----  -----write 1-----
    # addr    data  addr    data  en  addr     data  en  addr     data
    [    0, 0x0000,    4, 0x0000,  0,    0,  0x0000,  0,    0,  0x0000],
    [    3, 0x0000,    4, 0x0000,  1,    4,  0x0005,  0,    4,  0x0005],
    [    2, 0x0000,    4, 0x0005,  0,    0,  0x0006,  1,    2,  0x0006],
    [    2, 0x0006,    2, 0x0006,  0,    3,  0x0007,  0,    3,  0x0007],
    [    7, 0x0000,    3, 0x0000,  0,    7,  0x0090,  1,    7,  0x0010],
    [    4, 0x0005,    7, 0x0010,  0,    7,  0x0090,  0,    7,  0x0020],
    [    6, 0x0000,    7, 0x0010,  1,    7,  0x0090,  1,    6,  0x0090],
    [    6, 0x0090,    7, 0x0090,  1,    7,  0x0011,  0,    6,  0x0011],
    [    6, 0x0090,    7, 0x0011,  0,    0,  0x0000,  0,    0,  0x0000],
  ]

  # Instantiate and elaborate the model

  model = RegisterFile( dtype=16, nregs=8, rd_ports=2, wr_ports=2 )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.rd_addr[0].value = test_vector[0]
    model.rd_addr[1].value = test_vector[2]
    model.wr_en  [0].value = test_vector[4]
    model.wr_addr[0].value = test_vector[5]
    model.wr_data[0].value = test_vector[6]
    model.wr_en  [1].value = test_vector[7]
    model.wr_addr[1].value = test_vector[8]
    model.wr_data[1].value = test_vector[9]

  def tv_out( model, test_vector ):
    assert model.rd_data[0].value == test_vector[1]
    assert model.rd_data[1].value == test_vector[3]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #34
0
def test_adder( test_verilog, dump_vcd ):

  # Test vectors

  test_vectors = [
    # in0     in1     cin out     cout
    [ 0x0000, 0x0000, 0,  0x0000, 0 ],
    [ 0x0001, 0x0000, 0,  0x0001, 0 ],
    [ 0x0000, 0x0001, 0,  0x0001, 0 ],
    [ 0x0001, 0x0001, 0,  0x0002, 0 ],
    [ 0x0000, 0x0000, 1,  0x0001, 0 ],
    [ 0x0001, 0x0000, 1,  0x0002, 0 ],
    [ 0x0000, 0x0001, 1,  0x0002, 0 ],
    [ 0x0001, 0x0001, 1,  0x0003, 0 ],
    [ 0x000a, 0x0015, 0,  0x001f, 0 ],
    [ 0xfffe, 0x0001, 0,  0xffff, 0 ],
    [ 0xfffe, 0x0001, 1,  0x0000, 1 ],
    [ 0xffff, 0xffff, 1,  0xffff, 1 ]
  ]

  # Instantiate and elaborate the model

  model = Adder(16)
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.in0.value = test_vector[0]
    model.in1.value = test_vector[1]
    model.cin.value = test_vector[2]

  def tv_out( model, test_vector ):
    if test_vector[3] != '?':
      assert model.out.value == test_vector[3]
    if test_vector[4] != '?':
      assert model.cout.value == test_vector[4]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #35
0
def run_test(model, test_vectors):

    # Instantiate and elaborate the model

    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):
        model.reqs.value = test_vector[0]

    def tv_out(model, test_vector):
        assert model.grants == test_vector[1]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #36
0
def run_test( model, test_vectors ):

  # Instantiate and elaborate the model

  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.reqs.value = test_vector[0]

  def tv_out( model, test_vector ):
    assert model.grants == test_vector[1]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #37
0
def test_1entry_skid( dump_vcd, test_verilog ):
  """Single Element Skid Queue."""

  test_vectors = [

    # Enqueue one element and then dequeue it
    # enq.val enq.rdy enq.bits deq.val deq.rdy deq.bits
    [ 1,      1,      0x0001,  1,      1,      0x0001 ],
    [ 1,      0,      0x0006,  1,      0,      0x0001 ],
    [ 1,      1,      0x0006,  1,      1,      0x0006 ],
    [ 0,      1,      0x0008,  1,      1,      0x0006 ],
    [ 0,      1,      0x0008,  0,      0,      0x0006 ],
    [ 1,      1,      0x000a,  1,      1,      0x000a ],
    [ 0,      1,      0x000c,  1,      1,      0x000a ]

  ]

  # Instantiate and elaborate the model

  model = SingleElementSkidQueue( 16 )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):

    model.enq.val.value = test_vector[0]
    model.enq.msg.value = test_vector[2]
    model.deq.rdy.value = test_vector[4]

  def tv_out( model, test_vector ):

    assert model.enq.rdy.value    == test_vector[1]
    assert model.deq.val.value    == test_vector[3]
    if not test_vector[5] == '?':
      assert model.deq.msg.value == test_vector[5]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #38
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def test_GtComparator( test_verilog, dump_vcd ):

  # Test vectors

  test_vectors = [
    # in0     in1     out
    [ 0x0000, 0x0000, 0 ],
    [ 0x0001, 0x0001, 0 ],
    [ 0x0000, 0x0001, 0 ],
    [ 0x000a, 0x000a, 0 ],
    [ 0x000b, 0x000a, 1 ],
    [ 0x000b, 0x000c, 0 ],
    [ 0x007f, 0x007f, 0 ],
    [ 0x0141, 0x0140, 1 ],
    [ 0x0400, 0x0400, 0 ],
    [ 0x7fff, 0x7fff, 0 ],
    [ 0x8000, 0x7fff, 1 ],
    [ 0x8001, 0x8002, 0 ],
    [ 0xffff, 0xffff, 0 ],
  ]

  # Instantiate and elaborate the model

  model = GtComparator(16)
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.in0.value = test_vector[0]
    model.in1.value = test_vector[1]

  def tv_out( model, test_vector ):
    if test_vector[2] != '?':
      assert model.out.value == test_vector[2]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #39
0
def test_regfile_2R1W( dump_vcd, test_verilog ):

  # Test vectors

  test_vectors = [
    # rd_addr0 rd_data0  rd_addr0 rd_data0  wr_en wr_addr wr_data
    [       0,  0x0000,        1,  0x0000,     0,      0,  0x0000 ],
    [       3,  0x0000,        4,  0x0000,     1,      4,  0x0005 ],
    [       3,  0x0000,        4,  0x0005,     1,      2,  0x0006 ],
    [       4,  0x0005,        2,  0x0006,     0,      3,  0x0007 ],
    [       4,  0x0005,        4,  0x0005,     0,      7,  0x0090 ],
    [       4,  0x0005,        7,  0x0000,     0,      7,  0x0090 ],
    [       4,  0x0005,        7,  0x0000,     1,      7,  0x0090 ],
    [       4,  0x0005,        7,  0x0090,     1,      7,  0x0090 ],
  ]

  # Instantiate and elaborate the model

  model = RegisterFile( dtype=16, nregs=8, rd_ports=2 )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.rd_addr[0].value = test_vector[0]
    model.rd_addr[1].value = test_vector[2]
    model.wr_en.value      = test_vector[4]
    model.wr_addr.value    = test_vector[5]
    model.wr_data.value    = test_vector[6]

  def tv_out( model, test_vector ):
    assert model.rd_data[0].value == test_vector[1]
    assert model.rd_data[1].value == test_vector[3]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #40
0
def test_RegEn( dump_vcd, test_verilog ):

  # Test vectors

  test_vectors = [
    # in      en out
    [ 0x0a0a, 0, '?'    ],
    [ 0x0b0b, 1, '?'    ],
    [ 0x0c0c, 0, 0x0b0b ],
    [ 0x0d0d, 1, 0x0b0b ],
    [ 0x0d0d, 0, 0x0d0d ],
    [ 0x0d0d, 1, 0x0d0d ],
    [ 0x0e0e, 1, 0x0d0d ],
    [ 0x0e0e, 0, 0x0e0e ],
    [ 0x0f0f, 0, 0x0e0e ],
    [ 0x0e0e, 0, 0x0e0e ],
    [ 0x0e0e, 0, 0x0e0e ],
  ]

  # Instantiate and elaborate the model

  model = RegEn(16)
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.in_.value = test_vector[0]
    model.en.value  = test_vector[1]

  def tv_out( model, test_vector ):
    if test_vector[2] != '?':
      assert model.out.value == test_vector[2]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #41
0
def test_RegEn(dump_vcd, test_verilog):

    # Test vectors

    test_vectors = [
        # in      en out
        [0x0a0a, 0, '?'],
        [0x0b0b, 1, '?'],
        [0x0c0c, 0, 0x0b0b],
        [0x0d0d, 1, 0x0b0b],
        [0x0d0d, 0, 0x0d0d],
        [0x0d0d, 1, 0x0d0d],
        [0x0e0e, 1, 0x0d0d],
        [0x0e0e, 0, 0x0e0e],
        [0x0f0f, 0, 0x0e0e],
        [0x0e0e, 0, 0x0e0e],
        [0x0e0e, 0, 0x0e0e],
    ]

    # Instantiate and elaborate the model

    model = RegEn(16)
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):
        model.in_.value = test_vector[0]
        model.en.value = test_vector[1]

    def tv_out(model, test_vector):
        if test_vector[2] != '?':
            assert model.out.value == test_vector[2]

    # Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #42
0
def test_RightLogicalShifter( test_verilog, dump_vcd ):

  # Test vectors

  test_vectors = [
    # in        shamnt  out
    [ 0b100000, 1, 0b010000 ],
    [ 0b000000, 0, 0b000000 ],
    [ 0b100000, 0, 0b100000 ],
    [ 0b100000, 2, 0b001000 ],
    [ 0b100000, 3, 0b000100 ],
    [ 0b100000, 4, 0b000010 ],
    [ 0b101010, 1, 0b010101 ],
    [ 0b101010, 2, 0b001010 ],
    [ 0b111111, 3, 0b000111 ],
    [ 0b111111, 6, 0b000000 ],
  ]

  # Instantiate and elaborate the model

  model = RightLogicalShifter(6,3)
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.in_.value   = test_vector[0]
    model.shamt.value = test_vector[1]

  def tv_out( model, test_vector ):
    if test_vector[2] != '?':
      assert model.out.value == test_vector[2]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
def test_MergerPRTL( test_verilog, dump_vcd ):

  test_vectors = [
    # in0   in1   in2   in3   in4   in5   in6   in7   in8   in9   idx
    [ 0x96, 0x42, 0x03, 0x23, 0x89, 0x55, 0x78, 0x06, 0x09, 0x32, 0x2 ],
    [ 0x05, 0x77, 0x32, 0x96, 0x45, 0x23, 0x89, 0x09, 0x09, 0x01, 0x9 ],
    [ 0x00, 0x00, 0x03, 0x23, 0x89, 0x35, 0x43, 0x06, 0x09, 0x32, 0x0 ],
  ]

#  random.seed(0xdeadbeef)
#  test_vectors = []
#  for k in xrange( 50 ):
#    inputs = []
#    min_value = 0x96
#    min_idx   = 0
#    for i in xrange( 10 ):
#      input_value = random.randint( 0, 0x96 )
#      if ( input_value < min_value ):
#        min_value = input_value
#        min_idx   = i
#      inputs.append( input_value )
#    inputs.append( min_idx )
#    test_vectors.extend( inputs )

  model = MergerPRTL( 10, 8 )
  model.vcd_file = dump_vcd
  if test_verilog:
     model = TranslationTool( model )
  model.elaborate()

  def tv_in( model, test_vector ):
    for i in xrange( 10 ):
      model.in_[i].value = test_vector[i]

  def tv_out( model, test_vector ):
    if test_vector[10] != '?':
      assert model.out.value == test_vector[10]

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
def test_truncationStep(test_verilog, dump_vcd):

    test_vectors = [
        # msg_in            , lod_in      , msg_out , trunc_out
        [0b0111111111111111, 0b0000001110, 0b111111, 0x009],
        [0b0000001110000000, 0b0000001001, 0b111001, 0x004],
        [0b0000001110010000, 0b0000001001, 0b111001, 0x004],
        #[ 0b0111111111111111, 0b0000001110, 0b111111, 0x009 ],
        #[ 0b0000001110000000, 0b0000000111, 0b110000, 0x001 ],
        # [ 0b0000010000000000, 0b0000001010, 0b000000, 0x004 ],
        # [ 0b0000000000000000, 0b0000010000, 0b000000, 0x00a ],
        # [ 0b0000000000001000, 0b0000000111, 0b000100, 0x001 ],
        # [ 0b0000110000000010, 0b0000001001, 0b000000, 0x003 ],
    ]

    # Instantiate and elaborate the model

    model = truncationStep(16, 6)
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    # Define functions mapping the test vector to ports in model

    def tv_in(model, test_vector):
        model.msg_in.value = test_vector[0]
        model.lod_in.value = test_vector[1]

    def tv_out(model, test_vector):
        assert model.msg_out.value == test_vector[2]
        assert model.trunc_out.value == test_vector[3]

    def line_trace(s):
        return s.model.line_trace()

# Run the test

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #45
0
def test_regfile_1R1Wconst0( dump_vcd, test_verilog ):

  # Test vectors

  test_vectors = [
    # rd_addr0  rd_data0  wr_en  wr_addr  wr_data
    [       0,   0x0000,     0,       0,   0x0000 ],
    [       0,   0x0000,     1,       0,   0x0005 ],
    [       0,   0x0000,     0,       0,   0x0000 ],
    [       1,   '?',        0,       1,   0x0000 ],
    [       1,   '?',        1,       1,   0x0015 ],
    [       1,   0x0015,     0,       1,   0x0000 ],
    [       1,   0x0015,     0,       1,   0x0000 ],
  ]

  # Instantiate and elaborate the model

  model = RegisterFile( dtype = 16, nregs = 8, rd_ports = 1, const_zero=True )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model, verilator_xinit=test_verilog )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.rd_addr[0].value = test_vector[0]
    model.wr_en.value      = test_vector[2]
    model.wr_addr.value    = test_vector[3]
    model.wr_data.value    = test_vector[4]

  def tv_out( model, test_vector ):
    if test_vector[1] != '?':
      assert model.rd_data[0].value == test_vector[1]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
def  test_truncationStep( test_verilog , dump_vcd ):

  test_vectors = [
     # msg_in            , lod_in      , msg_out , trunc_out
     [ 0b0111111111111111, 0b0000001110, 0b111111, 0x009 ],
     [ 0b0000001110000000, 0b0000001001, 0b111001, 0x004 ],
     [ 0b0000001110010000, 0b0000001001, 0b111001, 0x004 ],
     #[ 0b0111111111111111, 0b0000001110, 0b111111, 0x009 ],
     #[ 0b0000001110000000, 0b0000000111, 0b110000, 0x001 ],
     # [ 0b0000010000000000, 0b0000001010, 0b000000, 0x004 ],
     # [ 0b0000000000000000, 0b0000010000, 0b000000, 0x00a ],
     # [ 0b0000000000001000, 0b0000000111, 0b000100, 0x001 ],
     # [ 0b0000110000000010, 0b0000001001, 0b000000, 0x003 ],
  ]

 # Instantiate and elaborate the model

  model = truncationStep( 16, 6 )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

 # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.msg_in.value    = test_vector[0]
    model.lod_in.value    = test_vector[1]
  def tv_out( model, test_vector ):
    assert model.msg_out.value   == test_vector[2]
    assert model.trunc_out.value == test_vector[3]

  def line_trace( s ):
    return s.model.line_trace()

 # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
def test_ReducerPRTL(test_verilog, dump_vcd):

    test_vectors = [
        # in0   in1   in2   rst  out
        [0x00, 0x00, 0x00, 0x1, 0x96],
        [0x32, 0x31, 0x30, 0x0, 0x96],
        [0x29, 0x28, 0x29, 0x0, 0x94],
        [0x27, 0x29, 0x28, 0x0, 0x8a],
        [0x25, 0x23, 0x24, 0x0, 0x7f],
        [0x30, 0x29, 0x32, 0x0, 0x72],
        [0x07, 0x03, 0x03, 0x0, 0x72],
        [0x28, 0x26, 0x25, 0x0, 0x4d],
        [0x00, 0x00, 0x00, 0x0, 0x4b],
        [0x32, 0x32, 0x32, 0x0, 0x26],
        [0x30, 0x31, 0x31, 0x0, 0x26],
        [0x30, 0x31, 0x31, 0x1, 0x26],
        [0x02, 0x01, 0x05, 0x0, 0x96],
        [0x30, 0x01, 0x17, 0x0, 0x65],
        [0x30, 0x01, 0x17, 0x0, 0x34],
    ]

    model = ReducerPRTL(3, 6, 3, 50)
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(model)
    model.elaborate()

    def tv_in(model, test_vector):
        model.in_[0].value = test_vector[0]
        model.in_[1].value = test_vector[1]
        model.in_[2].value = test_vector[2]
        model.rst.value = test_vector[3]

    def tv_out(model, test_vector):
        if test_vector[4] != '?':
            assert model.out.value == test_vector[4]

    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()
Beispiel #48
0
def run_test_unsign_unit( test_verilog, dump_vcd, nbits, test_vectors ):

  # Instantiate and elaborate the model

  model = UnsignUnit( nbits )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define functions mapping the test vector to ports in model

  def tv_in( model, test_vector ):
    model.in_.value = test_vector[0]

  def tv_out( model, test_vector ):
    if test_vector[1] != '?':
      assert model.out.value == test_vector[1]

  # Run the test

  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )
  sim.run_test()
Beispiel #49
0
def test_Demux( dump_vcd, test_verilog ):

  nports     = 2
  data_nbits = 16

  # Define test input and output functions

  def tv_in( model, test_vector ):
    model.sel.value = test_vector[0]
    model.in_.value = test_vector[1]

  def tv_out( model, test_vector ):
    assert model.out[0] == test_vector[2]
    assert model.out[1] == test_vector[3]

  # Select and elaborate the model under test

  model = Demux( nports, dtype = data_nbits )
  model.vcd_file = dump_vcd
  if test_verilog:
    model = TranslationTool( model )
  model.elaborate()

  # Define the test vectors
  test_vectors = [
    # sel  in_      out[0]  out[1]
    [ 0b00, 0x3333, 0x0000, 0x0000 ],
    [ 0b01, 0x1111, 0x1111, 0x0000 ],
    [ 0b10, 0x2222, 0x0000, 0x2222 ],
    [ 0b00, 0x1111, 0x0000, 0x0000 ],
  ]

  # Create the simulator and configure it
  sim = TestVectorSimulator( model, test_vectors, tv_in, tv_out )

  # Run the simulator
  sim.run_test()