def __init__(self, configFile, trigger, aldo, l1, prescale, freq, phase,
rawDataDirectory):
#-----------------------------
# load configuration from file
self.mask = config.LOAD_ALL
# if args.mode != "mixed":
# mask ^= config.LOAD_QDCMODE_MAP
self.mask ^= config.LOAD_QDCMODE_MAP
self.configFile = configFile
self.systemConfig = config.ConfigFromFile(configFile,
loadMask=self.mask)
self.daqd = daqd.Connection()
self.daqd.initializeSystem()
self.asicsConfig = self.daqd.getAsicsConfig()
self.activeAsics = self.daqd.getActiveAsics()
self.rawDataDirectory = rawDataDirectory
#--------------
self.trigger = trigger
self.l1 = l1
self.prescale = prescale
self.phase = phase
#------------------------------------------------
# enable required channels (all if not specified)
for portID, slaveID, chipID in self.activeAsics:
ac = self.asicsConfig[(portID, slaveID, chipID)]
for channelID in range(32):
cc = ac.channelConfig[channelID]
cc.setValue("c_tgr_main", 0b11)
for portID, slaveID, chipID in self.activeAsics:
ac = self.asicsConfig[(portID, slaveID, chipID)]
for channelID in range(32):
cc = ac.channelConfig[channelID]
cc.setValue("c_tgr_main", 0b00)
if aldo:
self.aldo = aldo
self.hvdac_config = self.daqd.get_hvdac_config()
for portID, slaveID, railID in self.hvdac_config.keys():
# set 48 V as ALDO input bias (should not exceed this value)
self.hvdac_config[(
portID, slaveID,
railID)] = self.systemConfig.mapBiasChannelVoltageToDAC(
(portID, slaveID, railID), 48)
self.daqd.set_hvdac_config(self.hvdac_config)
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
from petsys import daqd
from time import sleep
from sys import argv
daqd = daqd.Connection()
f = open(argv[1])
print("Configuring SI53xx clock filter")
for line in f:
if line[0] == '#': continue
line = line.rstrip('\r\n')
regNum, regValue = line.split(', ')
regNum = int(regNum)
regValue = '0x' + regValue[:-1]
regValue = int(regValue, base=16)
print("Register %02x set to %02x" % (regNum, regValue))
daqd.setSI53xxRegister(regNum, regValue)
print("Done")