def connect_from(self, other: PinOut):
if self._source is None:
self._source = other
if isinstance(other.parent, Alias):
self._assignment = other.parent
return
if self.alias is None:
self._source = other
else:
other.bind(self.alias)
def _pop_out(self, pin: PinOut = None):
if pin is None:
pin = self._outputs.pop()
else:
self._outputs.remove(pin)
delay = self._after[pin.name]
wire = pin.connection
pin.unbind()
del self._after[pin.name]
return wire, delay
def __init__(self, parent: Module, source: Wire, delay: int):
super().__init__("{}_v_buffer".format(source.name), parent)
buf_out = parent.create_wire()
org_post = set(source.post)
for p in org_post:
p.unbind()
p.bind(buf_out)
self._input = PinIn("v_bfr_in", self, source)
self._output = PinOut("v_bfr_out", self, buf_out)
self._delay = delay
class Alias(UnitBlock):
def __init__(self, name: str, parent: (Block, Device), org: Net,
alias: Net):
super().__init__(name, parent)
self._input = PinIn("alias", self, alias)
self._output = PinOut("org", self, org)
def unbind(self):
self._input.unbind()
self._output.unbind()
@property
def wire_in(self):
return self._input.connection
@property
def wire_out(self):
return self._output.connection
@property
def input_pins(self):
return [self._input]
@property
def output_pins(self):
return [self._output]
@property
def gate_count(self):
return 0
def get_delay(self, other=None):
return 0
def truth_table(self, other):
return 1
def to_verilog(self):
return "\tassign {} = {};".format(self._output.connection.name,
self._input.connection.name)
def __init__(self, name: str, parent: Device, model: Device,
mapping: Dict[str, Net]):
super().__init__(name, parent)
self._model = model
self._pins = dict()
self._inputs = list()
self._outputs = list()
for x in model.input_labels:
pin = PinIn(x, self, mapping.get(x))
self._pins[x] = pin
self._inputs.append(pin)
for x in model.output_labels:
pin = PinOut(x, self, mapping.get(x))
self._pins[x] = pin
self._outputs.append(pin)
def _add_wire(self, other: Wire, delay: int = 0):
split_out_pin = PinOut("v_fanout_out_{}".format(str(self._tracker)),
self, other)
self._outputs.add(split_out_pin)
self._tracker = self._tracker + 1
self._after[split_out_pin.name] = delay
class VirtualBuffer(LogicBlock):
def __init__(self, parent: Module, source: Wire, delay: int):
super().__init__("{}_v_buffer".format(source.name), parent)
buf_out = parent.create_wire()
org_post = set(source.post)
for p in org_post:
p.unbind()
p.bind(buf_out)
self._input = PinIn("v_bfr_in", self, source)
self._output = PinOut("v_bfr_out", self, buf_out)
self._delay = delay
@property
def input_pins(self):
return [self._input]
@property
def output_pins(self):
return {self._output}
def get_delay(self, other=None):
return self._delay
def decrease(self, margin: int = 1):
if self._delay == 0:
print("delay is already 0")
return
self._delay = self._delay - margin
if self._delay == 0:
source = self._input.connection
self._input.unbind()
to = self._output.connection
self._output.unbind()
to.post.pop().bind(source)
self.parent.remove_net(to.name)
def increase(self, margin: int = 1):
self._delay = self._delay + margin
@property
def gate_count(self):
return 2 * self._delay
def to_verilog(self):
return "Black box"
def cell_mapping(self, library):
if self._delay == 0:
return
buffer_model = library.get_buffer()
input_wire = self._input.connection
self._input.unbind()
for i in range(self._delay - 1):
wire_down = self.parent.create_wire()
self.parent.register_instance(
buffer_model.instantiate("{}_bfr_after".format(wire_down.name),
self.parent, [input_wire, wire_down]))
input_wire = wire_down
output_wire = self._output.connection
self._output.unbind()
self.parent.register_instance(
buffer_model.instantiate("{}_bfr_after".format(output_wire.name),
self.parent, [input_wire, output_wire]))
def __init__(self, name: str, parent: (Block, Device), org: Net,
alias: Net):
super().__init__(name, parent)
self._input = PinIn("alias", self, alias)
self._output = PinOut("org", self, org)