def func(a, b, c, d, e, f, g, h): v10 = arg8_mul(a, b, c, d, e, f, g, h) clkfence() v11 = arg8_mul(h, a, b, c, d, e, f, g) clkfence() return v10 + v11
def tx_char(self, char_c): wait_value(0, self.tx_busy) self.tx_data.wr(char_c) self.tx_start.wr(1) clkfence() wait_value(1, self.tx_busy) self.tx_start.wr(0)
def main(self): while polyphony.is_worker_running(): self.convst_n.wr(1) self.cs_n.wr(1) self.data_ready.wr(0) clkfence() self.convst_n.wr(0) clksleep(CONVST_PULSE_CYCLE) self.convst_n.wr(1) clksleep(CONVERSION_CYCLE) # starting ADC I/O self.cs_n.wr(0) sdo_tmp = 0 clksleep(1) for i in range(16): self.sclk.wr(0) sdi_tmp = 1 if (self.din() & (1 << (15 - i))) else 0 self.sdi.wr(sdi_tmp) clksleep(1) self.sclk.wr(1) sdo_tmp = sdo_tmp << 1 | self.sdo.rd() self.sclk.wr(0) self.dout.wr(sdo_tmp & 0x0fff) self.chout.wr((sdo_tmp & 0x7000) >> 12) self.cs_n.wr(1) clkfence() self.data_ready.wr(1)
def test(m): m.idata.wr(2) m.idata.wr(3) m.idata.wr(4) clkfence() assert m.odata.rd() == 256 assert m.odata.rd() == 6561 assert m.odata.rd() == 65536
def pow(idata, ivalid, odata, ovalid): while is_worker_running(): wait_rising(ivalid) d = idata.rd() odata.wr(d * d) clkfence() ovalid.wr(True) ovalid.wr(False)
def test(p04): with rule(scheduling='parallel'): p04.i1.wr(2) p04.i2.wr(3) p04.i3.wr(4) clkfence() assert p04.o1() == 4 assert p04.o2() == 9 assert p04.o3() == 16
def test(m): m.i_port.wr(99) for i in range(10): m.i_port.wr(i) if i == 8: #clksleep(2) clkfence() v = m.o_port.rd() print(v)
def test(p05): wait_value(True, p05.start) p05.in0(2) p05.in_valid(True) print('wait out_valid') wait_value(True, p05.out_valid) assert p05.out0() == 4 clkfence() print(p05.out0())
def main(self): self.start(True) while is_worker_running(): self.out_valid(False) wait_value(True, self.in_valid) i = self.in0() self.out0(i * i) clkfence() self.out_valid(True) break
def test(p03): p03.i1.wr(2) p03.i2.wr(2) clkfence() assert p03.o1.rd() == 2 + 1 + 2 + 3 assert p03.o2.rd() == 2 + 1 + 2 + 3 clksleep(10) p03.i1.wr(3) p03.i2.wr(3) clkfence() assert p03.o1.rd() == 3 + 1 + 2 + 3 assert p03.o2.rd() == 3 + 1 + 2 + 3
def test(p01): # wait to ensure the test starts after the worker is running wait_value(1, p01.start) p01.in0(2) p01.in_valid(1) print('wait out_valid') wait_value(1, p01.out_valid) assert p01.out0() == 4 clkfence() print(p01.out0())
def test(spic): f = 0 for i in range(12): wait_falling(spic.sclk) spic.miso.wr(f) f = 1 - f clkfence() clksleep(2) spic.miso.wr(0) data = spic.data16.rd() print("data0:", data)
def main(self): self.start(1) while is_worker_running(): self.out_valid(0) # We have to wait the input data ... wait_value(1, self.in_valid) i = self.in0() self.out0(i * i) # clkfence() function guarantees that the writing to out_valid is executed in a next cycle clkfence() self.out_valid(1) break
def test(spi_master): for i in range(7): wait_value(1, spi_master.sclk) f = 0 for i in range(8): wait_value(0, spi_master.sclk) clkfence() spi_master.miso.wr(f) f = 1 - f clksleep(1) spi_master.miso.wr(0) data = spi_master.data8.rd() print("data0:", data)
def sin_wave_worker(self, o_port, o_pulse): i = 0 f = 0 while polyphony.is_worker_running(): v = table[i] clkfence() o_port(v) o_pulse(1) o_pulse(0) #print(i, ":", v) if i == (SIN_CYCLE-1): i = 0 else: i = i + 1
def test(m): for i in range(10): rv = 0 shift_n = 0 #b = [0] * 32 m.i_start.wr(1) m.i_start.wr(0) clkfence() for i in range(32): #b[i] = m.o_data.rd() bb: bit32 = m.o_data.rd() rv += (bb << shift_n) print(bb, rv) shift_n = shift_n + 1 print("xor shift:", rv) clksleep(100)
def test_8_2(sorter): sorter.i0.wr(6) sorter.i1.wr(4) sorter.i2.wr(8) sorter.i3.wr(2) sorter.i4.wr(3) sorter.i5.wr(5) sorter.i6.wr(7) sorter.i7.wr(1) clkfence() assert 1 == sorter.o0.rd() assert 2 == sorter.o1.rd() assert 3 == sorter.o2.rd() assert 4 == sorter.o3.rd() assert 5 == sorter.o4.rd() assert 6 == sorter.o5.rd() assert 7 == sorter.o6.rd() assert 8 == sorter.o7.rd()
def read_data(self): self.cs_n.wr(0) clksleep(1) data: uint16 = 0 self.sclk.wr(0) for i in range(16): data <<= 1 clksleep(1) self.sclk.wr(1) clksleep(1) bit1 = self.miso.rd() & 1 clkfence() self.sclk.wr(0) data |= bit1 clksleep(1) self.cs_n.wr(1) return data
def read_data(self, addr): self.cs_n.wr(0) self.sclk.wr(0) clksleep(1) self.set_addr(1, 0, addr) data = 0 for i in range(8): data <<= 1 clksleep(1) self.sclk.wr(1) clksleep(1) bit1 = self.miso.rd() & 1 clkfence() self.sclk.wr(0) data |= bit1 clksleep(1) self.cs_n.wr(1) return data
def write_data(self, addr: uint8, data: uint8): self.rw(1) self.addr(addr) self.data_out(data) clkfence() self.stb(1) clkfence() wait_value(1, self.ack) clkfence() self.stb(0)
def read_data(self, addr: uint8): data: uint8 = 0 self.rw(0) self.addr(addr) clkfence() self.stb(1) clkfence() wait_value(1, self.ack) data = self.data_in.rd() clkfence() self.stb(0) return data
def write_data(self, data): self.cs_n.wr(0) clkfence() for i in range(8): clkfence() self.sclk.wr(0) bit1 = (data >> (7 - i)) & 1 self.mosi.wr(bit1) clksleep(1) self.sclk.wr(1) self.sclk.wr(0) clkfence()
def main(self): while polyphony.is_worker_running(): self.convst_n.wr(1) self.cs_n.wr(1) self.data_ready.wr(0) clkfence() self.convst_n.wr(0) clksleep(10) self.convst_n.wr(1) clksleep(40) # starting ADC I/O self.cs_n.wr(0) sdo_tmp = 0 clksleep(1) for i in range(16): self.sclk.wr(0) clkfence() sdi_tmp = 1 if (self.din() & (1 << (15 - i))) else 0 self.sdi.wr(sdi_tmp) clksleep(1) self.sclk.wr(1) clkfence() sdo_d = self.sdo.rd() sdo_tmp = sdo_tmp << 1 | sdo_d #print('sdo read!', i, sdo_d) self.sclk.wr(0) self.dout.wr(sdo_tmp & 0x0fff) self.chout.wr((sdo_tmp & 0x7000) >> 12) self.cs_n.wr(1) clkfence() self.data_ready.wr(1)
def read_data(self): #self.cs_n.wr(0) #clksleep(1) data: uint8 = 0 #self.sclk.wr(0) for i in range(8): data <<= 1 clkfence() self.sclk.wr(1) clkfence() bit1 = self.miso.rd() & 1 clkfence() self.sclk.wr(0) data |= bit1 clksleep(1) self.cs_n.wr(1) return data
def test(p02): p02.i.wr(2) clkfence() assert p02.o() == 4
def worker(self): self.sbus_reset.wr(1) clksleep(8) self.sbus_reset.wr(0) self.sbus_ipload(1) self.debug.wr(4) self._wait() wait_value(1, self.sbus_ipdone) self.sbus_ipload(0) self.debug.wr(0) clksleep(8) self.write_data(0x07, 0x18) self.write_data(0x0F, 2) self.write_data(0x09, 0x80) self.write_data(0x0A, 0xC0) self.write_data(0x0B, 0x02) self.write_data(0x0A, 0xC0) self.write_data(0x0D, 0x35) self.debug.wr(4) irq_status = 0 while True: irq_status = self.read_data(0x06) irq_trdy = (irq_status >> 4) & 1 if irq_trdy == 1: self.write_data(0x06, 0x10) break #self.debug.wr((irq_status >> 3) & 3) while True: irq_status = self.read_data(0x06) irq_rrdy = (irq_status >> 3) & 1 if irq_rrdy == 1: self.write_data(0x06, irq_status) break # self.write_data(0x0D, 0x5A) # self.debug.wr((irq_status >> 3) & 3) # #self.debug.wr(1) # # while True: # irq_status = self.read_data(0x06) # irq_trdy = (irq_status >> 4) & 1 # if irq_trdy == 1 : # self.write_data(0x06, 0x10) # #break # irq_rrdy = (irq_status >> 3) & 1 # if irq_rrdy == 1 : # self.write_data(0x06, 0x08) # break # # self.debug.wr(1) #self._wait() #while True: # irq_status = self.read_data(0x06) # if irq_status == 0 : # break # self._wait() # self.write_data(0x06, irq_status) # self._wait() #self.debug.wr((irq_status >> 3) & 2) #self._wait() self.write_data(0x0A, 0x80) #---------------------------------------------------- self.write_data(0x0A, 0xC0) self.write_data(0x0D, 0x12) self.debug.wr(7) irq_status = 0 while True: irq_status = self.read_data(0x06) irq_trdy = (irq_status >> 4) & 1 if irq_trdy == 1: self.write_data(0x0D, 0xAA) self.write_data(0x06, 0x10) break #self.debug.wr((irq_status >> 3) & 2) while True: irq_status = self.read_data(0x06) irq_rrdy = (irq_status >> 3) & 1 if irq_rrdy == 1: self.write_data(0x06, 0x08) break #self.debug.wr((irq_status >> 3) & 2) while True: irq_status = self.read_data(0x06) irq_rrdy = (irq_status >> 3) & 1 if irq_rrdy == 1: self.write_data(0x06, 0x08) break self.write_data(0x0A, 0x80) clkfence() clksleep(10) #self.debug.wr(4) while polyphony.is_worker_running(): data16 = self.read_spi_data16() print(data16) self._wait()