def test_connection_box(tmpdir):
io = Iopad()
block = IOBlock('mock_block', io, 4)
glb = Global('clk', is_clock=True)
sgmts = [Segment('L1', 4, 1), Segment('L2', 1, 2)]
lib = SwitchLibrary()
gen = VerilogGenerator()
# 1. add some ports
block.create_global(glb)
block.create_input('outpad', 1)
block.create_output('inpad', 1)
# 2. create a connection box
cbox = ConnectionBox('mock_cbox', Dimension.x)
# 3. populate and generate connections
populate_connection_box(cbox, sgmts, block, Orientation.south)
generate_fc(cbox, sgmts, block, Orientation.south,
BlockFCValue(BlockPortFCValue(0.5), BlockPortFCValue(1.0)))
# 2.3 switchify!
switchify(lib, cbox)
# 4. generate files
gen.generate_module(tmpdir.join(cbox.name + '.v').open(OpenMode.wb), cbox)
def test_rtlgen(tmpdir):
gen = VerilogGenerator()
lib = SwitchLibrary()
ff = Flipflop()
lut = LUT(4)
clk = Global('clk', is_clock=True)
# 1. cluster
cluster = Cluster('mock_cluster')
# 1.1 add some ports
cluster.create_clock('clk')
cluster.create_input('I', 4)
cluster.create_output('O', 1)
# 1.2 add some instances
ffinst = cluster.instantiate(ff, 'ff')
lutinst = cluster.instantiate(lut, 'lut')
# 1.3 connect stuff
cluster.connect(cluster.ports['I'], lutinst.pins['in'])
cluster.connect(cluster.ports['clk'], ffinst.pins['clk'])
cluster.connect(lutinst.pins['out'], ffinst.pins['D'])
cluster.connect(lutinst.pins['out'], cluster.ports['O'])
cluster.connect(ffinst.pins['Q'], cluster.ports['O'])
# 1.4 switchify!
switchify(lib, cluster)
physicalify(cluster)
# 2. block
block = LogicBlock('mock_block')
# 2.1 add some ports
block.create_global(clk, Orientation.south)
block.create_input('I', 8, Orientation.west)
block.create_output('O', 2, Orientation.east)
# 2.2 add some instances and connections
for i in range(2):
clst = block.instantiate(cluster, 'clst' + str(i))
block.connect(block.ports['clk'], clst.pins['clk'])
block.connect(block.ports['I'][4 * i:4 * (i + 1)], clst.pins['I'])
block.connect(clst.pins['O'], block.ports['O'][i])
# 2.3 switchify!
switchify(lib, block)
physicalify(block)
# 4. generate files
for module in chain(itervalues(lib.switches),
iter((ff, lut, cluster, block))):
gen.generate_module(
tmpdir.join(module.name + '.v').open(OpenMode.wb), module)
def test_io_leaf_array(tmpdir):
io = Iopad()
block = IOBlock('mock_block', io, 4)
glb = Global('clk', is_clock = True)
sgmts = [Segment('L1', 4, 1)]
lib = Library()
gen = VerilogGenerator()
fc = BlockFCValue(BlockPortFCValue(0.5), BlockPortFCValue(1.0))
# 1. add some ports
block.create_global(glb)
block.create_input('outpad', 1)
block.create_output('inpad', 1)
# 2. create tile
tile = Tile('mock_tile', block, Orientation.west)
# 3. cboxify
cboxify(lib, tile, sgmts, fc, Orientation.east)
# 4. populate and generate connections
for (position, orientation), cbox_inst in iteritems(tile.cbox_instances):
populate_connection_box(cbox_inst.model, sgmts, tile.block, orientation, position)
generate_fc(cbox_inst.model, sgmts, tile.block, orientation, fc, position)
# 5. netify
netify_tile(tile)
# 6. create array
array = Array('mock_array', tile.width, tile.height, coverage = ChannelCoverage(north = True, east = True))
# 7. place tile
array.instantiate_element(tile, (0, 0))
# 8. sboxify
sboxify(lib, array)
# 9. populate and generate connections
for env, sbox in iteritems(lib.sboxes):
populate_switch_box(sbox, sgmts, env)
generate_wilton(sbox, sgmts, cycle_free = True)
# 10. netify
netify_array(array)
# 11. switchify!
for box in chain(itervalues(lib.cboxes), itervalues(lib.sboxes)):
switchify(lib, box)
# 12. generate files
for module in chain(itervalues(lib.switches), itervalues(lib.sboxes), iter((array, ))):
gen.generate_module(tmpdir.join(module.name + '.v').open(OpenMode.wb), module)
def run(self, context):
hierarchy = analyze_hierarchy(context)
modules = list(chain(itervalues(context.clusters),
itervalues(context.io_blocks),
itervalues(context.logic_blocks),
itervalues(context.connection_boxes),
itervalues(context.switch_boxes)))
for module in modules:
switchify(context.switch_library, module)
for inst in itervalues(module.all_instances):
if inst.module_class.is_switch:
hierarchy.setdefault(inst.model.name, {})
hierarchy[module.name][inst.model.name] = inst.model
def test_logic_tile(tmpdir):
clk = Global('clk', is_clock=True)
sgmts = [Segment('L1', 4, 1), Segment('L2', 1, 2)]
lib = Library()
gen = VerilogGenerator()
block = LogicBlock('mock_block', 1, 3)
fc = BlockFCValue(BlockPortFCValue(0.5), BlockPortFCValue(1.0), {
"cin": BlockPortFCValue(0),
"cout": BlockPortFCValue(0)
})
# 1. add some ports
block.create_global(clk, Orientation.south, position=(0, 0))
block.create_input('addr', 10, Orientation.west, (0, 0))
block.create_input('din', 8, Orientation.west, (0, 1))
block.create_input('we', 1, Orientation.west, (0, 2))
block.create_output('dout', 8, Orientation.east, (0, 0))
cin = block.create_input('cin', 1, Orientation.south, position=(0, 0))
cout = block.create_output('cout', 1, Orientation.north, position=(0, 2))
# 2. direct tunnels
directs = [DirectTunnel('carrychain', cout, cin, (0, -3))]
# 3. create tile
tile = Tile('mock_tile', block)
# 4. cboxify
cboxify(lib, tile, sgmts, fc)
# 5. populate and generate connections
for (position, orientation), cbox_inst in iteritems(tile.cbox_instances):
populate_connection_box(
cbox_inst.model, sgmts, tile.block, orientation, position,
orientation.case((0, 0), (0, 0), (0, -1), (-1, 0)))
generate_fc(cbox_inst.model, sgmts, tile.block, orientation,
fc, position,
orientation.case((0, 0), (0, 0), (0, -1), (-1, 0)))
switchify(lib, cbox_inst.model)
# 7. netify
netify_tile(tile, directs)
# 8. generate files
for module in chain(itervalues(lib.switches), itervalues(lib.cboxes),
iter((tile, ))):
gen.generate_module(
tmpdir.join(module.name + '.v').open(OpenMode.wb), module)
def test_switch_box(tmpdir):
sgmts = [Segment('L1', 4, 1), Segment('L2', 1, 2)]
lib = SwitchLibrary()
gen = VerilogGenerator()
# 1. create a switch box
sbox = SwitchBox('mock_sbox')
# 2. populate and generate connections
populate_switch_box(sbox, sgmts)
generate_wilton(sbox, sgmts, cycle_free=True)
# 2.3 switchify!
switchify(lib, sbox)
# 4. generate files
gen.generate_module(tmpdir.join(sbox.name + '.v').open(OpenMode.wb), sbox)
def test_io_tile(tmpdir):
io = Iopad()
block = IOBlock('mock_block', io, 4)
glb = Global('clk', is_clock=True)
sgmts = [Segment('L1', 4, 1), Segment('L2', 1, 2)]
lib = Library()
gen = VerilogGenerator()
fc = BlockFCValue(BlockPortFCValue(0.5), BlockPortFCValue(1.0))
# 1. add some ports
block.create_global(glb)
block.create_input('outpad', 1)
block.create_output('inpad', 1)
# 2. create tile
tile = Tile('mock_tile', block, Orientation.west)
# 3. cboxify
cboxify(lib, tile, sgmts, fc, Orientation.east)
# 4. populate and generate connections
for (position, orientation), cbox_inst in iteritems(tile.cbox_instances):
populate_connection_box(cbox_inst.model, sgmts, tile.block,
orientation, position)
generate_fc(cbox_inst.model, sgmts, tile.block, orientation, fc,
position)
switchify(lib, cbox_inst.model)
# 5 switchify!
switchify(lib, block)
# 6. netify
netify_tile(tile)
# 7. generate files
for module in chain(itervalues(lib.switches), itervalues(lib.cboxes),
iter((tile, ))):
gen.generate_module(
tmpdir.join(module.name + '.v').open(OpenMode.wb), module)
def test_complex_array(tmpdir):
io = Iopad()
clk = Global('clk', is_clock = True)
clk.bind((0, 1), 0)
sgmts = [Segment('L1', 4, 1), Segment('L2', 1, 2)]
lib = Library()
gen = VerilogGenerator()
# 1. create IOB
iob = IOBlock('mock_iob', io, 4)
iob.create_global(clk)
iob.create_input('outpad', 1)
iob.create_output('inpad', 1)
# 2. create IOB tiles
iob_tiles = {}
io_fc = BlockFCValue(BlockPortFCValue(0.5), BlockPortFCValue(1.0))
for ori in Orientation:
if ori.is_auto:
continue
tile = iob_tiles[ori] = Tile('mock_tile_io' + ori.name[0], iob, ori)
cboxify(lib, tile, sgmts, io_fc, ori.opposite)
for (position, orientation), cbox_inst in iteritems(tile.cbox_instances):
generate_fc(cbox_inst.model, sgmts, tile.block, orientation, io_fc,
position, orientation.case((0, 0), (0, 0), (0, -1), (-1, 0)))
netify_tile(tile)
# 3. create CLB
clb = LogicBlock('mock_clb')
clb.create_global(clk, Orientation.west)
clb.create_input('ina', 4, Orientation.south)
clb.create_output('outa', 2, Orientation.south)
clb.create_input('inb', 4, Orientation.north)
clb.create_output('outb', 2, Orientation.north)
cin = clb.create_input('cin', 1, Orientation.west)
cout = clb.create_output('cout', 1, Orientation.east)
# 4. direct tunnels
directs = [DirectTunnel('carrychain', cout, cin, (-1, 0))]
# 5. create CLB tiles
clb_tile = Tile('mock_tile_clb', clb)
clb_fc = BlockFCValue(BlockPortFCValue(0.25), BlockPortFCValue(0.5))
cboxify(lib, clb_tile, sgmts, clb_fc)
for (position, orientation), cbox_inst in iteritems(clb_tile.cbox_instances):
generate_fc(cbox_inst.model, sgmts, clb_tile.block, orientation, clb_fc,
position, orientation.case((0, 0), (0, 0), (0, -1), (-1, 0)))
netify_tile(clb_tile, directs)
# 6. create BRAM
bram = LogicBlock('mock_bram', 1, 3)
bram.create_global(clk, Orientation.south, position = (0, 0))
bram.create_input('we', 1, Orientation.south, (0, 0))
bram.create_input('din', 1, Orientation.west, (0, 0))
bram.create_output('dout', 1, Orientation.east, (0, 0))
bram.create_input('addr_l', 4, Orientation.west, (0, 1))
bram.create_input('addr_h', 4, Orientation.west, (0, 2))
# 7. create BRAM tiles
bram_tile = Tile('mock_tile_bram', bram)
bram_fc = BlockFCValue(BlockPortFCValue(0.25, {'din': 0.5, 'we': 0.5}), BlockPortFCValue(0.5))
cboxify(lib, bram_tile, sgmts, bram_fc)
for (position, orientation), cbox_inst in iteritems(bram_tile.cbox_instances):
generate_fc(cbox_inst.model, sgmts, bram_tile.block, orientation, bram_fc,
position, orientation.case((0, 0), (0, 0), (0, -1), (-1, 0)))
netify_tile(bram_tile, directs)
# 8. repetitive sub-array
subarray = Array('mock_sub_array', 3, 3, coverage = ChannelCoverage(north = True, east = True))
subarray.instantiate_element(bram_tile, (2, 0))
for x in range(2):
for y in range(3):
subarray.instantiate_element(clb_tile, (x, y))
sboxify(lib, subarray)
# 9. top array
array = Array('mock_array', 8, 8)
for i in range(1, 7):
array.instantiate_element(iob_tiles[Orientation.north], (i, 7))
array.instantiate_element(iob_tiles[Orientation.east], (7, i))
array.instantiate_element(iob_tiles[Orientation.south], (i, 0))
array.instantiate_element(iob_tiles[Orientation.west], (0, i))
for x in range(1, 7, 3):
for y in range(1, 7, 3):
array.instantiate_element(subarray, (x, y))
# 10. sboxes and more
for env, sbox in iteritems(lib.sboxes):
populate_switch_box(sbox, sgmts, env)
generate_wilton(sbox, sgmts, cycle_free = True)
netify_array(subarray)
netify_array(array, True)
# 11. switchify!
for box in chain(itervalues(lib.cboxes), itervalues(lib.sboxes)):
switchify(lib, box)
# 12. generate files
for module in chain(itervalues(lib.switches), itervalues(lib.sboxes), itervalues(lib.cboxes),
itervalues(iob_tiles), iter((clb_tile, bram_tile, subarray, array))):
gen.generate_module(tmpdir.join(module.name + '.v').open(OpenMode.wb), module)
