import argparse
parser = argparse.ArgumentParser(description="Generate int segfiles")
parser.add_argument(
'--todo', action='store', default='../../todo.txt', help='todo file path')
parser.add_argument(
'--design',
action='store',
default='design.txt',
help='design description file path')
parser.add_argument('--verbose', action='store_true', help='')
parser.add_argument(
'--bits', action='store', default='design.bits', help='bits file path')
args = parser.parse_args()
segmk = Segmaker(args.bits)
verbose = args.verbose
tiledata = dict()
pipdata = dict()
ignpip = set()
todo = set()
print("Loading todo from %s." % args.todo)
with open(args.todo, "r") as f:
for line in f:
line = tuple(line.strip().split("."))
verbose and print('todo', line)
todo.add(line)
#!/usr/bin/env python3
import sys, os, re
from prjxray.segmaker import Segmaker
segmk = Segmaker("design.bits")
tiledata = dict()
pipdata = set()
print("Loading tags from design.txt.")
with open("design.txt", "r") as f:
for line in f:
ab, dst, src = line.split()
tile, dst = dst.split("/")
_, src = src.split("/")
if tile not in tiledata:
tiledata[tile] = {
"pips": set(),
"nodes": set(),
}
if ab == "A":
tiledata[tile]["pips"].add((dst, src))
pipdata.add((dst, src))
else:
tiledata[tile]["nodes"].add(src)
tiledata[tile]["nodes"].add(dst)
def main():
segmk = Segmaker("design.bits")
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
attrs = json.load(attr_file)
print("Loading tags")
with open("params.json") as f:
params_dict = json.load(f)
tile_type = params_dict["tile_type"]
params_list = params_dict["params"]
sites_in_tile = dict()
for params in params_list:
site = params["site"]
tile = params["tile"]
if "GTPE2_COMMON" not in site:
continue
sites_in_tile[tile] = site
in_use = params["IN_USE"]
segmk.add_site_tag(site, "IN_USE", in_use)
if in_use:
for param, param_info in attrs.items():
value = params[param]
param_type = param_info["type"]
param_digits = param_info["digits"]
param_values = param_info["values"]
if param_type == INT:
param_encodings = param_info["encoding"]
param_encoding = param_encodings[param_values.index(value)]
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=param_encoding, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, '%s[%u]' % (param, i),
bitstr[i])
else:
assert param_type == BIN
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=value, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(site, "%s[%u]" % (param, i),
bitstr[i])
for param in ["PLL0LOCKDETCLK", "PLL1LOCKDETCLK", "DRPCLK"]:
segmk.add_site_tag(site, "INV_" + param, params[param])
for param in [
"GTREFCLK0_USED", "GTREFCLK1_USED", "BOTH_GTREFCLK_USED"
]:
segmk.add_site_tag(site, param, params[param])
segmk.add_site_tag(site, "ENABLE_DRP", params["ENABLE_DRP"])
for params in params_list:
site = params["site"]
if "IBUFDS_GTE2" not in site:
continue
in_use = params["IN_USE"]
segmk.add_site_tag(site, "IN_USE", in_use)
if in_use:
tile = params["tile"]
for param in ["CLKRCV_TRST", "CLKCM_CFG"]:
value = params[param]
segmk.add_site_tag(site, param, "TRUE" in value)
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=params["CLKSWING_CFG"], digits=2)[::-1]
]
gtp_common_site = sites_in_tile[tile]
for i in range(2):
segmk.add_site_tag(gtp_common_site,
"IBUFDS_GTE2.CLKSWING_CFG[%u]" % (i),
bitstr[i])
if tile_type.startswith("GTP_COMMON_MID"):
bitfilter = bitfilter_gtp_common_mid
elif tile_type == "GTP_COMMON":
bitfilter = bitfilter_gtp_common
else:
assert False, tile_type
segmk.compile(bitfilter=bitfilter)
segmk.write()
#!/usr/bin/env python3
import sys
from prjxray.segmaker import Segmaker
segmk = Segmaker("design_%s.bits" % sys.argv[1])
pipdata = dict()
ignpip = set()
print("Loading tags from design.txt.")
with open("design_%s.txt" % sys.argv[1], "r") as f:
for line in f:
tile, loc, mask, pattern = line.split()
dsp = "DSP_0" if loc[-1] in "02468" else "DSP_1"
mask = int(mask.replace("48'h", ""), 16)
pattern = int(pattern.replace("48'h", ""), 16)
for i in range(48):
segmk.add_tile_tag(tile, "%s.MASK[%d]" % (dsp, i), (mask >> i) & 1)
segmk.add_tile_tag(tile, "%s.PATTERN[%d]" % (dsp, i),
(pattern >> i) & 1)
segmk.compile()
segmk.write(suffix=sys.argv[1])
def main():
print("Loading tags")
segmk = Segmaker("design.bits")
'''
port,site,tile,pin,slew,drive,pulltype
di[0],IOB_X0Y107,LIOB33_X0Y107,A21,PULLDOWN
di[10],IOB_X0Y147,LIOB33_X0Y147,F14,PULLUP
'''
with open('params.jl', 'r') as f:
design = json.load(f)
for d in design:
site = d['site']
if skip_broken_tiles(d):
continue
iostandard = verilog.unquote(d['IOSTANDARD'])
stepdown = iostandard in STEPDOWN_IOSTANDARDS
segmk.add_site_tag(site, '_'.join(STEPDOWN_IOSTANDARDS), stepdown)
if d['type'] is None:
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
for drive in drives_for_iostandard(iostandard):
segmk.add_site_tag(
site,
'{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard,
drive), 0)
elif d['type'] == 'IBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 0)
for drive in drives_for_iostandard(iostandard):
segmk.add_site_tag(
site,
'{}.DRIVE.I{}.IN_OUT_COMMON'.format(iostandard,
drive), 1)
elif d['type'] == 'OBUF':
segmk.add_site_tag(site, 'INOUT', 0)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.IN'.format(iostandard), 0)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
for drive in drives_for_iostandard(iostandard):
if drive == d['DRIVE']:
segmk.add_site_tag(
site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
iostandard, drive), 1)
else:
segmk.add_site_tag(
site, '{}.DRIVE.I{}.IN_OUT_COMMON'.format(
iostandard, drive), 0)
elif d['type'] == 'IOBUF_INTERMDISABLE':
segmk.add_site_tag(site, 'INOUT', 1)
segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), 1)
segmk.add_site_tag(site, '{}.OUT'.format(iostandard), 1)
if d['type'] is not None:
segmaker.add_site_group_zero(
segmk, site, "PULLTYPE.",
("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN",
verilog.unquote(d['PULLTYPE']))
if d['type'] == 'IBUF' or d['type'] is None:
continue
drive_opts = set()
for opt in ("LVCMOS25", "LVCMOS33", "LVCMOS18", "LVCMOS15",
"LVCMOS12", 'LVTTL'):
for drive_opt in ("4", "8", "12", "16", "24"):
if drive_opt == "16" and opt == "LVCMOS12":
continue
if drive_opt == "24" and opt not in ["LVCMOS18", 'LVTTL']:
continue
drive_opts.add(mk_drive_opt(opt, drive_opt))
segmaker.add_site_group_zero(segmk, site, '', drive_opts,
mk_drive_opt('LVCMOS25', '12'),
mk_drive_opt(iostandard, d['DRIVE']))
segmaker.add_site_group_zero(segmk, site, "SLEW.",
("SLOW", "FAST"), "FAST",
verilog.unquote(d['SLEW']))
if 'ibufdisable_wire' in d:
segmk.add_site_tag(site, 'IBUFDISABLE.I',
d['ibufdisable_wire'] != '0')
if 'intermdisable_wire' in d:
segmk.add_site_tag(site, 'INTERMDISABLE.I',
d['intermdisable_wire'] != '0')
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
def main():
print("Loading tags")
segmk = Segmaker("design.bits")
with open('params.jl', 'r') as f:
design = json.load(f)
for d in design:
site = d['ologic_loc']
handle_data_width(segmk, d)
segmk.add_site_tag(site, 'OSERDES.IN_USE', d['use_oserdese2'])
if d['use_oserdese2']:
segmk.add_site_tag(site, 'OQUSED', 1)
for opt in ['SDR', 'DDR']:
segmk.add_site_tag(
site, 'OSERDES.DATA_RATE_OQ.{}'.format(opt),
verilog.unquote(d['DATA_RATE_OQ']) == opt)
data_rate_tq = verilog.unquote(d['DATA_RATE_TQ'])
segmk.add_site_tag(
site, 'OSERDES.DATA_RATE_TQ.{}'.format(data_rate_tq), 1)
for opt in ['BUF', 'SDR', 'DDR']:
segmk.add_site_tag(site,
'OSERDES.DATA_RATE_TQ.{}'.format(opt),
opt == data_rate_tq)
segmk.add_site_tag(site, 'OSERDES.DATA_RATE_TQ.ZBUF',
data_rate_tq != 'BUF')
for opt in ['SRVAL_OQ', 'SRVAL_TQ', 'INIT_OQ', 'INIT_TQ']:
segmk.add_site_tag(site, opt, d[opt])
segmk.add_site_tag(site, 'Z' + opt, 1 ^ d[opt])
for opt in ['CLK', 'CLKDIV']:
if d['{}_USED'.format(opt)]:
k = 'IS_{}_INVERTED'.format(opt)
segmk.add_site_tag(site, k, d[k])
segmk.add_site_tag(site, 'ZINV_{}'.format(opt),
1 ^ d[k])
if d['io']:
for idx in range(4):
k = 'IS_T{}_INVERTED'.format(idx + 1)
segmk.add_site_tag(site, k, d[k])
segmk.add_site_tag(site, 'ZINV_T{}'.format(idx + 1),
1 ^ d[k])
for idx in range(8):
k = 'IS_D{}_INVERTED'.format(idx + 1)
segmk.add_site_tag(site, k, d[k])
segmk.add_site_tag(site, 'ZINV_D{}'.format(idx + 1),
1 ^ d[k])
for tristate_width in [1, 4]:
segmk.add_site_tag(
site,
'OSERDES.TRISTATE_WIDTH.W{}'.format(tristate_width),
d['TRISTATE_WIDTH'] == tristate_width)
for opt in ['MASTER', 'SLAVE']:
segmk.add_site_tag(
site, 'OSERDES.SERDES_MODE.{}'.format(opt),
opt == verilog.unquote(d['OSERDES_MODE']))
if 'o_sr_used' in d:
if d['o_sr_used'] in ['S', 'R']:
segmk.add_site_tag(site, 'ODDR.SRUSED', 1)
segmk.add_site_tag(site, 'ODDR.ZSRUSED', 0)
else:
assert d['o_sr_used'] == 'None'
segmk.add_site_tag(site, 'ODDR.SRUSED', 0)
segmk.add_site_tag(site, 'ODDR.ZSRUSED', 1)
if 't_sr_used' in d:
if d['t_sr_used'] in ['S', 'R']:
segmk.add_site_tag(site, 'TDDR.SRUSED', 1)
segmk.add_site_tag(site, 'TDDR.ZSRUSED', 0)
else:
assert d['t_sr_used'] == 'None'
segmk.add_site_tag(site, 'TDDR.SRUSED', 0)
segmk.add_site_tag(site, 'TDDR.ZSRUSED', 1)
if d['oddr_mux_config'] == 'direct':
segmk.add_site_tag(site, 'ODDR_TDDR.IN_USE', 1)
if d['tddr_mux_config'] == 'direct':
segmk.add_site_tag(site, 'ODDR_TDDR.IN_USE', 1)
if d['oddr_mux_config'] == 'direct' and d[
'tddr_mux_config'] == 'direct':
segmk.add_site_tag(site, 'ZINV_CLK', 1 ^ d['IS_CLK_INVERTED'])
if d['IS_CLK_INVERTED'] == 0:
for opt in ['OPPOSITE_EDGE', 'SAME_EDGE']:
segmk.add_site_tag(
site, 'ODDR.DDR_CLK_EDGE.{}'.format(opt),
verilog.unquote(d['ODDR_CLK_EDGE']) == opt)
segmk.add_site_tag(site, 'TDDR.DDR_CLK_EDGE.INV',
d['ODDR_CLK_EDGE'] != d['TDDR_CLK_EDGE'])
segmk.add_site_tag(site, 'TDDR.DDR_CLK_EDGE.ZINV',
d['ODDR_CLK_EDGE'] == d['TDDR_CLK_EDGE'])
if 'SRTYPE' in d:
for opt in ['ASYNC', 'SYNC']:
segmk.add_site_tag(site,
'OSERDES.SRTYPE.{}'.format(opt),
verilog.unquote(d['SRTYPE']) == opt)
for opt in ['ASYNC', 'SYNC']:
segmk.add_site_tag(site, 'OSERDES.TSRTYPE.{}'.format(opt),
verilog.unquote(d['TSRTYPE']) == opt)
if not d['use_oserdese2']:
no_oserdes(segmk, site)
if d['oddr_mux_config'] == 'lut':
segmk.add_site_tag(site, 'ODDR_TDDR.IN_USE', 0)
segmk.add_site_tag(site, 'OMUX.D1', 1)
segmk.add_site_tag(site, 'OQUSED', 1)
elif d['oddr_mux_config'] == 'direct':
segmk.add_site_tag(site, 'OMUX.D1', 0)
elif d['oddr_mux_config'] == 'none' and not d['io']:
segmk.add_site_tag(site, 'OQUSED', 0)
segmk.add_site_tag(site, 'TQUSED', d['io'])
if DEBUG_FUZZER:
for k in d:
segmk.add_site_tag(
site, 'param_' + k + '_' +
str(d[k]).replace(' ', '').replace('\n', ''), 1)
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
def main():
print("Loading tags")
segmk = Segmaker("design.bits")
with open('params.jl', 'r') as f:
design = json.load(f)
for d in design:
site = d['site']
handle_data_width(segmk, d)
handle_data_rate(segmk, d)
if d['use_oserdese2']:
if 'SRTYPE' in d:
for opt in ['ASYNC', 'SYNC']:
segmk.add_site_tag(site,
'OSERDESE.SRTYPE.{}'.format(opt),
verilog.unquote(d['SRTYPE']) == opt)
for opt in ['SDR', 'DDR']:
segmk.add_site_tag(
site, 'OSERDESE.DATA_RATE_OQ.{}'.format(opt),
verilog.unquote(d['DATA_RATE_OQ']) == opt)
for opt in ['BUF', 'SDR', 'DDR']:
segmk.add_site_tag(
site, 'OSERDESE.DATA_RATE_TQ.{}'.format(opt),
verilog.unquote(d['DATA_RATE_TQ']) == opt)
if d['oddr_mux_config'] != 'none':
segmk.add_site_tag(site, 'OFF.ZINIT_Q', not d['QINIT'])
for opt in ['OPPOSITE_EDGE', 'SAME_EDGE']:
segmk.add_site_tag(
site, 'ODDR.DDR_CLK_EDGE.{}'.format(opt),
verilog.unquote(d['ODDR_CLK_EDGE']) == opt)
if d['tddr_mux_config'] != 'none':
segmk.add_site_tag(site, 'TFF.ZINIT_Q', not d['TINIT'])
# Note: edge settings seem to be ignored for TFF
for opt in ['OPPOSITE_EDGE', 'SAME_EDGE']:
segmk.add_site_tag(
site, 'TDDR.DDR_CLK_EDGE.{}'.format(opt),
verilog.unquote(d['TDDR_CLK_EDGE']) != opt)
# all the bellow mux configs give 0 candidates
# this is wierd, as they are set when DDR output is used
# something's fishy here
if d['oddr_mux_config'] == 'direct':
segmk.add_site_tag(site, 'OMUXE2', 0)
elif d['oddr_mux_config'] == 'none':
segmk.add_site_tag(site, 'OMUXE2', 1)
else:
assert False, d['oddr_mux_config']
if d['tddr_mux_config'] == 'direct':
segmk.add_site_tag(site, 'TMUXE2', 0)
elif d['tddr_mux_config'] == 'none':
segmk.add_site_tag(site, 'TMUXE2', 1)
else:
assert False, d['tddr_mux_config']
segmk.compile()
segmk.write(allow_empty=True)
