Beispiel #1
0
def run():
    print('''
module top();
    ''')
    params = {}

    sites = list(gen_sites())
    jtag_chains = ("1", "2", "3", "4")
    for (tile_name, site_name), isone in zip(sites,
                                             util.gen_fuzz_states(len(sites))):
        params[tile_name] = (site_name, isone)
        print('''
            (* KEEP, DONT_TOUCH, LOC = "{0}" *)
            BSCANE2 #(
            .JTAG_CHAIN("{1}")
            )
            BSCANE2_{0} (
            .CAPTURE(),
            .DRCK(),
            .RESET(),
            .RUNTEST(),
            .SEL(),
            .SHIFT(),
            .TCK(),
            .TDI(),
            .TMS(),
            .UPDATE(),
            .TDO(1'b1)
            );
        '''.format(site_name, jtag_chains[isone]))

    print("endmodule")
    write_params(params)
Beispiel #2
0
def run():
    print('''
module top(input clk, stb, di, output do);
    localparam integer DIN_N = 8;
    localparam integer DOUT_N = 8;

    reg [DIN_N-1:0] din;
    wire [DOUT_N-1:0] dout;

    reg [DIN_N-1:0] din_shr;
    reg [DOUT_N-1:0] dout_shr;

    always @(posedge clk) begin
        din_shr <= {din_shr, di};
        dout_shr <= {dout_shr, din_shr[DIN_N-1]};
        if (stb) begin
            din <= din_shr;
            dout_shr <= dout;
        end
    end

    assign do = dout_shr[DOUT_N-1];
    ''')

    params = {}

    sites = list(gen_sites())
    for (tile_name, site_name), isone in zip(sites,
                                             util.gen_fuzz_states(len(sites))):
        params[tile_name] = (site_name, isone)

    print("endmodule")
    write_params(params)
Beispiel #3
0
def run():
    print('''
module top();
    ''')

    params = {}

    sites = list(gen_sites())
    for (tile_name, sites), isone in zip(sites,
                                         util.gen_fuzz_states(len(sites))):
        site_name = sites[0]
        params[tile_name] = (site_name, isone)

        print('''
            wire clk_{site};
            (* KEEP, DONT_TOUCH, LOC = "{site}" *)
            BUFMRCE #(
                .INIT_OUT({isone})
                ) buf_{site} (
                .O(clk_{site})
            );

            BUFR bufr_{site} (
                .I(clk_{site})
                );
'''.format(
            site=site_name,
            isone=isone,
        ))

    print("endmodule")
    write_params(params)
Beispiel #4
0
def run():
    print('''
module top();
    ''')

    params = {}

    sites = list(gen_sites())
    for (tile_name, sites), isone in zip(sites,
                                         util.gen_fuzz_states(len(sites))):
        site_name = sites[0]
        params[tile_name] = (site_name, isone)

        print('''
            wire clk_{site};
            BUFMRCE buf_{site} (
                .O(clk_{site})
            );

            (* KEEP, DONT_TOUCH, LOC = "{site}" *)
            BUFR #(
                .BUFR_DIVIDE("{divide}")
                ) bufr_{site} (
                .I(clk_{site})
                );
'''.format(site=site_name, divide="2" if isone else "1"))

    print("endmodule")
    write_params(params)
Beispiel #5
0
    def __iter__(self):
        assert self.curr_state is None
        assert self.states is None
        assert self.curr_state is None

        self.curr_site_idx = 0
        self.curr_state = None
        self.states = util.gen_fuzz_states(
            len(self.sites) * self.states_per_site)
        self.curr_site = iter(self.sites)
        return self
Beispiel #6
0
def run():
    print('''
module top(input di, output do);
    assign do = di;
    ''')

    params = {}

    sites = sorted(list(gen_sites()))
    for (tile_name, site_name), isone in zip(sites,
                                             util.gen_fuzz_states(len(sites))):
        params[tile_name] = (site_name, isone)

    print("endmodule")
    write_params(params)
Beispiel #7
0
def run():
    luts = lut_maker.LutMaker()
    connects = io.StringIO()

    tile_params = []
    params = []
    sites = sorted(list(gen_sites()))
    for idx, ((tile, site),
              isone) in enumerate(zip(sites,
                                      util.gen_fuzz_states(len(sites)))):

        p = {}
        p['tile'] = tile
        p['site'] = site
        p['isone'] = isone
        params.append(p)
        tile_params.append((tile, p['isone'], site))

    write_params(tile_params)

    print('''
module top();
    ''')

    # Always output a LUT6 to make placer happy.
    print('''
     (* KEEP, DONT_TOUCH *)
     LUT6 dummy_lut();
     ''')

    # Need IDELAYCTRL for IDEALAYs
    print('''
     (* KEEP, DONT_TOUCH *)
     IDELAYCTRL();
     ''')

    for p in params:
        use_idelay(p, luts, connects)

    for l in luts.create_wires_and_luts():
        print(l)

    print(connects.getvalue())

    print("endmodule")
Beispiel #8
0
def run():
    print('''
module top(input wire in, output wire out);
    ''')

    params = {}

    sites = list(gen_sites())
    for (tile_name, site_name), isone in zip(sites,
                                             util.gen_fuzz_states(len(sites))):
        params[tile_name] = (site_name, isone)

        print('''
    (* KEEP, DONT_TOUCH, LOC = "{}" *)
   GTPE2_CHANNEL #(
        .RXSYNC_OVRD(1'b{})
    ) gtpe2_channel_{} ();'''.format(site_name, isone, site_name))

    print("endmodule")
    write_params(params)
Beispiel #9
0
def run():
    print('''
module top();
    ''')

    params = {}

    sites = sorted(list(gen_sites()))
    for (tile_name, site_name), isone in zip(sites,
                                             util.gen_fuzz_states(len(sites))):
        params[tile_name] = (site_name, isone)

        # Force HARD0 -> GFAN1 with I2 = 0
        # Toggle 1 pip with I1 = ?
        print('''
            wire lut_to_f7_{0}, f7_to_f8_{0};
            (* KEEP, DONT_TOUCH, LOC = "{0}" *)
            LUT6_L #(
            .INIT(0)
            ) lut_rom_{0} (
                    .I0(1),
                    .I1({1}),
                    .I2(0),
                    .I3(1),
                    .I4(1),
                    .I5(1),
                    .LO(lut_to_f7_{0})
                    );
            (* KEEP, DONT_TOUCH, LOC = "{0}" *)
            MUXF7_L f7_{0} (
                .I0(lut_to_f7_{0}),
                .LO(f7_to_f8_{0})
                );
            (* KEEP, DONT_TOUCH, LOC = "{0}" *)
            MUXF8 f8_{0} (
                .I0(f7_to_f8_{0})
                );
'''.format(site_name, isone))

    print("endmodule")
    write_params(params)
Beispiel #10
0
def run():
    print('''
module top(input wire in, output wire out);
    ''')

    params = {}

    sites = list(gen_sites())
    for (tile_name, site_name), isone in zip(sites,
                                             util.gen_fuzz_states(len(sites))):
        params[tile_name] = (site_name, isone)

        attr = "FALSE" if isone else "TRUE"
        print('''
    (* KEEP, DONT_TOUCH*)
    PCIE_2_1 #(
        .AER_CAP_PERMIT_ROOTERR_UPDATE("{}")
    ) pcie ();'''.format(attr))

    print("endmodule")
    write_params(params)
Beispiel #11
0
def run():
    print('''
module top(input wire in, output wire out);
    ''')

    params = {}

    sites = list(gen_sites())
    for (tile_name, site_name), isone in zip(sites,
                                             util.gen_fuzz_states(len(sites))):
        params[tile_name] = (site_name, isone)

        attr = 4 if isone else 5
        print('''
    (* KEEP, DONT_TOUCH, LOC="{site}" *)
    GTPE2_COMMON #(
        .PLL0_FBDIV_45({attr})
    ) {site} ();'''.format(attr=attr, site=site_name))

    print("endmodule")
    write_params(params)
Beispiel #12
0
def run():
    print('''
module top();
    ''')

    params = {}

    sites = list(gen_sites())
    for (tile_name, site_name), isone in zip(sites,
                                             util.gen_fuzz_states(len(sites))):
        params[tile_name] = (site_name, isone)

        print('''
            (* KEEP, DONT_TOUCH, LOC = "{0}" *)
            DSP48E1 #(
                .MASK({1})
            ) dsp_{0} (
            );
'''.format(site_name, isone))

    print("endmodule")
    write_params(params)
Beispiel #13
0
def run():
    sites = list(gen_sites())
    print('''
`define N_DI {}

module top(input wire [`N_DI-1:0] di);
    wire [`N_DI-1:0] di_buf;

    (* KEEP, DONT_TOUCH, IODELAY_GROUP = "iodelays" *)
    IDELAYCTRL idelayctrl (
        .REFCLK()
    );
    '''.format(len(sites)))

    params = {}

    for idx, ((tile_name, site_name, pad_site_name),
              isone) in enumerate(zip(sites,
                                      util.gen_fuzz_states(len(sites)))):
        params[tile_name] = (site_name, isone, pad_site_name, "di[%u]" % idx)

        # Force HARD0 -> GFAN1 with CNTVALUEIN4 = 0
        # Toggle 1 pip with CNTVALUEIN3 = ?
        print('''

            // Solving for {3}
            (* KEEP, DONT_TOUCH *)
            IBUF ibuf_{0}(.I(di[{2}]), .O(di_buf[{2}]));

            (* KEEP, DONT_TOUCH, LOC = "{0}", IODELAY_GROUP = "iodelays" *)
            IDELAYE2 idelay_{0} (
                .CNTVALUEIN(5'b0{1}111),
                .IDATAIN(di_buf[{2}])
                );
'''.format(site_name, isone, idx, tile_name))

    print("endmodule")
    write_params(params)
Beispiel #14
0
def run():
    sites = list(gen_sites())
    print(
        '''
`define N_DI {}

module top(input wire [`N_DI-1:0] di);
    wire [`N_DI-1:0] di_buf;
    '''.format(len(sites)))

    params = {}
    print('''
        (* KEEP, DONT_TOUCH *)
        LUT6 dummy_lut();''')

    for idx, ((tile_name, site_name), isone) in enumerate(zip(
            sites, util.gen_fuzz_states(len(sites)))):
        params[tile_name] = (site_name, isone, "di[%u]" % idx)
        print(
            '''
    (* KEEP, DONT_TOUCH *)
    IBUF #(
    ) ibuf_{site_name} (
        .I(di[{idx}]),
        .O(di_buf[{idx}])
        );'''.format(site_name=site_name, idx=idx))

        if isone:
            print(
                '''
    (* KEEP, DONT_TOUCH *)
    PULLUP #(
    ) pullup_{site_name} (
        .O(di[{idx}])
        );'''.format(site_name=site_name, idx=idx))

    print("endmodule")
    write_params(params)
Beispiel #15
0
def run():
    print('''
module top();
    ''')

    params = {}

    sites = list(gen_sites())
    for (tile_name, site_name), isone in zip(sites,
                                             util.gen_fuzz_states(len(sites))):
        params[tile_name] = (site_name, isone)

        print('''
            (* KEEP, DONT_TOUCH, LOC = "{site_name}" *)
            RAMB18E1 #(
                    .INIT_00(256'b{isone})
                ) bram_{site_name} ();'''.format(
            site_name=site_name,
            isone=isone,
        ))

    print("endmodule")
    write_params(params)
Beispiel #16
0
def run():
    print('''
module top();
    ''')

    params = {}
    # FIXME: can't LOC?
    # only one for now, worry about later
    sites = list(gen_sites())
    for (tile_name, site_name), isone in zip(sites,
                                             util.gen_fuzz_states(len(sites))):
        params[tile_name] = (site_name, isone)

        print('''
    (* KEEP, DONT_TOUCH,  LOC = "{site_name}" *)
    PLLE2_ADV #( .STARTUP_WAIT({isone}) ) dut_{site_name} ();
'''.format(
            site_name=site_name,
            isone=verilog.quote('TRUE' if isone else 'FALSE'),
        ))

    print("endmodule")
    write_params(params)
Beispiel #17
0
def run():
    print('''
module top(input clk, stb, di, output do);
    localparam integer DIN_N = 8;
    localparam integer DOUT_N = 8;

    reg [DIN_N-1:0] din;
    wire [DOUT_N-1:0] dout;

    reg [DIN_N-1:0] din_shr;
    reg [DOUT_N-1:0] dout_shr;

    always @(posedge clk) begin
        din_shr <= {din_shr, di};
        dout_shr <= {dout_shr, din_shr[DIN_N-1]};
        if (stb) begin
            din <= din_shr;
            dout_shr <= dout;
        end
    end

    assign do = dout_shr[DOUT_N-1];
    ''')

    params = {}
    # FIXME: can't LOC?
    # only one for now, worry about later
    sites = list(gen_sites())
    for (tile_name, site_name), isone in zip(sites,
                                             util.gen_fuzz_states(len(sites))):
        # 0 is invalid
        # shift one bit, keeping LSB constant
        CLKOUT1_DIVIDE = {0: 2, 1: 3}[isone]
        params[tile_name] = (site_name, CLKOUT1_DIVIDE)

        print('''
    (* KEEP, DONT_TOUCH, LOC=%s *)
    MMCME2_ADV #(/*.LOC("%s"),*/ .CLKOUT1_DIVIDE(%u)) dut_%s(
            .CLKFBOUT(),
            .CLKFBOUTB(),
            .CLKFBSTOPPED(),
            .CLKINSTOPPED(),
            .CLKOUT0(),
            .CLKOUT0B(),
            .CLKOUT1(),
            .CLKOUT1B(),
            .CLKOUT2(),
            .CLKOUT2B(),
            .CLKOUT3(),
            .CLKOUT3B(),
            .CLKOUT4(),
            .CLKOUT5(),
            .CLKOUT6(),
            .DO(),
            .DRDY(),
            .LOCKED(),
            .PSDONE(),
            .CLKFBIN(clk),
            .CLKIN1(clk),
            .CLKIN2(clk),
            .CLKINSEL(clk),
            .DADDR(),
            .DCLK(clk),
            .DEN(),
            .DI(),
            .DWE(),
            .PSCLK(clk),
            .PSEN(),
            .PSINCDEC(),
            .PWRDWN(),
            .RST());
''' % (verilog.quote(site_name), site_name, CLKOUT1_DIVIDE, site_name))

    print("endmodule")
    write_params(params)
Beispiel #18
0
def run():
    print(
        '''
module top(input clk, stb, di, output do);
    localparam integer DIN_N = 8;
    localparam integer DOUT_N = 8;

    reg [DIN_N-1:0] din;
    wire [DOUT_N-1:0] dout;

    reg [DIN_N-1:0] din_shr;
    reg [DOUT_N-1:0] dout_shr;

    always @(posedge clk) begin
        din_shr <= {din_shr, di};
        dout_shr <= {dout_shr, din_shr[DIN_N-1]};
        if (stb) begin
            din <= din_shr;
            dout_shr <= dout;
        end
    end

    assign do = dout_shr[DOUT_N-1];
    ''')

    params = {}

    sites = list(gen_sites())
    for (tile_name, site_name), isone in zip(sites,
                                             util.gen_fuzz_states(len(sites))):
        params[tile_name] = (site_name, isone)

        print(
            '''
            (* KEEP, DONT_TOUCH, LOC = "%s" *)
            RAMB36E1 #(
                    .INIT_00(256'b%u)
                ) bram_%s (
                    .CLKARDCLK(),
                    .CLKBWRCLK(),
                    .ENARDEN(),
                    .ENBWREN(),
                    .REGCEAREGCE(),
                    .REGCEB(),
                    .RSTRAMARSTRAM(),
                    .RSTRAMB(),
                    .RSTREGARSTREG(),
                    .RSTREGB(),
                    .ADDRARDADDR(),
                    .ADDRBWRADDR(),
                    .DIADI(),
                    .DIBDI(),
                    .DIPADIP(),
                    .DIPBDIP(),
                    .WEA(),
                    .WEBWE(),
                    .DOADO(),
                    .DOBDO(),
                    .DOPADOP(),
                    .DOPBDOP());
''' % (site_name, isone, site_name))

    print("endmodule")
    write_params(params)
Beispiel #19
0
def run():
    print('''
module top();
    ''')

    params = {}

    sites = list(gen_fifos())
    N_INT = 12

    fuzz_iter = iter(util.gen_fuzz_states(len(sites) * N_INT))
    for site, int_tiles in sites:
        assert len(int_tiles) == N_INT
        int_tiles.reverse()

        bits = itertools.islice(fuzz_iter, N_INT)

        assigns = []

        # CMT_FIFO mux usage is regular with IMUX_L40 and IMUX_L42.
        #
        # INT[idx].IMUX_L40 = IN.D{idx}[1]
        # INT[idx].IMUX_L42 = IN.D{idx}[3]
        CHANNEL = [0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9]
        HOLD_BIT_0 = [1, 1, 1, 1, 1, 1, 5, 5, 1, 1, 1, 1]
        TOGGLE_BIT = [3, 3, 3, 3, 3, 3, 7, 7, 3, 3, 3, 3]
        #             0  1  2  3  4  5  6  7  8  9
        WIDTH = [4, 4, 4, 4, 4, 8, 8, 4, 4, 4]

        bits_set = set()

        for idx, (int_tile, bit) in enumerate(zip(int_tiles, bits)):
            bits_set.add((CHANNEL[idx], HOLD_BIT_0[idx]))
            bits_set.add((CHANNEL[idx], TOGGLE_BIT[idx]))

            assigns.append('            // {}'.format(int_tile))
            assigns.append(
                '            assign {site}_in_d{channel}[{bit}] = 0;'.format(
                    site=site,
                    channel=CHANNEL[idx],
                    bit=HOLD_BIT_0[idx],
                ))
            assigns.append(
                '            assign {site}_in_d{channel}[{bit}] = {toggle_bit};'
                .format(
                    site=site,
                    channel=CHANNEL[idx],
                    bit=TOGGLE_BIT[idx],
                    toggle_bit=bit,
                ))
            params[int_tile] = (bit, )

            assigns.append('')

        for channel, width in enumerate(WIDTH):
            for bit in range(width):
                if (channel, bit) not in bits_set:
                    assigns.append(
                        '            assign {site}_in_d{channel}[{bit}] = 1;'.
                        format(
                            site=site,
                            channel=channel,
                            bit=bit,
                        ))

        print('''
            wire [3:0] {site}_in_d0;
            wire [3:0] {site}_in_d1;
            wire [3:0] {site}_in_d2;
            wire [3:0] {site}_in_d3;
            wire [3:0] {site}_in_d4;
            wire [7:0] {site}_in_d5;
            wire [7:0] {site}_in_d6;
            wire [3:0] {site}_in_d7;
            wire [3:0] {site}_in_d8;
            wire [3:0] {site}_in_d9;

{assign_statements}

            (* KEEP, DONT_TOUCH, LOC = "{site}" *)
            IN_FIFO fifo_{site} (
                .D0({site}_in_d0),
                .D1({site}_in_d1),
                .D2({site}_in_d2),
                .D3({site}_in_d3),
                .D4({site}_in_d4),
                .D5({site}_in_d5),
                .D6({site}_in_d6),
                .D7({site}_in_d7),
                .D8({site}_in_d8),
                .D9({site}_in_d9)
                );
'''.format(
            site=site,
            assign_statements='\n'.join(assigns),
        ))

    print("endmodule")
    write_params(params)
Beispiel #20
0
def run():
    print('''
module top();
    ''')

    params = {}

    sites = list(gen_dsps())
    fuzz_iter = iter(util.gen_fuzz_states(len(sites) * 5))
    for tile_name, dsp_sites, int_tiles in sites:
        int_tiles.reverse()

        # Each DSP tile has 5 INT tiles.
        # The following feature is used to toggle a one PIP in each INT tile
        #
        # For a DSP, there are the following INT tiles and the feature
        # to toggle
        #
        # INT_L_X34Y89/INT_L.GFAN1->>IMUX_L30 :: D1.C36 = 0
        # INT_L_X34Y89/INT_L.GFAN1->>IMUX_L28 :: D1.CARRYINSEL1 = toggle
        #
        # INT_L_X34Y88/INT_L.GFAN1->>IMUX_L30 :: D0.CARRYINSEL0 = toggle
        #
        # INT_L_X34Y87/INT_L.GFAN1->>IMUX_L5  :: D1.A29 = 0
        # INT_L_X34Y87/INT_L.GFAN1->>IMUX_L14 :: D1.B8 = toggle
        #
        # INT_L_X34Y86/INT_L.GFAN1->>IMUX_L30 :: D1.B4 = 0
        # INT_L_X34Y86/INT_L.GFAN1->>IMUX_L28 :: D1.B6 = toggle
        #
        # INT_L_X34Y85/INT_L.GFAN1->>IMUX_L30 :: Dark Green :: D1.C20 = 0
        # INT_L_X34Y85/INT_L.GFAN1->>IMUX_L28 :: Color 10 :: D1.B2 = toggle
        (d1_carryinsel1, d0_carryinsel0, d1_b8, d1_b6,
         d1_b2) = itertools.islice(fuzz_iter, 5)
        params[int_tiles[0]] = (d1_carryinsel1, )
        params[int_tiles[1]] = (d0_carryinsel0, )
        params[int_tiles[2]] = (d1_b8, )
        params[int_tiles[3]] = (d1_b6, )
        params[int_tiles[4]] = (d1_b2, )

        print('''
            wire [6:0] {dsp_site0}_opmode;
            wire [2:0] {dsp_site0}_carryinsel;

            wire [29:0] {dsp_site1}_a;
            wire [17:0] {dsp_site1}_b;
            wire [47:0] {dsp_site1}_c;
            wire [6:0] {dsp_site1}_opmode;
            wire [2:0] {dsp_site1}_carryinsel;

            // INT 0, {int0}
            assign {dsp_site1}_c[36] = 0;
            assign {dsp_site1}_carryinsel[1] = {d1_carryinsel1};

            // INT 1, {int1}
            assign {dsp_site0}_carryinsel[0] = {d0_carryinsel0};

            // INT 2, {int2}
            assign {dsp_site1}_a[29] = 0;
            assign {dsp_site1}_b[8] = {d1_b8};

            // INT 3, {int3}
            assign {dsp_site1}_b[4] = 0;
            assign {dsp_site1}_b[6] = {d1_b6};

            // INT 4, {int4}
            assign {dsp_site1}_c[20] = 0;
            assign {dsp_site1}_b[2] = {d1_b2};

            (* KEEP, DONT_TOUCH, LOC = "{dsp_site0}" *)
            DSP48E1 #(
                    .OPMODEREG(0),
                    .CREG(0)
                ) dsp_{dsp_site0} (
                    .OPMODE({dsp_site0}_opmode),
                    .CARRYINSEL({dsp_site0}_carryinsel)
                    );

            (* KEEP, DONT_TOUCH, LOC = "{dsp_site1}" *)
            DSP48E1 #(
                    .OPMODEREG(0),
                    .CREG(0)
                ) dsp_{dsp_site1} (
                    .OPMODE({dsp_site1}_opmode),
                    .CARRYINSEL({dsp_site1}_carryinsel),
                    .A({dsp_site1}_a),
                    .B({dsp_site1}_b),
                    .C({dsp_site1}_c)
                    );
'''.format(
            dsp_site0=dsp_sites[0],
            dsp_site1=dsp_sites[1],
            d1_carryinsel1=d1_carryinsel1,
            d0_carryinsel0=d0_carryinsel0,
            d1_b8=d1_b8,
            d1_b6=d1_b6,
            d1_b2=d1_b2,
            int0=int_tiles[0],
            int1=int_tiles[1],
            int2=int_tiles[2],
            int3=int_tiles[3],
            int4=int_tiles[4],
        ))

    print("endmodule")
    write_params(params)
Beispiel #21
0
def run():
    print('''
module top(input clk, stb, di, output do);
    localparam integer DIN_N = 8;
    localparam integer DOUT_N = 8;

    reg [DIN_N-1:0] din;
    wire [DOUT_N-1:0] dout;

    reg [DIN_N-1:0] din_shr;
    reg [DOUT_N-1:0] dout_shr;

    always @(posedge clk) begin
        din_shr <= {din_shr, di};
        dout_shr <= {dout_shr, din_shr[DIN_N-1]};
        if (stb) begin
            din <= din_shr;
            dout_shr <= dout;
        end
    end

    assign do = dout_shr[DOUT_N-1];
    ''')

    params = {}

    # NOTE: The INT_L tile has been hardcoded and it works only for the part specified in the assertion
    database = os.getenv('XRAY_DATABASE')
    int_tile = os.getenv('XRAY_PS7_INT')
    assert database == "zynq7", database
    for isone in util.gen_fuzz_states(1):
        params[int_tile] = isone
        print('''
    (* KEEP, DONT_TOUCH *)

    PS7 dut_%(dut)s(
	.DMA0DATYPE			(),
	.DMA0DAVALID			(),
	.DMA0DRREADY			(),
	.DMA0RSTN			(),
	.DMA1DATYPE	              	(),
	.DMA1DAVALID			(),
	.DMA1DRREADY			(),
	.DMA1RSTN			(),
	.DMA2DATYPE			(),
	.DMA2DAVALID			(),
	.DMA2DRREADY			(),
	.DMA2RSTN			(),
	.DMA3DATYPE			(),
	.DMA3DAVALID			(),
	.DMA3DRREADY			(),
	.DMA3RSTN			(),
	.EMIOCAN0PHYTX			(),
	.EMIOCAN1PHYTX			(),
	.EMIOENET0GMIITXD		(),
	.EMIOENET0GMIITXEN		(),
	.EMIOENET0GMIITXER		(),
	.EMIOENET0MDIOMDC		(),
	.EMIOENET0MDIOO			(),
	.EMIOENET0MDIOTN		(),
	.EMIOENET0PTPDELAYREQRX		(),
	.EMIOENET0PTPDELAYREQTX		(),
	.EMIOENET0PTPPDELAYREQRX	(),
	.EMIOENET0PTPPDELAYREQTX	(),
	.EMIOENET0PTPPDELAYRESPRX	(),
	.EMIOENET0PTPPDELAYRESPTX	(),
	.EMIOENET0PTPSYNCFRAMERX	(),
	.EMIOENET0PTPSYNCFRAMETX	(),
	.EMIOENET0SOFRX			(),
	.EMIOENET0SOFTX			(),
	.EMIOENET1GMIITXD		(),
	.EMIOENET1GMIITXEN		(),
	.EMIOENET1GMIITXER		(),
	.EMIOENET1MDIOMDC		(),
	.EMIOENET1MDIOO			(),
	.EMIOENET1MDIOTN		(),
	.EMIOENET1PTPDELAYREQRX		(),
	.EMIOENET1PTPDELAYREQTX		(),
	.EMIOENET1PTPPDELAYREQRX	(),
	.EMIOENET1PTPPDELAYREQTX	(),
	.EMIOENET1PTPPDELAYRESPRX	(),
	.EMIOENET1PTPPDELAYRESPTX	(),
	.EMIOENET1PTPSYNCFRAMERX	(),
	.EMIOENET1PTPSYNCFRAMETX	(),
	.EMIOENET1SOFRX			(),
	.EMIOENET1SOFTX			(),
	.EMIOGPIOO			(),
	.EMIOGPIOTN			(),
	.EMIOI2C0SCLO			(),
	.EMIOI2C0SCLTN			(),
	.EMIOI2C0SDAO			(),
	.EMIOI2C0SDATN			(),
	.EMIOI2C1SCLO			(),
	.EMIOI2C1SCLTN			(),
	.EMIOI2C1SDAO			(),
	.EMIOI2C1SDATN			(),
	.EMIOPJTAGTDO			(),
	.EMIOPJTAGTDTN			(),
	.EMIOSDIO0BUSPOW		(),
	.EMIOSDIO0BUSVOLT		(),
	.EMIOSDIO0CLK			(),
	.EMIOSDIO0CMDO			(),
	.EMIOSDIO0CMDTN			(),
	.EMIOSDIO0DATAO			(),
	.EMIOSDIO0DATATN		(),
	.EMIOSDIO0LED			(),
	.EMIOSDIO1BUSPOW		(),
	.EMIOSDIO1BUSVOLT		(),
	.EMIOSDIO1CLK			(),
	.EMIOSDIO1CMDO			(),
	.EMIOSDIO1CMDTN			(),
	.EMIOSDIO1DATAO			(),
	.EMIOSDIO1DATATN		(),
	.EMIOSDIO1LED			(),
	.EMIOSPI0MO			(),
	.EMIOSPI0MOTN			(),
	.EMIOSPI0SCLKO			(),
	.EMIOSPI0SCLKTN			(),
	.EMIOSPI0SO			(),
	.EMIOSPI0SSNTN			(),
	.EMIOSPI0SSON			(),
	.EMIOSPI0STN			(),
	.EMIOSPI1MO			(),
	.EMIOSPI1MOTN			(),
	.EMIOSPI1SCLKO			(),
	.EMIOSPI1SCLKTN			(),
	.EMIOSPI1SO			(),
	.EMIOSPI1SSNTN			(),
	.EMIOSPI1SSON			(),
	.EMIOSPI1STN			(),
	.EMIOTRACECTL			(),
	.EMIOTRACEDATA			(),
	.EMIOTTC0WAVEO			(),
	.EMIOTTC1WAVEO			(),
	.EMIOUART0DTRN			(),
	.EMIOUART0RTSN			(),
	.EMIOUART0TX			(),
	.EMIOUART1DTRN			(),
	.EMIOUART1RTSN			(),
	.EMIOUART1TX			(),
	.EMIOUSB0PORTINDCTL		(),
	.EMIOUSB0VBUSPWRSELECT		(),
	.EMIOUSB1PORTINDCTL		(),
	.EMIOUSB1VBUSPWRSELECT		(),
	.EMIOWDTRSTO			(),
	.EVENTEVENTO			(),
	.EVENTSTANDBYWFE		(),
	.EVENTSTANDBYWFI		(),
	.FCLKCLK			(),
	.FCLKRESETN			(),
	.FTMTF2PTRIGACK			(),
	.FTMTP2FDEBUG			(),
	.FTMTP2FTRIG			(),
	.IRQP2F				(),
	.MAXIGP0ARADDR			(),
	.MAXIGP0ARBURST			(),
	.MAXIGP0ARCACHE			(),
	.MAXIGP0ARESETN			(),
	.MAXIGP0ARID			(),
	.MAXIGP0ARLEN			(),
	.MAXIGP0ARLOCK			(),
	.MAXIGP0ARPROT			(),
	.MAXIGP0ARQOS			(),
	.MAXIGP0ARSIZE			(),
	.MAXIGP0ARVALID			(),
	.MAXIGP0AWADDR			(),
	.MAXIGP0AWBURST			(),
	.MAXIGP0AWCACHE			(),
	.MAXIGP0AWID			(),
	.MAXIGP0AWLEN			(),
	.MAXIGP0AWLOCK			(),
	.MAXIGP0AWPROT			(),
	.MAXIGP0AWQOS			(),
	.MAXIGP0AWSIZE			(),
	.MAXIGP0AWVALID			(),
	.MAXIGP0BREADY			(),
	.MAXIGP0RREADY			(),
	.MAXIGP0WDATA			(),
	.MAXIGP0WID			(),
	.MAXIGP0WLAST			(),
	.MAXIGP0WSTRB			(),
	.MAXIGP0WVALID			(),
	.MAXIGP1ARADDR			(),
	.MAXIGP1ARBURST			(),
	.MAXIGP1ARCACHE			(),
	.MAXIGP1ARESETN			(),
	.MAXIGP1ARID			(),
	.MAXIGP1ARLEN			(),
	.MAXIGP1ARLOCK			(),
	.MAXIGP1ARPROT			(),
	.MAXIGP1ARQOS			(),
	.MAXIGP1ARSIZE			(),
	.MAXIGP1ARVALID			(),
	.MAXIGP1AWADDR			(),
	.MAXIGP1AWBURST			(),
	.MAXIGP1AWCACHE			(),
	.MAXIGP1AWID			(),
	.MAXIGP1AWLEN			(),
	.MAXIGP1AWLOCK			(),
	.MAXIGP1AWPROT			(),
	.MAXIGP1AWQOS			(),
	.MAXIGP1AWSIZE			(),
	.MAXIGP1AWVALID			(),
	.MAXIGP1BREADY			(),
	.MAXIGP1RREADY			(),
	.MAXIGP1WDATA			(),
	.MAXIGP1WID			(),
	.MAXIGP1WLAST			(),
	.MAXIGP1WSTRB			(),
	.MAXIGP1WVALID			(),
	.SAXIACPARESETN			(),
	.SAXIACPARREADY			(),
	.SAXIACPAWREADY			(),
	.SAXIACPBID			(),
	.SAXIACPBRESP			(),
	.SAXIACPBVALID			(),
	.SAXIACPRDATA			(),
	.SAXIACPRID			(),
	.SAXIACPRLAST			(),
	.SAXIACPRRESP			(),
	.SAXIACPRVALID			(),
	.SAXIACPWREADY			(),
	.SAXIGP0ARESETN			(),
	.SAXIGP0ARREADY			(),
	.SAXIGP0AWREADY			(),
	.SAXIGP0BID			(),
	.SAXIGP0BRESP			(),
	.SAXIGP0BVALID			(),
	.SAXIGP0RDATA			(),
	.SAXIGP0RID			(),
	.SAXIGP0RLAST			(),
	.SAXIGP0RRESP			(),
	.SAXIGP0RVALID			(),
	.SAXIGP0WREADY			(),
	.SAXIGP1ARESETN			(),
	.SAXIGP1ARREADY			(),
	.SAXIGP1AWREADY			(),
	.SAXIGP1BID			(),
	.SAXIGP1BRESP			(),
	.SAXIGP1BVALID			(),
	.SAXIGP1RDATA			(),
	.SAXIGP1RID			(),
	.SAXIGP1RLAST			(),
	.SAXIGP1RRESP			(),
	.SAXIGP1RVALID			(),
	.SAXIGP1WREADY			(),
	.SAXIHP0ARESETN			(),
	.SAXIHP0ARREADY			(),
	.SAXIHP0AWREADY			(),
	.SAXIHP0BID			(),
	.SAXIHP0BRESP			(),
	.SAXIHP0BVALID			(),
	.SAXIHP0RACOUNT			(),
	.SAXIHP0RCOUNT			(),
	.SAXIHP0RDATA			(),
	.SAXIHP0RID			(),
	.SAXIHP0RLAST			(),
	.SAXIHP0RRESP			(),
	.SAXIHP0RVALID			(),
	.SAXIHP0WACOUNT			(),
	.SAXIHP0WCOUNT			(),
	.SAXIHP0WREADY			(),
	.SAXIHP1ARESETN			(),
	.SAXIHP1ARREADY			(),
	.SAXIHP1AWREADY			(),
	.SAXIHP1BID			(),
	.SAXIHP1BRESP			(),
	.SAXIHP1BVALID			(),
	.SAXIHP1RACOUNT			(),
	.SAXIHP1RCOUNT			(),
	.SAXIHP1RDATA			(),
	.SAXIHP1RID			(),
	.SAXIHP1RLAST			(),
	.SAXIHP1RRESP			(),
	.SAXIHP1RVALID			(),
	.SAXIHP1WACOUNT			(),
	.SAXIHP1WCOUNT			(),
	.SAXIHP1WREADY			(),
	.SAXIHP2ARESETN			(),
	.SAXIHP2ARREADY			(),
	.SAXIHP2AWREADY			(),
	.SAXIHP2BID			(),
	.SAXIHP2BRESP			(),
	.SAXIHP2BVALID			(),
	.SAXIHP2RACOUNT			(),
	.SAXIHP2RCOUNT			(),
	.SAXIHP2RDATA			(),
	.SAXIHP2RID			(),
	.SAXIHP2RLAST			(),
	.SAXIHP2RRESP			(),
	.SAXIHP2RVALID			(),
	.SAXIHP2WACOUNT			(),
	.SAXIHP2WCOUNT			(),
	.SAXIHP2WREADY			(),
	.SAXIHP3ARESETN			(),
	.SAXIHP3ARREADY			(),
	.SAXIHP3AWREADY			(),
	.SAXIHP3BID			(),
	.SAXIHP3BRESP			(),
	.SAXIHP3BVALID			(),
	.SAXIHP3RACOUNT			(),
	.SAXIHP3RCOUNT			(),
	.SAXIHP3RDATA			(),
	.SAXIHP3RID			(),
	.SAXIHP3RLAST			(),
	.SAXIHP3RRESP			(),
	.SAXIHP3RVALID			(),
	.SAXIHP3WACOUNT			(),
	.SAXIHP3WCOUNT			(),
	.SAXIHP3WREADY			(),
	.DDRA				(),
	.DDRBA				(),
	.DDRCASB			(),
	.DDRCKE				(),
	.DDRCKN				(),
	.DDRCKP				(),
	.DDRCSB				(),
	.DDRDM				(),
	.DDRDQ				(),
	.DDRDQSN			(),
	.DDRDQSP			(),
	.DDRDRSTB			(),
	.DDRODT				(),
	.DDRRASB			(),
	.DDRVRN				(),
	.DDRVRP				(),
	.DDRWEB				(),
	.MIO				(),
	.PSCLK				(),
	.PSPORB				(),
	.PSSRSTB			(),
	.DDRARB				(%(dout)u),
	.DMA0ACLK			(),
	.DMA0DAREADY			(),
	.DMA0DRLAST			(),
	.DMA0DRTYPE			(),
	.DMA0DRVALID			(),
	.DMA1ACLK			(),
	.DMA1DAREADY			(),
	.DMA1DRLAST			(),
	.DMA1DRTYPE			(),
	.DMA1DRVALID			(),
	.DMA2ACLK			(),
	.DMA2DAREADY			(),
	.DMA2DRLAST			(),
	.DMA2DRTYPE			(),
	.DMA2DRVALID			(),
	.DMA3ACLK			(),
	.DMA3DAREADY			(),
	.DMA3DRLAST			(),
	.DMA3DRTYPE			(),
	.DMA3DRVALID			(),
	.EMIOCAN0PHYRX			(),
	.EMIOCAN1PHYRX			(),
	.EMIOENET0EXTINTIN		(),
	.EMIOENET0GMIICOL		(),
	.EMIOENET0GMIICRS		(),
	.EMIOENET0GMIIRXCLK		(),
	.EMIOENET0GMIIRXD		(),
	.EMIOENET0GMIIRXDV		(),
	.EMIOENET0GMIIRXER		(),
	.EMIOENET0GMIITXCLK		(),
	.EMIOENET0MDIOI			(),
	.EMIOENET1EXTINTIN		(),
	.EMIOENET1GMIICOL		(),
	.EMIOENET1GMIICRS		(),
	.EMIOENET1GMIIRXCLK		(),
	.EMIOENET1GMIIRXD		(),
	.EMIOENET1GMIIRXDV		(),
	.EMIOENET1GMIIRXER		(),
	.EMIOENET1GMIITXCLK		(),
	.EMIOENET1MDIOI			(),
	.EMIOGPIOI			(),
	.EMIOI2C0SCLI			(),
	.EMIOI2C0SDAI			(),
	.EMIOI2C1SCLI			(),
	.EMIOI2C1SDAI			(),
	.EMIOPJTAGTCK			(),
	.EMIOPJTAGTDI			(),
	.EMIOPJTAGTMS			(),
	.EMIOSDIO0CDN			(),
	.EMIOSDIO0CLKFB			(),
	.EMIOSDIO0CMDI			(),
	.EMIOSDIO0DATAI			(),
	.EMIOSDIO0WP			(),
	.EMIOSDIO1CDN			(),
	.EMIOSDIO1CLKFB			(),
	.EMIOSDIO1CMDI			(),
	.EMIOSDIO1DATAI			(),
	.EMIOSDIO1WP			(),
	.EMIOSPI0MI			(),
	.EMIOSPI0SCLKI			(),
	.EMIOSPI0SI			(),
	.EMIOSPI0SSIN			(),
	.EMIOSPI1MI			(),
	.EMIOSPI1SCLKI			(),
	.EMIOSPI1SI			(),
	.EMIOSPI1SSIN			(),
	.EMIOSRAMINTIN			(),
	.EMIOTRACECLK			(),
	.EMIOTTC0CLKI			(),
	.EMIOTTC1CLKI			(),
	.EMIOUART0CTSN			(),
	.EMIOUART0DCDN			(),
	.EMIOUART0DSRN			(),
	.EMIOUART0RIN			(),
	.EMIOUART0RX			(),
	.EMIOUART1CTSN			(),
	.EMIOUART1DCDN			(),
	.EMIOUART1DSRN			(),
	.EMIOUART1RIN			(),
	.EMIOUART1RX			(),
	.EMIOUSB0VBUSPWRFAULT		(),
	.EMIOUSB1VBUSPWRFAULT		(),
	.EMIOWDTCLKI			(),
	.EVENTEVENTI			(),
	.FCLKCLKTRIGN			(),
	.FPGAIDLEN			(),
	.FTMDTRACEINATID		(),
	.FTMDTRACEINCLOCK		(),
	.FTMDTRACEINDATA		(),
	.FTMDTRACEINVALID		(),
	.FTMTF2PDEBUG			(),
	.FTMTF2PTRIG			(),
	.FTMTP2FTRIGACK			(),
	.IRQF2P				(),
	.MAXIGP0ACLK			(),
	.MAXIGP0ARREADY			(),
	.MAXIGP0AWREADY			(),
	.MAXIGP0BID			(),
	.MAXIGP0BRESP			(),
	.MAXIGP0BVALID			(),
	.MAXIGP0RDATA			(),
	.MAXIGP0RID			(),
	.MAXIGP0RLAST			(),
	.MAXIGP0RRESP			(),
	.MAXIGP0RVALID			(),
	.MAXIGP0WREADY			(),
	.MAXIGP1ACLK			(),
	.MAXIGP1ARREADY			(),
	.MAXIGP1AWREADY			(),
	.MAXIGP1BID			(),
	.MAXIGP1BRESP			(),
	.MAXIGP1BVALID			(),
	.MAXIGP1RDATA			(),
	.MAXIGP1RID			(),
	.MAXIGP1RLAST			(),
	.MAXIGP1RRESP			(),
	.MAXIGP1RVALID			(),
	.MAXIGP1WREADY			(),
	.SAXIACPACLK			(),
	.SAXIACPARADDR			(),
	.SAXIACPARBURST			(),
	.SAXIACPARCACHE			(),
	.SAXIACPARID			(),
	.SAXIACPARLEN			(),
	.SAXIACPARLOCK			(),
	.SAXIACPARPROT			(),
	.SAXIACPARQOS			(),
	.SAXIACPARSIZE			(),
	.SAXIACPARUSER			(),
	.SAXIACPARVALID			(),
	.SAXIACPAWADDR			(),
	.SAXIACPAWBURST			(),
	.SAXIACPAWCACHE			(),
	.SAXIACPAWID			(),
	.SAXIACPAWLEN			(),
	.SAXIACPAWLOCK			(),
	.SAXIACPAWPROT			(),
	.SAXIACPAWQOS			(),
	.SAXIACPAWSIZE			(),
	.SAXIACPAWUSER			(),
	.SAXIACPAWVALID			(),
	.SAXIACPBREADY			(),
	.SAXIACPRREADY			(),
	.SAXIACPWDATA			(),
	.SAXIACPWID			(),
	.SAXIACPWLAST			(),
	.SAXIACPWSTRB			(),
	.SAXIACPWVALID			(),
	.SAXIGP0ACLK			(),
	.SAXIGP0ARADDR			(),
	.SAXIGP0ARBURST			(),
	.SAXIGP0ARCACHE			(),
	.SAXIGP0ARID			(),
	.SAXIGP0ARLEN			(),
	.SAXIGP0ARLOCK			(),
	.SAXIGP0ARPROT			(),
	.SAXIGP0ARQOS			(),
	.SAXIGP0ARSIZE			(),
	.SAXIGP0ARVALID			(),
	.SAXIGP0AWADDR			(),
	.SAXIGP0AWBURST			(),
	.SAXIGP0AWCACHE			(),
	.SAXIGP0AWID			(),
	.SAXIGP0AWLEN			(),
	.SAXIGP0AWLOCK			(),
	.SAXIGP0AWPROT			(),
	.SAXIGP0AWQOS			(),
	.SAXIGP0AWSIZE			(),
	.SAXIGP0AWVALID			(),
	.SAXIGP0BREADY			(),
	.SAXIGP0RREADY			(),
	.SAXIGP0WDATA			(),
	.SAXIGP0WID			(),
	.SAXIGP0WLAST			(),
	.SAXIGP0WSTRB			(),
	.SAXIGP0WVALID			(),
	.SAXIGP1ACLK			(),
	.SAXIGP1ARADDR			(),
	.SAXIGP1ARBURST			(),
	.SAXIGP1ARCACHE			(),
	.SAXIGP1ARID			(),
	.SAXIGP1ARLEN			(),
	.SAXIGP1ARLOCK			(),
	.SAXIGP1ARPROT			(),
	.SAXIGP1ARQOS			(),
	.SAXIGP1ARSIZE			(),
	.SAXIGP1ARVALID			(),
	.SAXIGP1AWADDR			(),
	.SAXIGP1AWBURST			(),
	.SAXIGP1AWCACHE			(),
	.SAXIGP1AWID			(),
	.SAXIGP1AWLEN			(),
	.SAXIGP1AWLOCK			(),
	.SAXIGP1AWPROT			(),
	.SAXIGP1AWQOS			(),
	.SAXIGP1AWSIZE			(),
	.SAXIGP1AWVALID			(),
	.SAXIGP1BREADY			(),
	.SAXIGP1RREADY			(),
	.SAXIGP1WDATA			(),
	.SAXIGP1WID			(),
	.SAXIGP1WLAST			(),
	.SAXIGP1WSTRB			(),
	.SAXIGP1WVALID			(),
	.SAXIHP0ACLK			(),
	.SAXIHP0ARADDR			(),
	.SAXIHP0ARBURST			(),
	.SAXIHP0ARCACHE			(),
	.SAXIHP0ARID			(),
	.SAXIHP0ARLEN			(),
	.SAXIHP0ARLOCK			(),
	.SAXIHP0ARPROT			(),
	.SAXIHP0ARQOS			(),
	.SAXIHP0ARSIZE			(),
	.SAXIHP0ARVALID			(),
	.SAXIHP0AWADDR			(),
	.SAXIHP0AWBURST			(),
	.SAXIHP0AWCACHE			(),
	.SAXIHP0AWID			(),
	.SAXIHP0AWLEN			(),
	.SAXIHP0AWLOCK			(),
	.SAXIHP0AWPROT			(),
	.SAXIHP0AWQOS			(),
	.SAXIHP0AWSIZE			(),
	.SAXIHP0AWVALID			(),
	.SAXIHP0BREADY			(),
	.SAXIHP0RDISSUECAP1EN		(),
	.SAXIHP0RREADY			(),
	.SAXIHP0WDATA			(),
	.SAXIHP0WID			(),
	.SAXIHP0WLAST			(),
	.SAXIHP0WRISSUECAP1EN		(),
	.SAXIHP0WSTRB			(),
	.SAXIHP0WVALID			(),
	.SAXIHP1ACLK			(),
	.SAXIHP1ARADDR			(),
	.SAXIHP1ARBURST			(),
	.SAXIHP1ARCACHE			(),
	.SAXIHP1ARID			(),
	.SAXIHP1ARLEN			(),
	.SAXIHP1ARLOCK			(),
	.SAXIHP1ARPROT			(),
	.SAXIHP1ARQOS			(),
	.SAXIHP1ARSIZE			(),
	.SAXIHP1ARVALID			(),
	.SAXIHP1AWADDR			(),
	.SAXIHP1AWBURST			(),
	.SAXIHP1AWCACHE			(),
	.SAXIHP1AWID			(),
	.SAXIHP1AWLEN			(),
	.SAXIHP1AWLOCK			(),
	.SAXIHP1AWPROT			(),
	.SAXIHP1AWQOS			(),
	.SAXIHP1AWSIZE			(),
	.SAXIHP1AWVALID			(),
	.SAXIHP1BREADY			(),
	.SAXIHP1RDISSUECAP1EN		(),
	.SAXIHP1RREADY			(),
	.SAXIHP1WDATA			(),
	.SAXIHP1WID			(),
	.SAXIHP1WLAST			(),
	.SAXIHP1WRISSUECAP1EN		(),
	.SAXIHP1WSTRB			(),
	.SAXIHP1WVALID			(),
	.SAXIHP2ACLK			(),
	.SAXIHP2ARADDR			(),
	.SAXIHP2ARBURST			(),
	.SAXIHP2ARCACHE			(),
	.SAXIHP2ARID			(),
	.SAXIHP2ARLEN			(),
	.SAXIHP2ARLOCK			(),
	.SAXIHP2ARPROT			(),
	.SAXIHP2ARQOS			(),
	.SAXIHP2ARSIZE			(),
	.SAXIHP2ARVALID			(),
	.SAXIHP2AWADDR			(),
	.SAXIHP2AWBURST			(),
	.SAXIHP2AWCACHE			(),
	.SAXIHP2AWID			(),
	.SAXIHP2AWLEN			(),
	.SAXIHP2AWLOCK			(),
	.SAXIHP2AWPROT			(),
	.SAXIHP2AWQOS			(),
	.SAXIHP2AWSIZE			(),
	.SAXIHP2AWVALID			(),
	.SAXIHP2BREADY			(),
	.SAXIHP2RDISSUECAP1EN		(),
	.SAXIHP2RREADY			(),
	.SAXIHP2WDATA			(),
	.SAXIHP2WID			(),
	.SAXIHP2WLAST			(),
	.SAXIHP2WRISSUECAP1EN		(),
	.SAXIHP2WSTRB			(),
	.SAXIHP2WVALID			(),
	.SAXIHP3ACLK			(),
	.SAXIHP3ARADDR			(),
	.SAXIHP3ARBURST			(),
	.SAXIHP3ARCACHE			(),
	.SAXIHP3ARID			(),
	.SAXIHP3ARLEN			(),
	.SAXIHP3ARLOCK			(),
	.SAXIHP3ARPROT			(),
	.SAXIHP3ARQOS			(),
	.SAXIHP3ARSIZE			(),
	.SAXIHP3ARVALID			(),
	.SAXIHP3AWADDR			(),
	.SAXIHP3AWBURST			(),
	.SAXIHP3AWCACHE			(),
	.SAXIHP3AWID			(),
	.SAXIHP3AWLEN			(),
	.SAXIHP3AWLOCK			(),
	.SAXIHP3AWPROT			(),
	.SAXIHP3AWQOS			(),
	.SAXIHP3AWSIZE			(),
	.SAXIHP3AWVALID			(),
	.SAXIHP3BREADY			(),
	.SAXIHP3RDISSUECAP1EN		(),
	.SAXIHP3RREADY			(),
	.SAXIHP3WDATA			(),
	.SAXIHP3WID			(),
	.SAXIHP3WLAST			(),
	.SAXIHP3WRISSUECAP1EN		(),
	.SAXIHP3WSTRB			(),
	.SAXIHP3WVALID			()
	);
    ''' % {
            'dut': 'site_name',
            'dout': isone
        })

    print("endmodule")
    write_params(params)
Beispiel #22
0
def run():
    print('''
module top();
    ''')

    params = {}

    sites = list(gen_brams())
    fuzz_iter = iter(util.gen_fuzz_states(len(sites) * 5))
    for tile_name, bram_sites, int_tiles in sites:
        # Each BRAM tile has 5 INT tiles.
        # The following feature is used to toggle a one PIP in each INT tile
        #
        # For BRAM_L_X6Y0, there are the following INT tiles and the feature
        # to toggle
        #
        #  - INT_L_X6Y0, tie bram_sites[0].DIADI[2] = 0, toggle bram_sites[0].DIADI[3]
        #  - INT_L_X6Y1, tie bram_sites[1].ADDRBWRADDR[7] = 0, toggle bram_sites[1].ADDRBWRADDR[10]
        #  - INT_L_X6Y2, tie bram_sites[1].ADDRARDADDR[9] = 0, toggle bram_sites[1].ADDRBWRADDR[9]
        #  - INT_L_X6Y3, tie bram_sites[1].ADDRBWRADDR[4] = 0, toggle bram_sites[1].ADDRBWRADDR[13]
        #  - INT_L_X6Y4, tie bram_sites[1].DIBDI[15] = 0, toggle bram_sites[1].DIADI[7]
        (b0_diadi3, b1_wraddr10, b1_wraddr9, b1_wraddr13,
         b1_diadi7) = itertools.islice(fuzz_iter, 5)
        params[int_tiles[0]] = (b0_diadi3, )
        params[int_tiles[1]] = (b1_wraddr10, )
        params[int_tiles[2]] = (b1_wraddr9, )
        params[int_tiles[3]] = (b1_wraddr13, )
        params[int_tiles[4]] = (b1_diadi7, )

        print('''
            wire [15:0] {bram_site0}_diadi;
            wire [15:0] {bram_site0}_dibdi;
            wire [13:0] {bram_site0}_wraddr;

            wire [15:0] {bram_site1}_diadi;
            wire [15:0] {bram_site1}_dibdi;
            wire [7:0] {bram_site1}_webwe;
            wire [13:0] {bram_site1}_rdaddr;
            wire [13:0] {bram_site1}_wraddr;

            // INT 0
            assign {bram_site0}_diadi[2] = 0;
            assign {bram_site0}_diadi[3] = {b0_diadi3};

            // INT 1
            assign {bram_site1}_wraddr[7] = 0;
            assign {bram_site1}_wraddr[10] = {b1_wraddr10};

            // INT 2
            assign {bram_site1}_rdaddr[9] = 0;
            assign {bram_site1}_wraddr[9] = {b1_wraddr9};

            // INT 3
            assign {bram_site1}_wraddr[4] = 0;
            assign {bram_site1}_wraddr[13] = {b1_wraddr13};

            // INT 4
            assign {bram_site1}_dibdi[15] = 0;
            assign {bram_site1}_diadi[7] = {b1_diadi7};

            (* KEEP, DONT_TOUCH, LOC = "{bram_site0}" *)
            RAMB18E1 #(
                ) bram_{bram_site0} (
                    .CLKARDCLK(),
                    .CLKBWRCLK(),
                    .ENARDEN(),
                    .ENBWREN(),
                    .REGCEAREGCE(),
                    .REGCEB(),
                    .RSTRAMARSTRAM(),
                    .RSTRAMB(),
                    .RSTREGARSTREG(),
                    .RSTREGB(),
                    .ADDRARDADDR(),
                    .ADDRBWRADDR({bram_site0}_wraddr),
                    .DIADI({bram_site0}_diadi),
                    .DIBDI({bram_site0}_dibdi),
                    .DIPADIP(),
                    .DIPBDIP(),
                    .WEA(),
                    .WEBWE(),
                    .DOADO(),
                    .DOBDO(),
                    .DOPADOP(),
                    .DOPBDOP());

            (* KEEP, DONT_TOUCH, LOC = "{bram_site1}" *)
            RAMB18E1 #(
                ) bram_{bram_site1} (
                    .CLKARDCLK(),
                    .CLKBWRCLK(),
                    .ENARDEN(),
                    .ENBWREN(),
                    .REGCEAREGCE(),
                    .REGCEB(),
                    .RSTRAMARSTRAM(),
                    .RSTRAMB(),
                    .RSTREGARSTREG(),
                    .RSTREGB(),
                    .ADDRARDADDR({bram_site1}_rdaddr),
                    .ADDRBWRADDR({bram_site1}_wraddr),
                    .DIADI({bram_site1}_diadi),
                    .DIBDI({bram_site1}_dibdi),
                    .DIPADIP(),
                    .DIPBDIP(),
                    .WEA(),
                    .WEBWE({bram_site1}_webwe),
                    .DOADO(),
                    .DOBDO(),
                    .DOPADOP(),
                    .DOPBDOP());
'''.format(bram_site0=bram_sites[0],
           bram_site1=bram_sites[1],
           b0_diadi3=b0_diadi3,
           b1_wraddr10=b1_wraddr10,
           b1_wraddr9=b1_wraddr9,
           b1_wraddr13=b1_wraddr13,
           b1_diadi7=b1_diadi7))

    print("endmodule")
    write_params(params)
Beispiel #23
0
def run():
    print('''
module top(input clk, stb, di, output do);
    localparam integer DIN_N = 8;
    localparam integer DOUT_N = 8;

    reg [DIN_N-1:0] din;
    wire [DOUT_N-1:0] dout;

    reg [DIN_N-1:0] din_shr;
    reg [DOUT_N-1:0] dout_shr;

    always @(posedge clk) begin
        din_shr <= {din_shr, di};
        dout_shr <= {dout_shr, din_shr[DIN_N-1]};
        if (stb) begin
            din <= din_shr;
            dout_shr <= dout;
        end
    end

    assign do = dout_shr[DOUT_N-1];
    ''')

    params = {}
    # only one for now, worry about later
    sites = list(gen_sites())
    assert len(sites) == 1, len(sites)
    for (tile_name, site_name), isone in zip(sites,
                                             util.gen_fuzz_states(len(sites))):
        INIT_43 = isone
        params[tile_name] = (site_name, INIT_43)

        print('''
    (* KEEP, DONT_TOUCH *)
    XADC #(/*.LOC("%s"),*/ .INIT_43(%u)) dut_%s(
            .BUSY(),
            .DRDY(),
            .EOC(),
            .EOS(),
            .JTAGBUSY(),
            .JTAGLOCKED(),
            .JTAGMODIFIED(),
            .OT(),
            .DO(),
            .ALM(),
            .CHANNEL(),
            .MUXADDR(),
            .CONVST(),
            .CONVSTCLK(clk),
            .DCLK(clk),
            .DEN(),
            .DWE(),
            .RESET(),
            .VN(),
            .VP(),
            .DI(),
            .VAUXN(),
            .VAUXP(),
            .DADDR());
''' % (site_name, INIT_43, site_name))

    print("endmodule")
    write_params(params)