def unpack(self, buff, offs):
REG1, REG2 = struct.unpack_from('LL', buff, offs)
#print(hex(REG1), hex(REG2), hex(REG3), hex(REG4))
#MAC
mac64 = REG1 | (_FLD2VAL(REG2, ItemMAC_REG2_MAC_Hi16_Pos,
ItemMAC_REG2_MAC_Hi16_Msk) << 32)
self.MAC = ':'.join([
'{:02x}'.format((mac64 >> ele) & 0xff)
for ele in range(0, 8 * 6, 8)
][::-1])
#rest
self.vlanID = _FLD2VAL(REG2, ItemMAC_REG2_VlanID_Pos,
ItemMAC_REG2_VlanID_Msk)
def unpack(self, buff, offs):
#R1, R2, hashAddr = struct.unpack_from('>LLH', buff, offs)
R1, R2 = struct.unpack_from('>LH', buff, offs)
R3, self.HashAddr = struct.unpack_from('HH', buff, offs + 6)
#print(hex(REG1), hex(REG2), hex(REG3), hex(REG4))
#MAC
mac64 = (R1 << 16) | (_FLD2VAL(R2, ItemMAC_R2_MAC_Lo16_Pos,
ItemMAC_R2_MAC_Lo16_Msk))
self.MAC = ':'.join([
'{:02x}'.format((mac64 >> ele) & 0xff)
for ele in range(0, 8 * 6, 8)
][::-1])
#rest
self.Age = _FLD2VAL(R3, ItemMAC_R2_AGE_Pos, ItemMAC_R2_AGE_Msk)
self.Port = _FLD2VAL(R3, ItemMAC_R2_PORT_Pos, ItemMAC_R2_PORT_Msk)
self.IsActive = (R3 & ItemMAC_R2_ACT_Msk) != 0
self.Hash = _FLD2VAL(self.HashAddr, VV3_HashToAddr_Pos,
VV3_HashToAddr_Msk)
self.HashInd = self.HashAddr & VV3_HashInd_Mask
def unpack(self, buff, offs):
#REG0, REG1, REG2 = struct.unpack_from('HLL', buff, offs)
self.key.unpack(buff, offs)
REG1, REG2 = struct.unpack_from('LL', buff, offs + KX028_KeyVLAN.packLen)
#self.key.vlanID = REG0 & ItemVLAN_REG1_VlanID_Msk
self.forwPorts = _FLD2VAL(REG1, EntryVLAN_REG1_ForwPorts_Pos, EntryVLAN_REG1_ForwPorts_Msk)
self.untaggedPorts = _FLD2VAL(REG1, EntryVLAN_REG1_UntagPortsLo_Pos, EntryVLAN_REG1_UntagPortsLo_Msk) \
| (_FLD2VAL(REG2 , EntryVLAN_REG2_UntagPortsHi_Pos, EntryVLAN_REG2_UntagPortsHi_Msk) << EntryVLAN_REG2_UntagPortsHi_Offs)
self.UCastHitAct = _FLD2VAL(REG2, EntryVLAN_REG2_UCastHit_Pos, EntryVLAN_REG2_UCastHit_Msk)
self.MCastHitAct = _FLD2VAL(REG2, EntryVLAN_REG2_MCastHit_Pos, EntryVLAN_REG2_MCastHit_Msk)
self.UCastMissAct = _FLD2VAL(REG2, EntryVLAN_REG2_UCastMiss_Pos, EntryVLAN_REG2_UCastMiss_Msk)
self.MCastMissAct = _FLD2VAL(REG2, EntryVLAN_REG2_MCastMiss_Pos, EntryVLAN_REG2_MCastMiss_Msk)
self.MSTPAct = _FLD2VAL(REG2, EntryVLAN_REG2_MSTP_Pos, EntryVLAN_REG2_MSTP_Msk)
def unpack(self, buff, offs):
self.key.unpack(buff, offs)
(REG3, ) = struct.unpack_from('L', buff, offs + KX028_KeyMAC.packLen)
print(hex(REG3))
#REG3
self.forwPorts = _FLD2VAL(REG3, MAC_ENTRY_FWD_PORT_LIST_Pos,
MAC_ENTRY_FWD_PORT_LIST_Msk)
self.tc = _FLD2VAL(REG3, MAC_ENTRY_TC_Pos, MAC_ENTRY_TC_Msk)
self.action = _FLD2VAL(REG3, MAC_ENTRY_FWD_ACT_Pos,
MAC_ENTRY_FWD_ACT_Msk)
self.cutThrough = _FLD2VAL(REG3, MAC_ENTRY_CUT_THROUGH_Pos,
MAC_ENTRY_CUT_THROUGH_Msk) != 0
self.isFresh = _FLD2VAL(REG3, MAC_ENTRY_FRESH_Pos,
MAC_ENTRY_FRESH_Msk) != 0
self.isStatic = _FLD2VAL(REG3, MAC_ENTRY_STATIC_Pos,
MAC_ENTRY_STATIC_Msk) != 0
def unpack(self, buff, offs):
REG1, REG2, REG3, REG4 = struct.unpack_from('LLLL', buff, offs)
print(hex(REG1), hex(REG2), hex(REG3), hex(REG4))
#REG1
self.vlanID = _FLD2VAL(REG1, ItemVLAN_REG1_VlanID_Pos,
ItemVLAN_REG1_VlanID_Msk)
self.forwPorts = _FLD2VAL(REG1, ItemVLAN_REG1_ForwPortsLo_Pos, ItemVLAN_REG1_ForwPortsLo_Msk) \
| (_FLD2VAL(REG2 , ItemVLAN_REG2_ForwPortsHi_Pos, ItemVLAN_REG2_ForwPortsHi_Msk) << ItemVLAN_REG2_ForwPortsHi_Offs)
#REG2
self.untaggedPorts = _FLD2VAL(REG2, ItemVLAN_REG2_UntagPorts_Pos,
ItemVLAN_REG2_UntagPorts_Msk)
self.UCastHitAct = _FLD2VAL(REG2, ItemVLAN_REG2_UCastHit_Pos,
ItemVLAN_REG2_UCastHit_Msk)
self.MCastHitAct = _FLD2VAL(REG2, ItemVLAN_REG2_MCastHit_Pos,
ItemVLAN_REG2_MCastHit_Msk)
self.UCastMissAct = _FLD2VAL(REG2, ItemVLAN_REG2_UCastMiss_Pos,
ItemVLAN_REG2_UCastMiss_Msk)
self.MCastMissAct = _FLD2VAL(REG2, ItemVLAN_REG2_MCastMissLo_Pos, ItemVLAN_REG2_MCastMissLo_Msk) \
| (_FLD2VAL(REG3 , ItemVLAN_REG3_MCastMissHi_Pos, ItemVLAN_REG3_MCastMissHi_Msk) << ItemVLAN_REG2_MCastMissHi_Offs)
#REG3
self.MSTPAct = _FLD2VAL(REG3, ItemVLAN_REG3_MSTP_Pos,
ItemVLAN_REG3_MSTP_Msk)
self.isValidREG1 = _FLD2VAL(REG3, ItemVLAN_REG3_IsValidREG1_Pos,
ItemVLAN_REG3_IsValidREG1_Msk) != 0
self.isValidREG2 = _FLD2VAL(REG3, ItemVLAN_REG3_IsValidREG2_Pos,
ItemVLAN_REG3_IsValidREG2_Msk) != 0
self.isValidREG3 = _FLD2VAL(REG3, ItemVLAN_REG3_IsValidREG3_Pos,
ItemVLAN_REG3_IsValidREG3_Msk) != 0
self.isValidREG3 = _FLD2VAL(REG3, ItemVLAN_REG3_IsValidREG4_Pos,
ItemVLAN_REG3_IsValidREG4_Msk) != 0
self.isValidREG3 = _FLD2VAL(REG3, ItemVLAN_REG3_IsValidREG5_Pos,
ItemVLAN_REG3_IsValidREG5_Msk) != 0
self.port = _FLD2VAL(REG3, ItemVLAN_REG3_PortNum_Pos,
ItemVLAN_REG3_PortNum_Msk)
self.collizPtr = _FLD2VAL(REG3, ItemVLAN_REG3_CollizPtr_Pos,
ItemVLAN_REG3_CollizPtr_Msk)
#REG4
self.isValidColiz = _FLD2VAL(REG4, ItemVLAN_REG4_IsValidCollPtr_Pos,
ItemVLAN_REG4_IsValidCollPtr_Msk) != 0
self.isActive = _FLD2VAL(REG4, ItemVLAN_REG4_IsActive_Pos,
ItemVLAN_REG4_IsActive_Msk) != 0
def unpackFromRegs(self, REG1, REG2):
self.TPID = _FLD2VAL(REG1, STRUC1_PORT_TPID_Pos, STRUC1_PORT_TPID_Msk)
self.Fallback = _FLD2VAL(REG1, STRUC1_PORT_FALLBACK_BDID_Pos,
STRUC1_PORT_FALLBACK_BDID_Msk)
self.shutDown = _FLD2VAL(REG2, STRUC2_PORT_SHUTDOWN_Pos,
STRUC2_PORT_SHUTDOWN_Msk)
self.AFT = _FLD2VAL(REG2, STRUC2_PORT_AFT_Pos, STRUC2_PORT_AFT_Msk)
self.Blockstate = _FLD2VAL(REG2, STRUC2_PORT_BLOCKSTATE_Pos,
STRUC2_PORT_BLOCKSTATE_Msk)
self.defCFI = _FLD2VAL(REG2, STRUC2_PORT_DEF_CFI_Pos,
STRUC2_PORT_DEF_CFI_Msk)
self.defPRI = _FLD2VAL(REG2, STRUC2_PORT_DEF_PRI_Pos,
STRUC2_PORT_DEF_PRI_Msk)
self.defTC = _FLD2VAL(REG2, STRUC2_PORT_DEF_TC_Pos,
STRUC2_PORT_DEF_TC_Msk)
self.trusted = _FLD2VAL(REG2, STRUC2_PORT_TRUSTED_Pos,
STRUC2_PORT_TRUSTED_Msk)
self.vidPreffix = _FLD2VAL(REG2, STRUC2_PORT_VID_PREFIX_Pos,
STRUC2_PORT_VID_PREFIX_Msk)
self.UntagBTable = _FLD2VAL(REG2, STRUC2_PORT_UNTAG_FROM_BTABLE_Pos,
STRUC2_PORT_UNTAG_FROM_BTABLE_Msk)
def unpack(self, buff, offs):
REG1, REG2, REG3, REG4 = struct.unpack_from('LLLL', buff, offs)
#print(hex(REG1), hex(REG2), hex(REG3), hex(REG4))
#MAC
mac64 = (REG1 << 16) | (_FLD2VAL(REG2, ItemMAC_REG2_MAC_Lo16_Pos,
ItemMAC_REG2_MAC_Lo16_Msk))
self.MAC = ':'.join([
'{:02x}'.format((mac64 >> ele) & 0xff)
for ele in range(0, 8 * 6, 8)
][::-1])
#rest
self.vlanID = _FLD2VAL(REG2, ItemMAC_REG2_VlanID_Pos,
ItemMAC_REG2_VlanID_Msk)
self.forwPorts = _FLD2VAL(REG2, ItemMAC_REG2_PortListL_Pos, ItemMAC_REG2_PortListL_Msk) \
| (_FLD2VAL(REG3 , ItemMAC_REG3_PortListH_Pos, ItemMAC_REG3_PortListH_Msk) << ItemMAC_REG3_ForwPortsHi_Offs)
#REG3
self.tc = _FLD2VAL(REG3, ItemMAC_REG3_TC_Pos, ItemMAC_REG3_TC_Msk)
self.action = _FLD2VAL(REG3, ItemMAC_REG3_Actions_Pos,
ItemMAC_REG3_Actions_Msk)
self.cutThrough = _FLD2VAL(REG3, ItemMAC_REG3_CutThrough_Pos,
ItemMAC_REG3_CutThrough_Msk) != 0
self.isFresh = _FLD2VAL(REG3, ItemMAC_REG3_IsFresh_Pos,
ItemMAC_REG3_IsFresh_Msk) != 0
self.isStatic = _FLD2VAL(REG3, ItemMAC_REG3_IsStatic_Pos,
ItemMAC_REG3_IsStatic_Msk) != 0
self.isValidREG1 = _FLD2VAL(REG3, ItemMAC_REG3_IsValidREG1_Pos,
ItemMAC_REG3_IsValidREG1_Msk) != 0
self.isValidREG2 = _FLD2VAL(REG3, ItemMAC_REG3_IsValidREG2_Pos,
ItemMAC_REG3_IsValidREG2_Msk) != 0
self.isValidREG3 = _FLD2VAL(REG3, ItemMAC_REG3_IsValidREG3_Pos,
ItemMAC_REG3_IsValidREG3_Msk) != 0
self.isValidREG4 = _FLD2VAL(REG3, ItemMAC_REG3_IsValidREG4_Pos,
ItemMAC_REG3_IsValidREG4_Msk) != 0
#REG4
self.isValidREG5 = _FLD2VAL(REG4, ItemMAC_REG4_IsValidREG5_Pos,
ItemMAC_REG4_IsValidREG5_Msk) != 0
self.port = _FLD2VAL(REG4, ItemMAC_REG4_PortNum_Pos,
ItemMAC_REG4_PortNum_Msk)
self.collizPtr = _FLD2VAL(REG4, ItemMAC_REG4_CollizPtr_Pos,
ItemMAC_REG4_CollizPtr_Msk)
self.isValidColiz = _FLD2VAL(REG4, ItemMAC_REG4_IsValidCollPtr_Pos,
ItemMAC_REG4_IsValidCollPtr_Msk) != 0
self.isActive = _FLD2VAL(REG4, ItemMAC_REG4_IsActive_Pos,
ItemMAC_REG4_IsActive_Msk) != 0