def alu_reg_reg_cmp(self, _from_a, _from_b): _value_a = Binary(int(self.Regs[_from_b]), bit_lenght=8, sign_behavior='unsigned') _value_b = Binary(int(self.Regs[_from_a]), bit_lenght=8, sign_behavior='unsigned') _value, of = ops.overflowing_sub(_value_b, _value_a) zf = int(_value) == 0 return zf, of
def alu_reg_reg_sub(self, _from_a, _from_b): _value_a = Binary(int(self.Regs[_from_b]), bit_lenght=8, sign_behavior='unsigned') _value_b = Binary(int(self.Regs[_from_a]), bit_lenght=8, sign_behavior='unsigned') _value, of = ops.overflowing_sub(_value_a, _value_b) self.Regs[_from_b] = _value
def alu_reg_reg_lsh(self, _from_a, _to_b): _value = Binary(int(self.Regs[_from_a]), bit_lenght=8, sign_behavior='unsigned') _value, of = ops.overflowing_lsh(_value, 1) #TODO self.Regs[_to_b] = int(_value)
def alu_reg_dec(self, _from_a): _value = Binary(int(self.Regs[_from_a]), bit_lenght=8, sign_behavior='unsigned') _value, of = ops.overflowing_sub(_value, 1) self.overflow_flag = of self.Regs[_from_a] = _value
def parse_command(self): low = Binary(int(self.RAM[self.ROM_COUNTER]), bit_lenght=8) cu = int(low[4:]) r1 = int(low[:2]) r2 = int(low[2:4]) if cu == 0: r1r2 = int(low[:4]) if r1r2 == 0: print("Shuting with error") self.is_running_flag = False elif r1r2 == 1: self.is_running_flag = False elif r1r2 == 2: self.inc_counter() n1 = int(self.RAM[self.ROM_COUNTER]) self.jump(n1) return elif r1r2 == 3: self.inc_counter() n1 = int(self.RAM[self.ROM_COUNTER]) self.jump_flag(n1) return elif r1r2 == 4: self.interutp(None, None) elif r1r2 == 5: self.clear_screen() else: raise error.EmulationError("Command is not implemented") elif cu == 1: if r2 == 0: self.inc_counter() n1 = int(self.RAM[self.ROM_COUNTER]) self.mov_const_reg(n1, r1) elif r2 == 1: self.alu_reg_inc(r1) elif r2 == 2: self.alu_reg_dec(r1) elif r2 == 3: raise elif cu == 2: self.mov_reg_reg(r2, r1) elif cu == 3: self.alu_reg_reg_add(r2, r1) elif cu == 4: self.alu_reg_reg_sub(r2, r1) elif cu == 5: self.alu_reg_reg_rsh(r2, r1) elif cu == 6: self.alu_reg_reg_lsh(r2, r1) elif cu == 7: self.alu_reg_reg_and(r2, r1) elif cu == 8: self.alu_reg_reg_or(r2, r1) elif cu == 9: self.alu_reg_reg_xor(r2, r1) elif cu == 10: #JUMP EQUAL zf, _ = self.alu_reg_reg_cmp(r2, r1) if zf == True: self.inc_counter() n1 = self.RAM[self.ROM_COUNTER] self.jump(n1) return else: self.inc_counter() elif cu == 11: #JUMP GREATER zf, of = self.alu_reg_reg_cmp(r2, r1) if zf == False and of == True: self.inc_counter() n1 = self.RAM[self.ROM_COUNTER] self.jump(n1) return else: self.inc_counter() elif cu == 12: self.read_reg_pointer(r2, r1) elif cu == 13: self.inc_counter() n1 = self.RAM[self.ROM_COUNTER] self.read_ram_reg(n1, r1) elif cu == 14: self.write_pointer_reg(r1, r2) elif cu == 15: self.inc_counter() n1 = self.RAM[self.ROM_COUNTER] self.write_const_reg(r1, n1) else: raise error.EmulationError("Unreachable") self.inc_counter()