def get_hier_module(self, template_env):
context = self.module_context(template_env)
for child in self.node.local_intfs:
hmod = hdlmod(child)
contents = hmod.get_inst(template_env)
if contents:
context['inst'].append(contents)
for child in self.node.child:
for s in child.meta_kwds['signals']:
if isinstance(s, OutSig):
name = child.params['sigmap'][s.name]
context['inst'].append(f'logic [{s.width-1}:0] {name};')
hmod = hdlmod(child)
if hasattr(hmod, 'get_inst'):
contents = hmod.get_inst(template_env)
if contents:
if hmod.traced:
context['inst'].append('/*verilator tracing_on*/')
context['inst'].append(contents)
if hmod.traced:
context['inst'].append('/*verilator tracing_off*/')
return template_env.render_local(__file__, "hier_module.j2", context)
def basename(self):
basename = self._basename
if self.is_port_intf:
return basename
cnt = 0
for c in self.parent.child:
if hdlmod(c)._basename == basename:
cnt += 1
for c in self.parent.local_intfs:
if c is self.intf:
break
if hdlmod(c)._basename == basename:
cnt += 1
for p in self.parent.out_ports:
if p.basename == basename:
cnt += 1
if cnt == 0:
basename = f'{self._basename}_s'
else:
basename = f'{self._basename}{cnt}_s'
return basename
def Gear(self, node):
hdlgen_inst = hdlmod(node)
if not hdlgen_inst.hierarchical:
return True
for i in node.local_intfs:
hdlgen_map = reg['hdlgen/map']
hdlgen_map[i] = SVIntfGen(i, hdlgen_inst.lang)
def traced(self):
self_traced = any(
fnmatch.fnmatch(self.node.name, p) for p in reg['debug/trace'])
if self.hierarchical:
children_traced = any(
hdlmod(child).traced for child in self.node.child)
else:
children_traced = False
return self_traced or children_traced
def traced(self):
def check(pattern):
if isinstance(pattern, str):
return fnmatch.fnmatch(self.node.name, pattern)
else:
return pattern(self.node)
self_traced = any(check(p) for p in reg['debug/trace'])
if self.hierarchical:
children_traced = any(hdlmod(child).traced for child in self.node.child)
else:
children_traced = False
return self_traced or children_traced
def get_in_port_map_intf_name(self, port, lang):
intf = port.producer
hdlgen_intf = hdlmod(intf)
if len(intf.consumers) == 1:
if lang == 'sv':
return hdlgen_intf.outname
else:
return hdlgen_intf.outname, None
else:
i = intf.consumers.index(port)
if lang == 'sv':
return f'{hdlgen_intf.outname}[{i}]'
else:
return (hdlgen_intf.outname, i)
def get_out_port_map_intf_name(self, port, lang):
basename = hdlmod(port.consumer).basename
if lang == 'sv':
return basename
else:
return basename, None