def test_mapped_directed(sim_cls, din_delay, cfg_delay, dout_delay, branches):
t_ctrl = Uint[bitw(branches - 1)]
ref = [(i, i) for i in range(branches)]
mapping = {}
for i in range(branches):
mapping[i] = (i + 1) if (i + 1) < branches else 0
ctrl = list(range(branches))
seqs = [[(i - 1) if (i - 1) >= 0 else (branches - 1)]
for i in range(branches)]
drvs = [
drv(t=Uint[s[0] + 1], seq=s) | delay_rng(din_delay, din_delay)
for s in seqs
]
directed(drv(t=t_ctrl, seq=ctrl) | delay_rng(cfg_delay, cfg_delay),
*drvs,
f=mux(mapping=mapping, sim_cls=sim_cls),
delays=[delay_rng(dout_delay, dout_delay)],
ref=ref)
sim()
def test_async_over_if_over_async_over_if(lang, din_delay, dout_delay):
@gear
async def test(sel: Bool, din0: Uint,
din1: Uint) -> b'max(din0, din1) * Uint[2]':
async with sel as s:
if s:
async with din1 as d1:
if d1 > 4:
yield d1
else:
async with din0 as d0:
if d0 < 2:
yield d0
elif d0 > 0:
yield d0 * 2
directed(drv(t=Bool, seq=[0, 1, 0, 1, 0, 1, 0, 1]),
drv(t=Uint[4], seq=list(range(4)))
| delay_rng(din_delay, din_delay),
drv(t=Uint[4], seq=list(range(4, 8)))
| delay_rng(din_delay, din_delay),
f=test,
ref=[0, 1, 5, 4, 6, 6, 7])
cosim('/test', 'verilator', lang=lang)
sim(check_activity=False)
def test_directed_3in(cosim_cls, din_delay, dout_delay):
t_deal = Queue[Uint[16], 3]
num = 3
lvl = 2
seq = [[[list(range(3)), list(range(5))],
[list(range(1)), list(range(4)),
list(range(4)), list(range(8))]],
[[list(range(3)), list(range(5)), list(range(1))], [list(range(1)),
list(range(8))], [list(range(4))]],
[[list(range(3)), list(range(1))], [list(range(1))]]]
ref0 = [seq[0][0], seq[1][0], seq[2][0]]
ref1 = [seq[0][1], seq[1][1], seq[2][1]]
ref2 = [seq[1][2]]
ref = [ref0, ref1, ref2]
dout_dly = [delay_rng(dout_delay, dout_delay)] * num
dut = get_dut(dout_delay)
directed(drv(t=t_deal, seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls, lvl=lvl, num=num),
ref=ref,
delays=dout_dly)
sim()
def test_cosim(cosim_cls):
seq = list(range(1, 10))
directed(drv(t=Uint[16], seq=seq) | delay_rng(0, 2),
f=decouple(sim_cls=cosim_cls),
ref=seq,
delays=[delay_rng(0, 2)])
sim()
def test_qfilt_union_delay(cosim_cls, din_delay, dout_delay, sel):
dut = get_dut(dout_delay)
verif(drv(t=queue_din, seq=[directed_seq, directed_seq])
| delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls, fixsel=sel),
ref=filt(name='ref_model', fixsel=sel),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_sim(din_delay, dout_delay):
seq = list(range(1, 10))
directed(drv(t=Uint[16], seq=seq) | delay_rng(din_delay, din_delay),
f=pipe(length=8),
ref=seq,
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_directed_cosim(cosim_cls, din_delay, dout_delay):
dut = get_decoupled_dut(dout_delay, replicate)
verif(drv(t=T_DIN, seq=SEQUENCE) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls),
ref=replicate(name='ref_model'),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_directed_cosim(cosim_cls, lvl, din_delay, dout_delay):
seq = DIR_SEQ
dut = get_dut(dout_delay)
verif(drv(t=T_DIN, seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls, lvl=lvl),
ref=qcnt(name='ref_model', lvl=lvl),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_directed_golden(sim_cls, din_delay, dout_delay):
seq = DIR_SEQ
dut = get_dut(dout_delay)
directed(drv(t=T_DIN, seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=sim_cls),
ref=get_ref(seq),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_cosim():
seq = list(range(1, 10))
directed(drv(t=Uint[16], seq=seq) | delay_rng(0, 2),
f=viv_fifo(depth=16),
ref=seq,
delays=[delay_rng(0, 2)])
cosim('/viv_fifo', 'xsim')
sim()
def test_cosim(cosim_cls, din_delay, dout_delay):
verif(drv(t=Uint[8], seq=[0]) | delay_rng(din_delay, din_delay),
drv(t=Queue[Uint[8]], seq=[list(range(10))])
| delay_rng(din_delay, din_delay),
f=cart(sim_cls=cosim_cls),
ref=cart(name='ref_model'),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_random_cosim(cosim_cls, din_delay, dout_delay):
skip_ifndef('RANDOM_TEST')
seq = RANDOM_SEQ
dut = get_dut(dout_delay)
verif(drv(t=T_DIN, seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls),
ref=qcnt(name='ref_model'),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_random_golden(sim_cls, din_delay, dout_delay):
skip_ifndef('RANDOM_TEST')
seq = RANDOM_SEQ
dut = get_dut(dout_delay)
directed(drv(t=T_DIN, seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=sim_cls),
ref=get_ref(seq),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_cosim(cosim_cls, din_delay, dout_delay):
seq = list(range(1, 10))
dut = get_dut(dout_delay)
directed(drv(t=Uint[16], seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls),
ref=seq,
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_queue_tuple(cosim_cls, din_delay, dout_delay):
seq = [[(0, 1), (4, 0), (1, 1)], [(1, 1), (2, 0), (3, 1), (4, 0)]]
dut = get_dut(dout_delay)
verif(drv(t=Queue[Tuple[Uint[16], Int[2]]], seq=seq)
| delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls),
ref=dreg(name='ref_model'),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_replicate_queue(cosim_cls, din_delay, dout_delay):
dut = get_decoupled_dut(dout_delay, replicate_while)
verif(drv(t=Bool, seq=[1, 1, 0] * 5),
drv(t=Queue[Uint[16]], seq=[list(range(5))])
| delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls),
ref=replicate_while(name='ref_model'),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_cosim_active(cosim_cls, din_delay, dout_delay):
no = 4
dut = get_dut(dout_delay)
verif(drv(t=TDin[Uint[8], no, 4],
seq=[((8, ) * no, 3), ((2, ) * no, 4),
((1, ) * no, 1)]) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls),
ref=serialize(name='ref_model'),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_cosim(din_delay, dout_delay):
from pygears.sim.modules import SimVerilated
seq = list(range(1, 10))
verif(drv(t=Uint[16], seq=seq) | delay_rng(0, din_delay),
f=pipe(name='dut', length=8),
ref=pipe(length=8, sim_cls=SimVerilated),
delays=[delay_rng(0, dout_delay)],
check_timing=True)
sim()
def test_q_directed_two_inputs(sim_cls, din_delay, cfg_delay):
seq1 = [list(range(3)) for _ in range(9)]
seq2 = [list(range(6)) for _ in range(5)]
seq = [seq1, seq2]
directed(drv(t=T_QDIN_SEP, seq=seq) | delay_rng(din_delay, din_delay),
drv(t=T_CFG, seq=[2, 3]) | delay_rng(cfg_delay, cfg_delay),
f=take(sim_cls=sim_cls),
ref=[[list(range(3))] * 2, [list(range(6))] * 3])
sim()
def test_simple_directed(sim_cls, din_delay, dout_delay, branches):
seq = [(i, i) for i in range(branches)]
TDin = Union[tuple(Uint[i] for i in range(1, branches + 1))]
directed(
drv(t=TDin, seq=seq) | delay_rng(din_delay, din_delay),
f=demux(sim_cls=sim_cls),
delays=[delay_rng(dout_delay, dout_delay) for _ in range(branches)],
ref=[[i] for i in range(branches)])
sim()
def test_directed(
cosim_cls,
wr0_delay,
rd0_delay,
wr1_delay,
rd1_delay,
dout_delay,
depth,
):
def wr0_delay_gen():
for _ in range(depth):
yield 0
while True:
yield wr0_delay
w_addr = 3
w_data = 8
wr_req_t = TWrReq[w_addr, Uint[w_data]]
rd_req_t = Uint[w_addr]
req_t = Union[rd_req_t, wr_req_t]
wr0_req_seq = [(i, i * 2) for i in range(depth)]
wr0_init_seq = [(i, 0) for i in range(depth)]
rd0_req_seq = list(range(depth))
rd1_req_seq = list(range(depth))
wr0_req = drv(t=wr_req_t, seq=wr0_init_seq + wr0_req_seq) \
| delay_gen(f=wr0_delay_gen())
rd0_req = drv(t=Uint[w_addr], seq=rd0_req_seq) \
| delay_gen(f=iter([depth])) \
| delay_rng(0, rd0_delay)
req0 = priority_mux(rd0_req, wr0_req)
req1 = ccat(drv(t=Uint[w_addr], seq=rd1_req_seq) \
| req_t.data \
| delay_gen(f=iter([depth])) \
| delay_rng(0, rd1_delay)
, Bool(False)) | req_t
verif(req0,
req1,
f=tdp(name='dut', sim_cls=cosim_cls, depth=depth),
ref=tdp(depth=depth),
delays=[delay_rng(0, dout_delay),
delay_rng(0, 0)])
sim()
def test_uint_3(cosim_cls, din_delay, dout_delay):
directed(drv(t=Uint[2], seq=[0, 1, 2, 3])
| delay_rng(din_delay[0], din_delay[0]),
drv(t=Uint[3], seq=[4, 5, 6, 7])
| delay_rng(din_delay[1], din_delay[1]),
drv(t=Uint[8], seq=[8, 9, 10, 11])
| delay_rng(din_delay[2], din_delay[2]),
f=ccat(sim_cls=cosim_cls),
ref=[(0, 4, 8), (1, 5, 9), (2, 6, 10), (3, 7, 11)],
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_q_directed(sim_cls, delay, dout_delay):
seq1 = [[(j, 2) for j in range(3)] for _ in range(9)]
seq2 = [[(j, 3) for j in range(6)] for _ in range(5)]
seq = [seq1, seq2]
dut = get_dut(dout_delay)
directed(drv(t=T_QDIN, seq=seq) | delay_rng(delay, delay),
f=dut(sim_cls=sim_cls),
ref=[[list(range(3))] * 2, [list(range(6))] * 3],
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_queue_3(cosim_cls, din_delay, dout_delay):
verif(drv(t=Queue[Uint[2]], seq=[[0, 1], [2, 3]])
| delay_rng(din_delay[0], din_delay[0]),
drv(t=Queue[Uint[3]], seq=[[4, 5], [6, 7]])
| delay_rng(din_delay[1], din_delay[1]),
drv(t=Queue[Uint[8]], seq=[[8, 9], [10, 11]])
| delay_rng(din_delay[2], din_delay[2]),
f=ccat(sim_cls=cosim_cls),
ref=ccat(name='ref_model'),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_cosim(cosim_cls, din_delay, dout_delay):
brick_size = 4
seq_list = [1, 2, 3, 4]
dut = get_dut(dout_delay)
verif(drv(t=Array[Uint[16], brick_size],
seq=[(i, ) * brick_size
for i in seq_list]) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls),
ref=serialize(name='ref_model'),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_tuple_uint_directed(sim_cls, din_delay, cfg_delay, dout_delay):
t_ctrl = Uint[4]
t_din = Tuple[Uint[8], Uint[8], Uint[8]]
dut = get_decoupled_dut(dout_delay, field_mux)
directed(drv(t=t_ctrl, seq=[0, 1, 2])
| delay_rng(cfg_delay, cfg_delay),
drv(t=t_din, seq=[(5, 6, 7), (5, 6, 7), (5, 6, 7)])
| delay_rng(din_delay, din_delay),
f=dut(sim_cls=sim_cls),
ref=[(5, 0), (6, 1), (7, 2)],
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_directed(cosim_cls, din_delay, dout_delay):
seq = [[list(range(8)), list(range(2)), list(range(3))], [list(range(1)), list(range(2))]]
ref0 = [seq[0][0], seq[0][2], seq[1][0]]
ref1 = [seq[0][1], seq[1][1]]
ref = [ref0, ref1]
dut = get_dut(dout_delay)
directed(drv(t=T_TRR_DIST, seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls, num=2),
ref=ref,
delays=[delay_rng(dout_delay, dout_delay),
delay_rng(dout_delay, dout_delay)])
sim()
def test_cosim_zipsync_both_queue(cosim_cls, din0_delay, din1_delay,
dout0_delay, dout1_delay):
verif(drv(t=Queue[Uint[8], 2], seq=[[list(range(10)) for _ in range(2)]])
| delay_rng(din0_delay, din0_delay),
drv(t=Queue[Uint[8], 2], seq=[[list(range(10)) for _ in range(2)]])
| delay_rng(din1_delay, din1_delay),
f=zip_sync(sim_cls=cosim_cls),
ref=zip_sync(name='ref_model'),
delays=[
delay_rng(dout0_delay, dout0_delay),
delay_rng(dout1_delay, dout1_delay)
])
sim()
def test_qfilt_delay(cosim_cls, din_delay, dout_delay):
@datagear
def even(x: Integer) -> Bool:
return not x[0]
directed(drv(t=Queue[Uint[8]], seq=[list(range(10)),
list(range(10))])
| delay_rng(din_delay, din_delay),
f=filt(sim_cls=cosim_cls, f=even),
ref=[list(range(0, 10, 2)),
list(range(0, 10, 2))],
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_intf_vararg_mux(sim_cls, din_delay, dout_delay):
@gear
async def test(*din: Uint) -> b'din[0]':
async with mux(0, *din) as d:
yield code(d[0], Uint[4])
directed(drv(t=Uint[4], seq=list(range(4)))
| delay_rng(din_delay, din_delay),
drv(t=Uint[4], seq=list(range(4, 8)))
| delay_rng(din_delay, din_delay),
f=test(sim_cls=sim_cls),
delays=[delay_rng(dout_delay, dout_delay)],
ref=list(range(4)))
sim(check_activity=False)
