def test_directed_3in(cosim_cls, din_delay, dout_delay):
t_deal = Queue[Uint[16], 3]
num = 3
lvl = 2
seq = [[[list(range(3)), list(range(5))],
[list(range(1)), list(range(4)),
list(range(4)), list(range(8))]],
[[list(range(3)), list(range(5)), list(range(1))], [list(range(1)),
list(range(8))], [list(range(4))]],
[[list(range(3)), list(range(1))], [list(range(1))]]]
ref0 = [seq[0][0], seq[1][0], seq[2][0]]
ref1 = [seq[0][1], seq[1][1], seq[2][1]]
ref2 = [seq[1][2]]
ref = [ref0, ref1, ref2]
dout_dly = [delay_rng(dout_delay, dout_delay)] * num
dut = get_dut(dout_delay)
directed(drv(t=t_deal, seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls, lvl=lvl, num=num),
ref=ref,
delays=dout_dly)
sim()
def test_mapped_directed(sim_cls, din_delay, cfg_delay, dout_delay, branches):
t_ctrl = Uint[bitw(branches - 1)]
ref = [(i, i) for i in range(branches)]
mapping = {}
for i in range(branches):
mapping[i] = (i + 1) if (i + 1) < branches else 0
ctrl = list(range(branches))
seqs = [[(i - 1) if (i - 1) >= 0 else (branches - 1)]
for i in range(branches)]
drvs = [
drv(t=Uint[s[0] + 1], seq=s) | delay_rng(din_delay, din_delay)
for s in seqs
]
directed(drv(t=t_ctrl, seq=ctrl) | delay_rng(cfg_delay, cfg_delay),
*drvs,
f=mux(mapping=mapping, sim_cls=sim_cls),
delays=[delay_rng(dout_delay, dout_delay)],
ref=ref)
sim()
def test_add():
directed(drv(t=Uint[8], seq=list(range(8))),
drv(t=Uint[8], seq=list(range(8))),
f=add(sim_cls=SimVerilated),
ref=[2 * i for i in range(8)])
sim()
def test_directed(sim_cls, div):
seq = list(range(256 - div))
ref = [math.ceil(x / div) for x in seq]
directed(drv(t=Uint[8], seq=seq),
f=iceil(sim_cls=sim_cls, div=div),
ref=ref)
sim()
def test_directed_active(sim_cls):
no = 4
directed(drv(t=TDin[Uint[8], no, 4],
seq=[((8, ) * no, 3), ((2, ) * no, 4), ((1, ) * no, 1)]),
f=serialize(sim_cls=sim_cls),
ref=[[8] * 3, [2] * 4, [1]])
sim()
def test_same_lvl(sim_cls):
ref = [[[0, 1]] for _ in range(8)]
directed(drv(t=Queue[Uint[8]], seq=[[0, 1] for _ in range(8)]),
f=qdeal(num=8, lvl=1),
ref=ref)
sim()
def test_pygears_sim():
seq = list(range(10))
directed(drv(t=Uint[16], seq=seq), f=dreg, ref=seq)
sim()
assert timestep() == len(seq) + 2
def test_cosim(cosim_cls):
seq = list(range(1, 10))
directed(drv(t=Uint[16], seq=seq) | delay_rng(0, 2),
f=decouple(sim_cls=cosim_cls),
ref=seq,
delays=[delay_rng(0, 2)])
sim()
def test_sim(din_delay, dout_delay):
seq = list(range(1, 10))
directed(drv(t=Uint[16], seq=seq) | delay_rng(din_delay, din_delay),
f=pipe(length=8),
ref=seq,
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_directed_golden(sim_cls, din_delay, dout_delay):
seq = DIR_SEQ
dut = get_dut(dout_delay)
directed(drv(t=T_DIN, seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=sim_cls),
ref=get_ref(seq),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_unsigned_overflow(sim_cls):
seq = [(0x1, 0xf), (0x2, 0xe), (0x3, 0xd)]
directed(drv(t=Tuple[Uint[2], Uint[4]], seq=seq),
f=max2(sim_cls=sim_cls),
ref=[0xf, 0xe, 0xd])
sim()
def test_signed_cosim(sim_cls):
seq = [(0x1, 0x7), (-0x2, 0x7), (0x1, -0x8), (-0x2, -0x8)]
directed(drv(t=Tuple[Int[2], Int[4]], seq=seq),
f=max2(sim_cls=sim_cls),
ref=[0x7, 0x7, 0x1, -0x2])
sim()
def test_signed_unsigned(sim_cls):
seq = [(0x1, 0xf), (-0x2, 0xf), (0x1, 0x0), (-0x2, 0x0)]
directed(drv(t=Tuple[Int[2], Uint[4]], seq=seq),
f=max2(sim_cls=sim_cls),
ref=[0xf, 0xf, 0x1, 0x0])
sim()
def test_cosim():
seq = list(range(1, 10))
directed(drv(t=Uint[16], seq=seq) | delay_rng(0, 2),
f=viv_fifo(depth=16),
ref=seq,
delays=[delay_rng(0, 2)])
cosim('/viv_fifo', 'xsim')
sim()
def test_random_golden(sim_cls, din_delay, dout_delay):
skip_ifndef('RANDOM_TEST')
seq = RANDOM_SEQ
dut = get_dut(dout_delay)
directed(drv(t=T_DIN, seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=sim_cls),
ref=get_ref(seq),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_directed_list(sim_cls):
data = list(range(100, 110))
addr = list(range(10))
directed(drv(t=Uint[5], seq=addr),
f=rom(sim_cls=sim_cls, data=data, dtype=Uint[8]),
ref=data)
sim()
def test_cosim(cosim_cls, din_delay, dout_delay):
seq = list(range(1, 10))
dut = get_dut(dout_delay)
directed(drv(t=Uint[16], seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls),
ref=seq,
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_cosim_all_init(feedback):
from pygears.sim.modules import SimVerilated
seq = list(range(1, 10))
ref = [0] * 8 + seq
directed(drv(t=Uint[16], seq=seq),
f=pipeline(length=8, init=0, feedback=feedback, sim_cls=SimVerilated),
ref=ref)
sim()
def test_array(cosim_cls, din_delay, dout_delay, size):
ref = [list(range(i * size, (i + 1) * size)) for i in range(255 // size)]
dut = get_decoupled_dut(dout_delay, parallelize(t=Array[Uint[8], size]))
directed(drv(t=Uint[8], seq=itertools.chain(*ref)),
f=dut(name='dut', sim_cls=cosim_cls),
ref=ref,
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_hier(cosim_cls):
@gear
def const_sub(din):
return din - 1
directed(drv(t=Uint[4], seq=[1, 2, 3]),
f=const_sub(sim_cls=cosim_cls),
ref=[0, 1, 2])
sim()
def test_directed(sim_cls):
brick_size = 4
seq_list = [1, 2, 3, 4]
directed(drv(t=Array[Uint[16], brick_size],
seq=[(i, ) * brick_size for i in seq_list]),
f=serialize(sim_cls=sim_cls),
ref=[(i, ) * brick_size for i in seq_list])
sim()
def test__rmul__(sim_cls):
# Uint __mul__ raises NotImplemented, so __rmul__ of Ufixp needs to be
# invoked
directed(
drv(t=Uint[8], seq=[128]),
drv(t=Ufixp[0, 8], seq=[0.5]),
f=mul,
ref=[64],
)
sim()
def test_random(sim_cls):
skip_ifndef('RANDOM_TEST')
seq = [[list(range(random.randint(1, 10))),
list(range(random.randint(1, 5)))],
[list(range(random.randint(1, 20))),
list(range(random.randint(1, 7)))]]
directed(drv(t=T_TRR_DIST, seq=seq), f=qdeal(sim_cls=sim_cls, num=2), ref=get_refs(seq))
sim()
def test_directed_dict(sim_cls):
addr = list(range(0, 20, 2))
data = {i: i + 100 for i in addr}
res = list(data.values())
directed(drv(t=Uint[8], seq=addr),
f=rom(sim_cls=sim_cls, data=data, dtype=Uint[8]),
ref=res)
sim()
def test_directed_dict_dflt(sim_cls):
addr = list(range(0, 20, 2))
data = {i: i + 100 for i in addr}
res = [data[i] if i in data else 0 for i in range(20)]
directed(drv(t=Uint[8], seq=range(20)),
f=rom(sim_cls=sim_cls, data=data, dtype=Uint[8], dflt=0),
ref=res)
sim()
def test_uint(cosim_cls, din_delay, dout_delay):
size = 8
ref = [Uint[size](0x11), Uint[size](0x22), Uint[size](0x33)]
dut = get_decoupled_dut(dout_delay, parallelize(t=Uint[size]))
directed(drv(t=Bool, seq=itertools.chain(*ref)),
f=dut(name='dut', sim_cls=cosim_cls),
ref=ref,
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_directed(sim_cls):
wr_addr_data = [(i, i * 2) for i in range(4)]
rd_addr = list(range(4))
rd_data = [i * 2 for i in range(4)]
directed(drv(t=Tuple[Uint[3], Uint[5]], seq=wr_addr_data),
drv(t=Uint[3], seq=rd_addr) | delay_rng(1, 1),
f=sdp(sim_cls=sim_cls, depth=4, latency=2),
ref=rd_data)
sim()
def test_fixp_diff_arith(sim_cls):
@gear(hdl={'compile': True})
async def fixp_arith(x: Fixpnumber, y: Fixpnumber) -> Ufixp[6, 9]:
async with gather(x, y) as data:
yield (data[0] + data[1]) + (data[0] + data[1])
directed(drv(t=Ufixp[4, 7], seq=[3.125]),
drv(t=Ufixp[4, 6], seq=[2.25]),
f=fixp_arith(sim_cls=sim_cls),
ref=[Ufixp[6, 9](10.75)])
sim()
def test_sim_prefil(sim_cls):
rd_addr = list(range(4))
mem = {i: 2 * i for i in rd_addr}
rd_data = [mem[i] for i in rd_addr]
directed(drv(t=Tuple[Uint[3], Uint[5]], seq=[]),
drv(t=Uint[3], seq=rd_addr),
f=sdp(sim_cls=sim_cls, depth=4, mem=mem),
ref=rd_data)
sim()
def test_channeling():
@gear
def dut(din):
return din \
| bc_sig(sigmap={'dout_sig': 'sig'}) \
| add_wrap(sigmap={'din_sig': 'sig'})
directed(drv(t=Uint[16], seq=list(range(3))),
f=dut(sim_cls=SimVerilated),
ref=(list(range(0, 6, 2))))
sim()