def test_random_golden(sim_cls, din_delay, dout_delay):
skip_ifndef('RANDOM_TEST')
seq = RANDOM_SEQ
dut = get_dut(dout_delay)
directed(drv(t=T_DIN, seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=sim_cls),
ref=get_ref(seq),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_random_cosim(cosim_cls, din_delay, dout_delay):
skip_ifndef('RANDOM_TEST')
seq = RANDOM_SEQ
dut = get_dut(dout_delay)
verif(drv(t=T_DIN, seq=seq) | delay_rng(din_delay, din_delay),
f=dut(sim_cls=cosim_cls),
ref=qcnt(name='ref_model'),
delays=[delay_rng(dout_delay, dout_delay)])
sim()
def test_extern_design(tmpdir):
skip_ifndef('SYNTH_TEST')
test_dir = os.path.dirname(__file__)
ipgen(
'vivado',
design=os.path.join(test_dir, 'design.py'),
top='/qdeal',
outdir=tmpdir,
build=True)
def test_random(sim_cls):
skip_ifndef('RANDOM_TEST')
seq = [[list(range(random.randint(1, 10))),
list(range(random.randint(1, 5)))],
[list(range(random.randint(1, 20))),
list(range(random.randint(1, 7)))]]
directed(drv(t=T_TRR_DIST, seq=seq), f=qdeal(sim_cls=sim_cls, num=2), ref=get_refs(seq))
sim()
def cast_cosim_test(src_type, cast_type, seq, expected, module=cast_gear):
skip_ifndef('VERILATOR_ROOT')
report = verif(drv(t=src_type, seq=seq),
f=module(sim_cls=SimVerilated, t=cast_type),
ref=module(name='ref_model', t=cast_type),
make_report=True)
sim()
for e, rep in zip(expected, report[0]):
assert e == rep['items'][0]
def test_pysim_dir(sel, din_t, seq, sim_cls):
if seq == 'rand':
skip_ifndef('RANDOM_TEST')
seq = [(random.randint(1, 100), random.randint(0, 2))
for _ in range(random.randint(10, 50))]
if typeof(din_t, Queue):
queue_filt_test(din_t, seq, sel, sim_cls)
elif typeof(din_t, Union):
filt_test(din_t, seq, sel, sim_cls)
else:
filt_by_test(din_t, seq, sel, sim_cls)
def test_makefile(tmpdir):
skip_ifndef('SYNTH_TEST')
test_dir = os.path.dirname(__file__)
ipgen(
'vivado',
design=os.path.join(test_dir, 'design.py'),
top='/qdeal',
outdir=tmpdir,
build=False,
generate=False)
os.system(f'cd {tmpdir}; make')
def test_socket_rand_cons():
skip_ifndef('SIM_SOCKET_TEST', 'RANDOM_TEST')
cons = []
cons.append(
randomize(T_DIN,
'din',
eot_cons=['data_size == 50', 'trans_lvl1[0] == 4']))
verif(drv(t=T_DIN, seq=rand_seq('din', 30)),
f=qcnt(sim_cls=partial(SimSocket, run=True)),
ref=qcnt(name='ref_model'))
sim(extens=[partial(SVRandSocket, cons=cons)])
def test_extern_design(tmpdir):
skip_ifndef('SYNTH_TEST')
test_dir = os.path.dirname(__file__)
report = synth(
'vivado',
design=os.path.join(test_dir, 'design.py'),
top='/qdeal',
outdir=tmpdir,
util=True,
build=True)
assert 'util' in report
def test_random_constrained():
skip_ifndef('SIM_SOCKET_TEST', 'RANDOM_TEST')
cnt = 5
# cons.append(randomize(T_CFG, 'cfg', cons=['cfg == 2']))
stim = []
stim.append(drv(t=T_DIN_SEP, seq=randomize(T_DIN_SEP, 'din', cnt=cnt)))
stim.append(
drv(t=T_CFG, seq=randomize(T_CFG, 'cfg', cons=['cfg < 20', 'cfg > 0'], cnt=cnt)))
verif(*stim, f=clip, ref=clip(name='ref_model'))
cosim('/clip', 'xsim', run=False)
sim()
def test_random(cosim_cls):
skip_ifndef('RANDOM_TEST')
cfg_seq = []
din_seq = []
cfg_num = random.randint(2, 10)
for _ in range(cfg_num):
cfg_seq.append(random.randint(1, 10))
din_seq.append(list(range(random.randint(1, 10))))
verif(
drv(t=T_DIN_SEP, seq=din_seq),
drv(t=T_CFG, seq=cfg_seq),
f=clip(sim_cls=cosim_cls),
ref=clip(name='ref_model'))
sim()
def test_socket_cosim_rand():
skip_ifndef('SIM_SOCKET_TEST', 'RANDOM_TEST')
din_num = 3
cons = []
for i in range(din_num):
cons.append(randomize(T_DIN, f'din{i}', eot_cons=['data_size == 10']))
stim = []
for i in range(din_num):
stim.append(drv(t=T_DIN, seq=rand_seq(f'din{i}', 30)))
verif(*stim,
f=qinterlace(sim_cls=partial(SimSocket, run=True)),
ref=qinterlace(name='ref_model'))
sim(extens=[partial(SVRandSocket, cons=cons)])
def test_socket_rand_cons():
skip_ifndef('SIM_SOCKET_TEST', 'RANDOM_TEST')
cnt = 5
cons = []
cons.append(randomize(t_din, 'din', eot_cons=['data_size == 20']))
cons.append(randomize(t_cfg, 'cfg', cons=['cfg < 20', 'cfg > 0']))
stim = []
stim.append(drv(t=t_din, seq=rand_seq('din', cnt)))
stim.append(drv(t=t_cfg, seq=rand_seq('cfg', cnt)))
verif(*stim,
f=chop(sim_cls=partial(SimSocket, run=True)),
ref=chop(name='ref_model'))
sim(extens=[partial(SVRandSocket, cons=cons)])
def test_random(sim_cls):
skip_ifndef('RANDOM_TEST')
din_num = 3
stim = []
for _ in range(din_num):
stim.append(
drv(t=T_DIN,
seq=[
list(range(random.randint(1, 10))),
list(range(random.randint(1, 10)))
]))
verif(*stim,
f=qinterlace(sim_cls=sim_cls),
ref=qinterlace(name='ref_model'))
sim()
def test_open_rand_cons():
skip_ifndef('VERILATOR_ROOT', 'SCV_HOME', 'RANDOM_TEST')
cnt = 5
cons = []
# TODO : queue constraints not yet supported in SCVRand
# cons.append(randomize(t_din, 'din', eot_cons=['data_size == 20']))
cons.append(randomize(t_cfg, 'cfg', cons=['cfg < 20', 'cfg > 0']))
stim = []
din_seq = []
for i in range(cnt):
din_seq.append(list(range(random.randint(1, 10))))
stim.append(drv(t=t_din, seq=din_seq))
# stim.append(drv(t=t_din, seq=rand_seq('din', cnt)))
stim.append(drv(t=t_cfg, seq=rand_seq('cfg', cnt)))
verif(*stim, f=chop(sim_cls=SimVerilated), ref=chop(name='ref_model'))
sim(extens=[partial(SCVRand, cons=cons)])
def test_random(sim_cls):
skip_ifndef('RANDOM_TEST')
stim = get_stim()
verif(*stim, f=chop(sim_cls=sim_cls), ref=chop(name='ref_model'))
sim()
from pygears.definitions import ROOT_DIR
from pygears.sim import sim
from pygears.lib.verif import drv
from pygears.sim.modules.sim_socket import SimSocket
from pygears.typing import Queue, Tuple, Uint
# import sys
# sys.path.append('/data/projects/pygears/tests')
from pygears.util.test_utils import prepare_result_dir, skip_ifndef
test_single_word_data_cmake = """
cmake_minimum_required (VERSION 2.6)
project (sock)
add_executable(sock sock.c main.c)
"""
skip_ifndef('INCLUDE_SLOW_TESTS')
def build_sock_echo_app(resdir):
os.chdir(os.path.dirname(os.path.abspath(__file__)))
shutil.copy(os.path.join(ROOT_DIR, 'sim', 'dpi', 'sock.c'), resdir)
shutil.copy(os.path.join(ROOT_DIR, 'sim', 'dpi', 'svdpi.h'), resdir)
shutil.copy(os.path.join(ROOT_DIR, 'sim', 'dpi', 'sock.h'), resdir)
shutil.copy(
os.path.join('test_socket_core_main.c'), os.path.join(
resdir, 'main.c'))
with open(os.path.join(resdir, 'CMakeLists.txt'), 'w') as f: