def __init__(self):
super().__init__()
self.name = ""
self.jump = []
self.jump_start = riscv_instr()
self.jump_end = riscv_instr()
self.num_of_jump_instr = vsc.rand_int_t()
def gen_pop_stack_instr(self, stack_len, saved_regs):
self.stack_len = stack_len
self.saved_regs = saved_regs
self.init()
self.gen_instr(1)
self.pop_stack_instr = [0] * (self.num_of_reg_to_save + 1)
for i in range(len(self.pop_stack_instr)):
self.pop_stack_instr[i] = riscv_instr()
for i in range(len(self.saved_regs)):
if rcs.XLEN == 32:
self.pop_stack_instr[i] = riscv_instr.get_instr(riscv_instr_name_t.LW)
with self.pop_stack_instr[i].randomize_with():
self.pop_stack_instr[i].rd == self.saved_regs[i]
self.pop_stack_instr[i].rs1 == cfg.sp
self.pop_stack_instr[i].imm == 4 * (i + 1)
else:
self.pop_stack_instr[i] = riscv_instr.get_instr(riscv_instr_name_t.LD)
with self.pop_stack_instr[i].randomize_with():
self.pop_stack_instr[i].rd == self.saved_regs[i]
self.pop_stack_instr[i].rs1 == cfg.sp
self.pop_stack_instr[i].imm == 8 * (i + 1)
self.pop_stack_instr[i].process_load_store = 0
# addi sp,sp,imm
self.pop_stack_instr[self.num_of_reg_to_save] = riscv_instr.get_instr(
riscv_instr_name_t.ADDI)
with self.pop_stack_instr[self.num_of_reg_to_save].randomize_with():
self.pop_stack_instr[self.num_of_reg_to_save].rd == cfg.sp
self.pop_stack_instr[self.num_of_reg_to_save].rs1 == cfg.sp
self.pop_stack_instr[self.num_of_reg_to_save].imm == self.stack_len
self.pop_stack_instr[self.num_of_reg_to_save].imm_str = pkg_ins.format_string(
'{}'.format(self.stack_len))
self.mix_instr_stream(self.pop_stack_instr)
for i in range(len(self.instr_list)):
self.instr_list[i].atomic = 1
self.instr_list[i].has_label = 0
def __init__(self):
super().__init__()
self.stack_len = 0
self.num_of_reg_to_save = 0
self.num_of_redundant_instr = 0
self.pop_stack_instr = vsc.list_t(vsc.attr(riscv_instr()))
self.saved_regs = []
def gen_pop_stack_instr(self, stack_len, saved_regs):
self.stack_len = stack_len
self.saved_regs = saved_regs
self.init()
self.gen_instr(1)
self.pop_stack_instr = [None] * (self.num_of_reg_to_save + 1)
for i in range(len(self.pop_stack_instr)):
self.pop_stack_instr[i] = riscv_instr()
for i in range(len(self.saved_regs)):
if rcs.XLEN == 32:
self.pop_stack_instr[i] = riscv_instr_ins.get_instr(riscv_instr_name_t.LW.name)
with self.pop_stack_instr[i].randomize_with() as it:
self.rd == self.saved_regs[i]
self.rs1 == cfg.sp
self.imm == 4 * (i + 1)
else:
self.pop_stack_instr[i] = riscv_instr_ins.get_instr(riscv_instr_name_t.LD.name)
with self.pop_stack_instr[i].randomize_with() as it:
self.rd == self.saved_regs[i]
self.rs1 == cfg.sp
self.imm == 8 * (i + 1)
self.pop_stack_instr[i].process_load_store = 0
# addi sp,sp,imm
self.pop_stack_instr[self.num_of_reg_to_save] = riscv_instr_ins.get_instr(
riscv_instr_name_t.ADDI.name)
''' TODO `DV_CHECK_RANDOMIZE_WITH_FATAL(pop_stack_instr[num_of_reg_to_save],
rd == cfg.sp; rs1 == cfg.sp; imm == stack_len;) '''
self.pop_stack_instr[self.num_of_reg_to_save].imm_str = pkg_ins.format_string(
'{}', self.stack_len)
self.mix_instr_stream(self.pop_stack_instr)
for i in range(len(self.instr_list)):
self.instr_list[i].atomic = 1
self.instr_list[i].has_label = 0
def add_mixed_instr(self, instr_cnt):
self.setup_allowed_instr(no_branch = 1, no_load_store = 1)
for i in range(instr_cnt):
instr = riscv_instr()
instr = self.randomize_instr(instr, include_group = [riscv_instr_group_t.RV32I,
riscv_instr_group_t.RV32C])
if instr.category not in [riscv_instr_category_t.SYSTEM, riscv_instr_category_t.SYNCH]:
self.insert_instr(instr)
def __init__(self):
super().__init__()
self.stack_len = 0
self.num_of_reg_to_save = 0
self.num_of_redundant_instr = 0
self.push_stack_instr = []
self.saved_regs = []
self.branch_instr = vsc.attr(riscv_instr())
self.enable_branch = vsc.rand_bit_t(1)
self.push_start_label = ''
def gen_push_stack_instr(self, stack_len, allow_branch=1):
self.stack_len = stack_len
self.init()
self.push_stack_instr = [0] * (self.num_of_reg_to_save + 1)
for i in range(len(self.push_stack_instr)):
self.push_stack_instr[i] = riscv_instr()
self.push_stack_instr[0] = \
riscv_instr.get_instr(riscv_instr_name_t.ADDI.name)
with self.push_stack_instr[0].randomize_with() as it:
self.push_stack_instr[0].rd == cfg.sp
self.push_stack_instr[0].rs1 == cfg.sp
self.push_stack_instr[0].imm == (~cfg.stack_len + 1)
self.push_stack_instr[0].imm_str = '-{}'.format(self.stack_len)
for i in range(len(self.saved_regs)):
if rcs.XLEN == 32:
self.push_stack_instr[i + 1] = riscv_instr.get_instr(
riscv_instr_name_t.SW.name)
with self.push_stack_instr[i + 1].randomize_with() as it:
self.push_stack_instr[i + 1].rs2 == self.saved_regs[i]
self.push_stack_instr[i + 1].rs1 == cfg.sp
self.push_stack_instr[i + 1].imm == 4 * (i + 1)
else:
self.push_stack_instr[i + 1] = riscv_instr.get_instr(
riscv_instr_name_t.SD.name)
with self.push_stack_instr[i + 1].randomize_with() as it:
self.push_stack_instr[i + 1].rs2 == self.saved_regs[i]
self.push_stack_instr[i + 1].rs1 == cfg.sp
self.push_stack_instr[i + 1].imm == 8 * (i + 1)
self.push_stack_instr[i + 1].process_load_store = 0
if allow_branch:
# TODO
# vsc.randomize(self.enable_branch)
pass
else:
self.enable_branch = 0
if self.enable_branch:
self.branch_instr = \
riscv_instr.get_rand_instr(include_category=[riscv_instr_name_t.BRANCH.name])
self.branch_instr.randomize()
self.branch_instr.imm_str = self.push_start_label
self.branch_instr.brach_assigned = 1
self.push_stack_instr[0].label = self.push_start_label
self.push_stack_instr[0].has_label = 1
self.branch_instr.extend(self.push_stack_instr)
self.mix_instr_stream(self.push_stack_instr)
for i in range(len(self.instr_list)):
self.instr_list[i].atomic = 1
if self.instr_list[i].label == '':
self.instr_list[i].has_label = 0
def create_instr_instance(self):
for i in range(self.instr_cnt):
instr = riscv_instr()
self.instr_list.append(instr)
def add_mixed_instr(self, instr_cnt):
self.setup_allowed_instr(1, 1)
for i in range(instr_cnt):
instr = riscv_instr()
instr = self.randomize_instr(instr)
self.insert_instr(instr)
def __init__(self):
super().__init__()
self.lr_instr = vsc.attr(riscv_instr())
self.sc_instr = vsc.attr(riscv_instr())
