def set_sthal_params(wafer, gmax, gmax_div):
"""
synaptic strength:
gmax: 0 - 1023, strongest: 1023
gmax_div: 2 - 30, strongest: 2
"""
# for all HICANNs in use
for hicann in wafer.getAllocatedHicannCoordinates():
fgs = wafer[hicann].floating_gates
# set parameters influencing the synaptic strength
for block in iter_all(FGBlockOnHICANN):
fgs.setShared(block, HICANN.shared_parameter.V_gmax0, gmax)
fgs.setShared(block, HICANN.shared_parameter.V_gmax1, gmax)
fgs.setShared(block, HICANN.shared_parameter.V_gmax2, gmax)
fgs.setShared(block, HICANN.shared_parameter.V_gmax3, gmax)
for driver in iter_all(SynapseDriverOnHICANN):
for row in iter_all(RowOnSynapseDriver):
wafer[hicann].synapses[driver][row].set_gmax_div(
HICANN.GmaxDiv(gmax_div))
# don't change values below
for ii in xrange(fgs.getNoProgrammingPasses()):
cfg = fgs.getFGConfig(Enum(ii))
cfg.fg_biasn = 0
cfg.fg_bias = 0
fgs.setFGConfig(Enum(ii), cfg)
for block in iter_all(FGBlockOnHICANN):
fgs.setShared(block, HICANN.shared_parameter.V_dllres, 275)
fgs.setShared(block, HICANN.shared_parameter.V_ccas, 800)
def test_synapseswitch_exclusiveness(self):
"""
Check if checking of exclusiveness of synapse switch matrix works.
Warning: Does not check for all possible valid and invalid combinations.
"""
from pyhalbe.HICANN import SynapseSwitch
import pysthal
from pyhalco_common import iter_all, SideHorizontal
import pyhalco_hicann_v2 as C
hicann = pysthal.HICANN()
settings = pysthal.Settings.get()
# check per vline
for side in iter_all(SideHorizontal):
for vline in iter_all(C.VLineOnHICANN):
syn_drvs = [
syn_drv for syn_drv in vline.toSynapseDriverOnHICANN(side)
]
for syn_drv1, syn_drv2 in zip(syn_drvs, syn_drvs[1:]):
settings.synapse_switches.max_switches_per_column_per_side = 1
ssr1 = syn_drv1.toSynapseSwitchRowOnHICANN().line()
ssr2 = syn_drv2.toSynapseSwitchRowOnHICANN().line()
# one switch in vline -> ok
hicann.synapse_switches.set(vline, ssr1, True)
self.assertEqual(hicann.check(), "")
# two switches in vline -> invalid
hicann.synapse_switches.set(vline, ssr2, True)
self.assertNotEqual(hicann.check(), "")
settings.synapse_switches.max_switches_per_column_per_side = 2
self.assertEqual(hicann.check(), "")
hicann.clear_l1_switches()
# check per synapse switch row
for syn_drv in C.iter_all(C.SynapseDriverOnHICANN):
ssr = syn_drv.toSynapseSwitchRowOnHICANN()
vlines = [vl for vl in SynapseSwitch.get_lines(ssr)]
for vline1, vline2 in zip(vlines, vlines[1:]):
settings.synapse_switches.max_switches_per_row = 1
# one switch in switch row -> ok
hicann.synapse_switches.set(vline1, ssr.line(), True)
self.assertEqual(hicann.check(), "")
# two switches in switch row -> invalid
hicann.synapse_switches.set(vline2, ssr.line(), True)
self.assertNotEqual(hicann.check(), "")
settings.synapse_switches.max_switches_per_row = 2
self.assertEqual(hicann.check(), "")
hicann.clear_l1_switches()
def test_board_led_chain(cls):
all_leds = list(iter_all(halco.LEDOnBoard))
builder = stadls.PlaybackProgramBuilder()
# reset chip
builder.write(halco.ResetChipOnDLS(), haldls.ResetChip(True))
builder.write(halco.TimerOnDLS(), haldls.Timer())
builder.block_until(halco.TimerOnDLS(), 10)
builder.write(halco.ResetChipOnDLS(), haldls.ResetChip(False))
# write shiftreg container
shiftreg = haldls.ShiftRegister()
builder.write(halco.ShiftRegisterOnBoard(), shiftreg)
for led in all_leds + list(reversed(all_leds)):
builder.write(halco.TimerOnDLS(), haldls.Timer())
shiftreg.set_enable_led(led, True)
builder.write(halco.ShiftRegisterOnBoard(), shiftreg)
builder.block_until(halco.TimerOnDLS(),
int(fisch.fpga_clock_cycles_per_us * 1e6 / 8))
shiftreg.set_enable_led(led, False)
builder.write(halco.ShiftRegisterOnBoard(), shiftreg)
# pop playback program
program = builder.done()
# execute playback program
with hxcomm.ManagedConnection() as conn:
stadls.run(conn, program)
def f_fpga(coord):
"""print fpga related infomations"""
gcoord = Coordinate.FPGAGlobal(coord, WAFER)
out = "{}:\n".format(gcoord)
for dnc_f in iter_all(Coordinate.DNCOnFPGA):
dnc = dnc_f.toDNCOnWafer(gcoord)
out += "\t{} ({}, {}):\n".format(dnc, dnc.toEnum(), dnc.toPowerCoordinate())
out += print_hicanns_on_dnc(dnc, "\t\t")
return out
def test_pb_program_builder_dumper(self):
builder = stadls.PlaybackProgramBuilderDumper()
# reset chip
builder.write(halco.ResetChipOnDLS(), haldls.ResetChip(True))
builder.write(halco.TimerOnDLS(), haldls.Timer())
builder.block_until(halco.TimerOnDLS(), 10)
tmp = (halco.ResetChipOnDLS(), haldls.ResetChip(False))
builder.write(*tmp)
# write shiftreg container
shiftreg = haldls.ShiftRegister()
builder.write(halco.ShiftRegisterOnBoard(), shiftreg)
all_leds = list(iter_all(halco.LEDOnBoard))
for led in all_leds + list(reversed(all_leds)):
builder.write(halco.TimerOnDLS(), haldls.Timer())
shiftreg.set_enable_led(led, True)
builder.write(halco.ShiftRegisterOnBoard(), shiftreg)
builder.block_until(halco.TimerOnDLS(),
int(fisch.fpga_clock_cycles_per_us * 1e6 / 8))
shiftreg.set_enable_led(led, False)
builder.write(halco.ShiftRegisterOnBoard(), shiftreg)
builder.block_until(halco.BarrierOnFPGA(), haldls.Barrier.omnibus)
# pop playback program
builder_copy = stadls.PlaybackProgramBuilderDumper()
builder_copy.copy_back(builder)
program = builder.done()
self.assertEqual(len(program), 5 + len(all_leds) * 2 * 3 + 2,
"Wrong number of coordinate/container pairs")
self.assertNotEqual(program.tolist()[0], tmp)
self.assertNotEqual(program.tolist()[1], tmp)
self.assertNotEqual(program.tolist()[2], tmp)
self.assertEqual(program.tolist()[3], tmp)
self.assertNotEqual(program.tolist()[4], tmp)
dump = pickle.dumps(program.tolist())
restored_cocos = pickle.loads(dump)
self.assertEqual(program.tolist(), restored_cocos)
builder = stadls.PlaybackProgramBuilder()
for cor, con in restored_cocos:
if isinstance(cor, (halco.TimerOnDLS, halco.BarrierOnFPGA)) and \
isinstance(con, (haldls.Timer.Value, haldls.Barrier)):
builder.block_until(cor, con)
else:
builder.write(cor, con)
real_program = builder.done()
self.assertEqual(real_program,
stadls.convert_to_builder(program).done())
self.assertEqual(real_program,
stadls.convert_to_builder(builder_copy).done())
def test_synapse_access(self):
import pysthal
import numpy
import pyhalco_common
import pyhalco_hicann_v2
from pyhalbe import HICANN
d_patterns = {}
w_patterns = {}
hicann = pysthal.HICANN()
for row in pyhalco_common.iter_all(
pyhalco_hicann_v2.SynapseRowOnHICANN):
d_pattern = numpy.random.randint(0, 16, 256)
d_patterns[row] = d_pattern
hicann.synapses[row].decoders[:] = [
HICANN.SynapseDecoder(int(ii)) for ii in d_pattern
]
w_pattern = [
HICANN.SynapseWeight(int(ii))
for ii in numpy.random.randint(0, 16, 256)
]
w_patterns[row] = w_pattern
hicann.synapses[row].weights[:] = w_pattern
for drv in pyhalco_common.iter_all(
pyhalco_hicann_v2.SynapseDriverOnHICANN):
double_row = hicann.synapses.getDecoderDoubleRow(drv)
for x in (pyhalco_common.top, pyhalco_common.bottom):
row = pyhalco_hicann_v2.SynapseRowOnHICANN(drv, x)
data = numpy.array([int(ii) for ii in double_row[x.value()]])
if not numpy.all(data == d_patterns[row]):
err = "Missmatch in decoder values: {!s} != {!s} in {!s}".format(
data, d_patterns[row], row)
self.fail(err)
for syn in pyhalco_common.iter_all(pyhalco_hicann_v2.SynapseOnHICANN):
hicann.synapses[syn]
def test_neuronsize(self):
import pysthal
from pyhalco_common import iter_all, X
from pyhalco_hicann_v2 import NeuronOnHICANN, QuadOnHICANN
hicann = pysthal.HICANN()
sizes = [2**x for x in range(7)]
# There and back again
for size in sizes[:] + sizes[::-1]:
hicann.set_neuron_size(size)
hicann.check()
active = [
hicann.neurons[neuron].activate_firing()
for neuron in iter_all(NeuronOnHICANN)
]
self.assertEqual(active.count(True), 512 / size)
for quad in iter_all(QuadOnHICANN):
self.assertEqual(
hicann.neurons[quad].getVerticalInterconnect(X(0)),
(size > 1))
self.assertEqual(
hicann.neurons[quad].getVerticalInterconnect(X(1)),
(size > 1))
def test_chain_assign_synram_conf(self):
"""
Test that writing new values to common_synram_config.wait_ctr_clear
actually changes the common_synram_config object.
This has failed before because common_synram_config was returning a
copy of wait_ctr_clear that would be modified but never set.
"""
for val in Co.iter_all(self.chip.common_synram_config.WaitCtrClear):
self.chip.common_synram_config.wait_ctr_clear = val
self.assertIsInstance(
self.chip.common_synram_config.wait_ctr_clear,
self.chip.common_synram_config.WaitCtrClear)
self.assertEqual(val,
self.chip.common_synram_config.wait_ctr_clear)
def to_neighbors(coord):
if isinstance(coord, HICANNOnWafer):
return [to_string(coord.move(d)) for d in iter_all(Direction) if coord.can_move(d)]
else:
raise TypeError(
"coordinate type not handled, received: {}".format(type(coord)))
parser.add_argument("vertical", type=str, choices=["top", "bottom"])
args = parser.parse_args()
bg_addr = pyhalbe.HICANN.L1Address(0)
in_addr_int = args.in_addr
in_addr = pyhalbe.HICANN.L1Address(in_addr_int)
# Get wafer and HICANN
wafer = pysthal.Wafer(wafer_c)
hicann = wafer[hicann_c]
neuron = hicann.neurons[neuron_c]
neuron.activate_firing(True)
# Configure background generators to fire on L1 address 0
for bg in iter_all(Coordinate.BackgroundGeneratorOnHICANN):
generator = hicann.layer1[bg]
generator.enable(True)
generator.random(False)
generator.period(200) # 16 bits!
generator.address(bg_addr)
# Reconfigure merger tree. By default it gets routed from top to bottom (one-to-one).
#hicann.layer1[Coordinate.Merger0OnHICANN(0)].config = HICANN.Merger.LEFT_ONLY
# Configure DNC mergers.:
for merger in iter_all(Coordinate.DNCMergerOnHICANN):
hicann.layer1[merger].slow = True # Needed for sending repeaters
# Configure sending repeater to forward spikes to the right
h_line = Coordinate.HLineOnHICANN(62)
def test_find_neuron_in_analog_output(self):
"""
Check if find_neuron_in_analog_output works.
"""
import pysthal
from pyhalco_common import iter_all, X, Y
from pyhalco_hicann_v2 import NeuronOnHICANN, AnalogOnHICANN
hicann = pysthal.HICANN()
NeuronOnHICANN.__repr__ = NeuronOnHICANN.__str__
# Nothing active, this should throw
for analog in iter_all(AnalogOnHICANN):
with self.assertRaises(RuntimeError):
hicann.find_neuron_in_analog_output(analog)
# Enable 4 neurons, connected to different analog mux entries, but not
# the mux yet, this should throw
hicann.neurons[NeuronOnHICANN(X(0), Y(0))].enable_aout(True)
hicann.neurons[NeuronOnHICANN(X(1), Y(0))].enable_aout(True)
hicann.neurons[NeuronOnHICANN(X(0), Y(1))].enable_aout(True)
hicann.neurons[NeuronOnHICANN(X(1), Y(1))].enable_aout(True)
for analog in iter_all(AnalogOnHICANN):
with self.assertRaises(RuntimeError):
hicann.find_neuron_in_analog_output(analog)
# Now enable the mux for each of the neurons and check if the correct
# neuron was found
for analog in iter_all(AnalogOnHICANN):
hicann.analog.set_membrane_top_even(analog)
self.assertEqual(NeuronOnHICANN(X(0), Y(0)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.set_membrane_top_odd(analog)
self.assertEqual(NeuronOnHICANN(X(1), Y(0)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.set_membrane_bot_even(analog)
self.assertEqual(NeuronOnHICANN(X(0), Y(1)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.set_membrane_bot_odd(analog)
self.assertEqual(NeuronOnHICANN(X(1), Y(1)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.disable(analog)
# Now enable 4 more, each connected to different analog mux entries,
# now it should fail, because two neurons are connected
hicann.neurons[NeuronOnHICANN(X(30), Y(0))].enable_aout(True)
hicann.neurons[NeuronOnHICANN(X(41), Y(0))].enable_aout(True)
hicann.neurons[NeuronOnHICANN(X(10), Y(1))].enable_aout(True)
hicann.neurons[NeuronOnHICANN(X(255), Y(1))].enable_aout(True)
for analog in iter_all(AnalogOnHICANN):
hicann.analog.set_membrane_top_even(analog)
with self.assertRaises(RuntimeError):
hicann.find_neuron_in_analog_output(analog)
hicann.analog.set_membrane_top_odd(analog)
with self.assertRaises(RuntimeError):
hicann.find_neuron_in_analog_output(analog)
hicann.analog.set_membrane_bot_even(analog)
with self.assertRaises(RuntimeError):
hicann.find_neuron_in_analog_output(analog)
hicann.analog.set_membrane_bot_odd(analog)
with self.assertRaises(RuntimeError):
hicann.find_neuron_in_analog_output(analog)
hicann.analog.disable(analog)
# Now disable the first 4 neurons, and everything should be fine again
hicann.neurons[NeuronOnHICANN(X(0), Y(0))].enable_aout(False)
hicann.neurons[NeuronOnHICANN(X(1), Y(0))].enable_aout(False)
hicann.neurons[NeuronOnHICANN(X(0), Y(1))].enable_aout(False)
hicann.neurons[NeuronOnHICANN(X(1), Y(1))].enable_aout(False)
for analog in iter_all(AnalogOnHICANN):
hicann.analog.set_membrane_top_even(analog)
self.assertEqual(NeuronOnHICANN(X(30), Y(0)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.set_membrane_top_odd(analog)
self.assertEqual(NeuronOnHICANN(X(41), Y(0)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.set_membrane_bot_even(analog)
self.assertEqual(NeuronOnHICANN(X(10), Y(1)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.set_membrane_bot_odd(analog)
self.assertEqual(NeuronOnHICANN(X(255), Y(1)),
hicann.find_neuron_in_analog_output(analog))
hicann.analog.disable(analog)
