class TestWire(unittest.TestCase):
def setUp(self):
self.wire = Wire()
def test_default(self):
assert self.wire.val == 'x'
def set_val(self, x):
self.wire.val = x
assert self.wire.val == x
def test_set(self):
self.set_val('x')
self.set_val('X')
self.set_val('0')
self.set_val('1')
with self.assertRaises(HDLError) as cm:
self.wire.val = 'A'
def test_listeners(self):
self.wire.addListener('a')
assert self.wire.listeners == ['a']
def test_driver(self):
self.wire.driver = 'abc'
assert self.wire.driver == 'abc'
def test_multiple_driver(self):
with self.assertRaises(HDLError) as cm:
self.wire.driver = 'abc'
self.wire.driver = 'xyz'
class TestWire(unittest.TestCase):
def setUp(self):
self.wire = Wire()
def test_default(self):
assert self.wire.val == 'x'
def set_val(self, x):
self.wire.val = x
assert self.wire.val == x
def test_set(self):
self.set_val('x')
self.set_val('X')
self.set_val('0')
self.set_val('1')
with self.assertRaises(HDLError) as cm:
self.wire.val = 'A'
def test_listeners(self):
self.wire.addListener('a')
assert self.wire.listeners == ['a']
def test_driver(self):
self.wire.driver = 'abc'
assert self.wire.driver == 'abc'
def test_multiple_driver(self):
with self.assertRaises(HDLError) as cm:
self.wire.driver = 'abc'
self.wire.driver = 'xyz'
def setUp(self):
self.a = Wire()
self.b = Wire()
self.out = Wire()
self.carry = Wire()
self.adder = HalfAdder(a=self.a, b=self.b, out=self.out, carry=self.carry)
def setUp(self):
self.a = Wire()
self.b = Wire()
self.cin = Wire()
self.out = Wire()
self.cout = Wire()
self.adder = FullAdder(a=self.a, b=self.b, out=self.out, cin=self.cin, cout=self.cout)
def setUp(self):
self.inputs = {
"a": Wire(),
"b": Wire(),
"c": Wire(),
}
self.outputs = {
"x": Wire(),
"y": Wire(),
"z": Wire(),
}
self.internals = {
"i1": Wire(),
"i2": Wire(),
"i3": Wire(),
}
self.gateList = [self, self, self, self]
self.gateDict = {
"g1": self,
"g2": self,
"g3": self,
}
self.composite = Composite(self.gateList, self.inputs, self.outputs,
self.internals, self.gateDict)
self.tick_count = 0
self.tock_count = 0
self.eval_count = 0
class TestSubWireSlice(unittest.TestCase):
def setUp(self):
self.wire = Wire(width=4)
self.subwire = self.wire[2:3]
self.evalCalls = 0
def eval(self):
self.evalCalls += 1
def test_default(self):
assert self.subwire.val == 'x'
def set_val(self, x):
self.wire.val = '01{0}1'.format(x)
assert self.subwire.val == x
def test_set(self):
self.set_val('x')
self.set_val('X')
self.set_val('0')
self.set_val('1')
def test_contains(self):
assert slice(2, 3) in self.wire
assert slice(10, 12) not in self.wire
assert slice(0, 2) in self.wire
def test_iter(self):
i = 0
for item in self.wire.__iter__():
assert item == slice(i, i + 1)
i += 1
def test_len(self):
assert len(self.wire) == 4
def test_new(self):
a = Wire(type="input")
b = Wire(type="input")
c = Wire()
d = Wire(type="output")
e = Wire(type="output")
g1 = NandGate(a=a, b=b, out=c)
g2 = NandGate(a=c, b=c, out=d)
g3 = NandGate(a=d, b=c, out=e)
classdict = {
"a": a,
"b": b,
"c": c,
"d": d,
"e": e,
"g1": g1,
"g2": g2,
"g3": g3,
}
module = ModuleMetaClass('TestModule', (Module, ), dict(classdict))
pyhdl_stuff = getattr(module, '_pyhdl_stuff')
assert pyhdl_stuff['gates']['g1'] == g1
assert pyhdl_stuff['gates']['g2'] == g2
assert pyhdl_stuff['gates']['g3'] == g3
assert pyhdl_stuff['gate_list'][0] == g1
assert pyhdl_stuff['gate_list'][1] == g2
assert pyhdl_stuff['gate_list'][2] == g3
assert pyhdl_stuff['inputs']['a'] == a
assert pyhdl_stuff['inputs']['b'] == b
assert pyhdl_stuff['outputs']['d'] == d
assert pyhdl_stuff['outputs']['e'] == e
assert pyhdl_stuff['internals']['c'] == c
class TestSubWireSlice(unittest.TestCase):
def setUp(self):
self.wire = Wire(width=4)
self.subwire = self.wire[2:3]
self.evalCalls = 0
def eval(self):
self.evalCalls += 1
def test_default(self):
assert self.subwire.val == 'x'
def set_val(self, x):
self.wire.val = '01{0}1'.format(x)
assert self.subwire.val == x
def test_set(self):
self.set_val('x')
self.set_val('X')
self.set_val('0')
self.set_val('1')
def test_listeners(self):
self.subwire.addListener('a')
assert self.subwire.listeners == ['a']
def test_driver(self):
self.wire.driver = 'abc'
assert self.subwire.driver == 'abc'
def test_eval(self):
self.subwire.addListener(self)
self.subwire.eval()
assert self.evalCalls == 1
def test_contains(self):
assert slice(2, 3) in self.wire
assert slice(10, 12) not in self.wire
assert slice(0, 2) in self.wire
def test_iter(self):
i = 0
for item in self.wire.__iter__():
assert item == slice(i, i+1)
i += 1
def test_len(self):
assert len(self.wire) == 4
def setUp(self):
self.outputs = [
Wire(width=3),
Wire(width=3),
Wire(width=3),
Wire(width=3),
]
self.sel = Wire(width=2)
self.input = Wire(width=3)
self.demux = Demultiplexer(
a=self.outputs[0],
b=self.outputs[1],
c=self.outputs[2],
d=self.outputs[3],
sel=self.sel,
input=self.input,
width=3,
ways=4
)
def setUp(self):
self.wire = Wire()
def setUp(self):
self.inp, self.out = Wire(), Wire()
self.not_gate = NotGate(self.inp, self.out)
def setUp(self):
self.a, self.b, self.out = Wire(), Wire(), Wire()
self.and_gate = self.gate(a=self.a, b=self.b, out=self.out)
def setUp(self):
self.module = type('TestModule', Module.__bases__, dict(Module.__dict__))
self.inputs = {
"a": Wire(),
"b": Wire(),
"c": Wire(),
}
self.outputs = {
"x": Wire(),
"y": Wire(),
"z": Wire(),
}
self.internals = {
"i1": Wire(),
"i2": Wire(),
"i3": Wire(),
}
self.gateList = []
self.gateDict = {}
setattr(self.module, '_pyhdl_stuff', {
'gate_list': self.gateList,
'inputs': self.inputs,
'outputs': self.outputs,
'internals': self.internals,
'gates': self.gateDict,
})
self.a = Wire()
self.z = Wire()
self.composite = self.module(a=self.a, z=self.z)
self.tick_count = 0
self.tock_count = 0
self.eval_count = 0
def setUp(self):
self.wire = Wire()
def setUp(self):
self.input = Wire(width=4)
self.output = Wire(width=4)
self.write = Wire()
self.register = Register(input=self.input, output=self.output, write=self.write, default='0000')
def setUp(self):
self.a = Wire(width=16)
self.b = Wire(width=16)
self.out = Wire(width=16)
self.adder = Adder(a=self.a, b=self.b, out=self.out, width=16)
def setUp(self):
self.wire = Wire(width=16)
def setUp(self):
self.wire = Wire(width=4)
self.subwire = self.wire[2:3]
self.evalCalls = 0
def setUp(self):
self.wire = Wire(width=4)
self.subwire = self.wire[2:3]
self.evalCalls = 0
def setUp(self):
self.a, self.out = Wire(), Wire()
self.dff_gate = DFF(self.a, self.out, '0')
def setUp(self):
self.wire = Wire(width=4)
self.subwire = SubWire(self.wire, slice(2, 3))
self.evalCalls = 0
def setUp(self):
self.input = Wire(width=16)
self.output = Wire(width=16)
self.address = Wire(width=16)
self.write = Wire()
self.memory = Memory(input=self.input, output=self.output, address=self.address, write=self.write, default=0, width=16)
def setUp(self):
self.input = Wire()
self.output = Wire()
self.bridge = BridgeWire(self.input, self.output)