def construct(s, data_width, num_entries, count_width):
s.count = OutPort(mk_bits(count_width))
s.deq_en = InPort(Bits1)
s.deq_rdy = OutPort(Bits1)
s.deq_msg = OutPort(mk_bits(data_width))
s.enq_en = InPort(Bits1)
s.enq_rdy = OutPort(Bits1)
s.enq_msg = InPort(mk_bits(data_width))
def construct(s):
s.in0 = InPort(Bits32)
s.in1 = InPort(Bits32)
s.cin = InPort(Bits1)
s.out = OutPort(Bits32)
s.cout = OutPort(Bits1)
s.sverilog_import = ImportConfigs(vl_src=get_dir(__file__) +
'VAdder.sv')
def construct( s ):
s.in_1 = InPort( Bits32 )
s.in_2 = InPort( Bits32 )
s.in_3 = InPort( Bits32 )
s.out = OutPort( Bits1 )
@s.update
def v_reduce():
s.out = reduce_and( s.in_1 ) & reduce_or( s.in_2 ) | reduce_xor( s.in_3 )
def construct(s):
s.in_1 = InPort(Bits32)
s.in_2 = InPort(Bits32)
s.out = OutPort(Bits64)
@s.update
def upblk():
s.out = concat(s.in_1, s.in_2)
def construct( s, data_width, num_entries, count_width ): s.count = OutPort( mk_bits( count_width ) ) s.deq_en = InPort( Bits1 ) s.deq_rdy = OutPort( Bits1 ) s.deq_msg = OutPort( mk_bits( data_width ) ) s.enq_en = InPort( Bits1 ) s.enq_rdy = OutPort( Bits1 ) s.enq_msg = InPort( mk_bits( data_width ) ) s.set_metadata( VerilogTranslationImportPass.enable, True )
def construct(s):
s.in_ = InPort(Bits4)
s.slice_l = InPort(Bits2)
s.slice_r = InPort(Bits2)
s.out = OutPort(Bits1)
@s.update
def upblk():
s.out = s.in_[s.slice_l:s.slice_r]
def construct(s, data_width, num_entries, count_width):
s.count = OutPort(mk_bits(count_width))
s.deq_en = InPort(Bits1)
s.deq_rdy = OutPort(Bits1)
s.deq_msg = OutPort(mk_bits(data_width))
s.enq_en = InPort(Bits1)
s.enq_rdy = OutPort(Bits1)
s.enq_msg = InPort(mk_bits(data_width))
s.sverilog_import = ImportConfigs(vl_src=get_dir(__file__) +
'VQueue.sv')
def construct(s, data_width, num_entries, count_width):
s.count = OutPort(mk_bits(count_width))
s.deq_en = InPort(Bits1)
s.deq_rdy = OutPort(Bits1)
s.deq_msg = OutPort(mk_bits(data_width))
s.enq_en = InPort(Bits1)
s.enq_rdy = OutPort(Bits1)
s.enq_msg = InPort(mk_bits(data_width))
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=dirname(__file__) + '/VQueue.v', )
s.verilog_translate_import = True
def construct(s):
s.in_1 = InPort(Bits32)
s.in_2 = InPort(Bits32)
s.out = OutPort(Bits32)
@s.update
def upblk():
if Bits1(1):
s.out = s.in_1
else:
s.out = s.in_2
def construct(s):
s.in0 = InPort(Bits32)
s.in1 = InPort(Bits32)
s.cin = InPort(Bits1)
s.out = OutPort(Bits32)
s.cout = OutPort(Bits1)
s.config_placeholder = VerilogPlaceholderConfigs(
src_file=dirname(__file__) + '/VAdder.v',
top_module='VAdder',
)
s.verilog_translate_import = True
def construct( s ):
s.in_b = InPort( B )
s.in_c = InPort( C )
s.out_b = OutPort( Bits32 )
s.out_c = OutPort( Bits32 )
@s.update
def upblk1():
u = s.in_b
s.out_b = u.foo
@s.update
def upblk2():
u = s.in_c
s.out_c = u.bar
def construct(s):
s.in_ = [InPort(Bits32) for _ in range(2)]
s.out = OutPort(Bits64)
@s.update
def upblk():
s.out = concat(s.in_[0], s.in_[1])
def construct(s):
s.in_ = InPort(Bits64)
s.out = OutPort(Bits32)
@s.update
def upblk():
s.out = s.in_[4:36]
def construct(s):
s.in_ = InPort(Bits32)
s.out = OutPort(Bits64)
@s.update
def upblk():
s.out = concat(s.in_, Bits32(0))
def construct(s):
s.in_ = InPort(Bits32)
s.out = OutPort(Bits64)
@s.update
def upblk():
s.out = zext(s.in_, 64)
def construct(s):
s.in_ = InPort(B)
s.out = OutPort(Bits96)
@s.update
def upblk():
s.out = concat(s.in_.bar[0], s.in_.c.woof, s.in_.foo)
def construct( s ):
s.in_ = InPort( Bits32 )
s.idx = B()
s.out = OutPort( Bits4 )
@s.update
def upblk():
s.out = s.in_[ 0:s.idx ]
def construct(s):
s.in_ = [InPort(Bits1) for _ in range(4)]
s.out = OutPort(Bits1)
@s.update
def upblk():
s.out = s.in_[4]
def construct(s):
s.in_ = InPort(B)
s.out = OutPort(Bits1)
@s.update
def upblk():
s.out = Bits1(1) and s.in_
def construct(s):
s.in_ = InPort(Bits32)
s.out = OutPort(Bits32)
@s.update_on_edge
def upblk():
s.out = s.in_
def construct(s):
s.in_ = InPort(B)
s.out = OutPort(Bits16)
@s.update
def upblk():
s.out = s.in_
def construct( s ):
s.in_ = InPort( Bits16 )
s.out = OutPort( Bits8 )
@s.update
def mismatch_width_assign():
s.out = s.in_
def construct(s, nbits=0):
s.in_ = InPort(mk_bits(nbits))
s.out = OutPort(mk_bits(nbits))
@s.update
def up_x2():
s.out = s.in_ << 1
def construct(s, nbits=0):
s.in_ = InPort(mk_bits(nbits))
s.out = OutPort(mk_bits(nbits))
s.w = Wire(mk_bits(nbits))
connect(s.w, s.out)
s.inner = Foo(32)(in_=s.in_, out=s.w)
def construct(s):
s.in_ = InPort(Bits8)
s.out = OutPort(Bits16)
@s.update
def upblk():
s.out = zext(s.in_, 4)
def construct( s ):
s.in_ = InPort( Bits16 )
s.out = [ OutPort( Bits8 ) for _ in range(2) ]
@s.update
def upblk():
for i in range(2):
s.out[i] = s.in_[i*8 : i*8 + 8]
def construct( s ):
s.in_ = InPort( Bits16 )
s.out = OutPort( Bits16 )
@s.update
def bits_basic():
s.out = s.in_ + Bits16( 10 )
def construct(s):
s.in_ = InPort(Bits32)
s.out = OutPort(Bits32)
@s.update_ff
def upblk():
s.out <<= s.in_
def construct(s):
s.in_ = InPort(Bits8)
s.out = OutPort(Bits16)
@s.update
def upblk():
s.out = concat(s, s.in_)
def construct( s ):
s.in_ = InPort( Bits16 )
s.out = OutPort( Bits16 )
@s.update
def multi_components_B():
s.out = s.in_
