def test_L1_port_index():
a = CaseConnectPortIndexComp.DUT()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(gen_connections(a)))
connections = a.get_metadata(StructuralRTLIRGenL1Pass.connections)
comp = sexp.CurComp(a, 's')
assert connections == \
[(sexp.PortIndex(sexp.CurCompAttr(comp, 'in_'), 2), sexp.CurCompAttr(comp, 'out'))]
def test_L1_bits_connection():
a = CaseConnectBitsConstToOutComp.DUT()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(gen_connections(a)))
connections = a.get_metadata(StructuralRTLIRGenL1Pass.connections)
comp = sexp.CurComp(a, 's')
assert connections == \
[(sexp.ConstInstance(Bits32(0), 0), sexp.CurCompAttr(comp, 'out'))]
def test_L1_wire_index():
a = CaseConnectInToWireComp.DUT()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(gen_connections(a)))
connections = a.get_metadata(StructuralRTLIRGenL1Pass.connections)
comp = sexp.CurComp(a, 's')
assert connections[0] == \
(sexp.WireIndex(sexp.CurCompAttr(comp, 'wire_'), 2), sexp.CurCompAttr(comp, 'out'))
def test_L1_part_selection():
a = CaseConnectSliceToOutComp.DUT()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(gen_connections(a)))
connections = a.get_metadata(StructuralRTLIRGenL1Pass.connections)
comp = sexp.CurComp(a, 's')
assert connections == \
[(sexp.PartSelection(sexp.CurCompAttr(comp, 'in_'), 4, 8), sexp.CurCompAttr(comp, 'out'))]
def test_L1_port_index():
a = CaseConnectPortIndexComp.DUT()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(gen_connections(a)))
ns = a._pass_structural_rtlir_gen
comp = sexp.CurComp(a, 's')
assert ns.connections == \
[(sexp.PortIndex(sexp.CurCompAttr(comp, 'in_'), 2), sexp.CurCompAttr(comp, 'out'))]
def test_L1_connection_order():
a = CaseInx2Outx2ConnectComp.DUT()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(gen_connections(a)))
connections = a.get_metadata(StructuralRTLIRGenL1Pass.connections)
comp = sexp.CurComp(a, 's')
assert connections == \
[(sexp.CurCompAttr(comp, 'in_1'), sexp.CurCompAttr(comp, 'out1')),
(sexp.CurCompAttr(comp, 'in_2'), sexp.CurCompAttr(comp, 'out2'))]
def test_L1_bit_selection():
a = CaseConnectBitSelToOutComp.DUT()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(gen_connections(a)))
connections = a.get_metadata(StructuralRTLIRGenL1Pass.connections)
comp = sexp.CurComp(a, 's')
# PyMTL DSL converts bit selection into 1-bit part selection!
assert connections == \
[(sexp.PartSelection(sexp.CurCompAttr(comp, 'in_'), 0, 1), sexp.CurCompAttr(comp, 'out'))]
def test_L1_connection_order():
a = CaseInx2Outx2ConnectComp.DUT()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(gen_connections(a)))
ns = a._pass_structural_rtlir_gen
comp = sexp.CurComp(a, 's')
assert ns.connections == \
[(sexp.CurCompAttr(comp, 'in_1'), sexp.CurCompAttr(comp, 'out1')),
(sexp.CurCompAttr(comp, 'in_2'), sexp.CurCompAttr(comp, 'out2'))]
def test_L1_const_index():
a = CaseConnectConstToOutComp.DUT()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(gen_connections(a)))
connections = a.get_metadata(StructuralRTLIRGenL1Pass.connections)
comp = sexp.CurComp(a, 's')
# The expression structure is removed and only the constant value
# is left in this node.
assert connections == \
[(sexp.ConstInstance(Bits32(a.const_[2]), 42), sexp.CurCompAttr(comp, 'out'))]
def test_L1_bits_connection():
class A(dsl.Component):
def construct(s):
s.out = dsl.OutPort(Bits32)
dsl.connect(s.out, Bits32(0))
a = A()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(*gen_connections(a)))
ns = a._pass_structural_rtlir_gen
comp = sexp.CurComp(a, 's')
assert ns.connections == \
[(sexp.ConstInstance(Bits32(0), 0), sexp.CurCompAttr(comp, 'out'))]
def test_L1_port_index():
class A(dsl.Component):
def construct(s):
s.in_ = [dsl.InPort(Bits32) for _ in range(5)]
s.out = dsl.OutPort(Bits32)
dsl.connect(s.in_[2], s.out)
a = A()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(*gen_connections(a)))
ns = a._pass_structural_rtlir_gen
comp = sexp.CurComp(a, 's')
assert ns.connections == \
[(sexp.PortIndex(sexp.CurCompAttr(comp, 'in_'), 2), sexp.CurCompAttr(comp, 'out'))]
def test_L1_part_selection():
class A(dsl.Component):
def construct(s):
s.in_ = dsl.InPort(Bits32)
s.out = dsl.OutPort(Bits4)
dsl.connect(s.in_[4:8], s.out)
a = A()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(*gen_connections(a)))
ns = a._pass_structural_rtlir_gen
comp = sexp.CurComp(a, 's')
assert ns.connections == \
[(sexp.PartSelection(sexp.CurCompAttr(comp, 'in_'), 4, 8), sexp.CurCompAttr(comp, 'out'))]
def test_L1_bit_selection():
class A(dsl.Component):
def construct(s):
s.in_ = dsl.InPort(Bits32)
s.out = dsl.OutPort(Bits1)
dsl.connect(s.in_[0], s.out)
a = A()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(*gen_connections(a)))
ns = a._pass_structural_rtlir_gen
comp = sexp.CurComp(a, 's')
# PyMTL DSL converts bit selection into 1-bit part selection!
assert ns.connections == \
[(sexp.PartSelection(sexp.CurCompAttr(comp, 'in_'), 0, 1), sexp.CurCompAttr(comp, 'out'))]
def test_L1_const_index():
class A(dsl.Component):
def construct(s):
s.const = [42 for _ in range(5)]
s.out = dsl.OutPort(Bits32)
dsl.connect(s.const[2], s.out)
a = A()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(*gen_connections(a)))
ns = a._pass_structural_rtlir_gen
comp = sexp.CurComp(a, 's')
# The expression structure is removed and only the constant value
# is left in this node.
assert ns.connections == \
[(sexp.ConstInstance(a.const[2], 42), sexp.CurCompAttr(comp, 'out'))]
def test_L1_wire_index():
class A(dsl.Component):
def construct(s):
s.in_ = [dsl.InPort(Bits32) for _ in range(5)]
s.wire = [dsl.Wire(Bits32) for _ in range(5)]
s.out = dsl.OutPort(Bits32)
dsl.connect(s.wire[2], s.out)
for i in range(5):
dsl.connect(s.wire[i], s.in_[i])
a = A()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(gen_connections(a)))
ns = a._pass_structural_rtlir_gen
comp = sexp.CurComp(a, 's')
assert ns.connections[0] == \
(sexp.WireIndex(sexp.CurCompAttr(comp, 'wire'), 2), sexp.CurCompAttr(comp, 'out'))
def test_L1_connection_order():
class A(dsl.Component):
def construct(s):
s.in_1 = dsl.InPort(Bits32)
s.in_2 = dsl.InPort(Bits32)
s.out1 = dsl.OutPort(Bits32)
s.out2 = dsl.OutPort(Bits32)
dsl.connect(s.in_1, s.out1)
dsl.connect(s.in_2, s.out2)
a = A()
a.elaborate()
a.apply(StructuralRTLIRGenL1Pass(*gen_connections(a)))
ns = a._pass_structural_rtlir_gen
comp = sexp.CurComp(a, 's')
assert ns.connections == \
[(sexp.CurCompAttr(comp, 'in_1'), sexp.CurCompAttr(comp, 'out1')),
(sexp.CurCompAttr(comp, 'in_2'), sexp.CurCompAttr(comp, 'out2'))]