def mux_t_subprocess(self, addr_width, val_width):
mux_ins, vals = utils.make_consts(num_wires=2**addr_width, exact_bitwidth=val_width)
control, testctrl = utils.an_input_and_vals(addr_width, 40, "mux_ctrl")
out = pyrtl.Output(val_width, "mux_out")
out <<= pyrtl.corecircuits.mux(control, *mux_ins)
true_result = [vals[i] for i in testctrl]
mux_result = utils.sim_and_ret_out(out, (control,), (testctrl,))
self.assertEqual(mux_result, true_result)
def test_mux_with_default(self):
addr_width = 5
val_width = 9
default_val = 170 # arbitrary value under 2**val_width
num_defaults = 5
mux_ins, vals = utils.make_consts(num_wires=2**addr_width - num_defaults,
exact_bitwidth=val_width, random_dist=utils.uniform_dist)
control, testctrl = utils.an_input_and_vals(addr_width, 40, "mux_ctrl", utils.uniform_dist)
for i in range(5):
vals.append(default_val)
out = pyrtl.Output(val_width, "mux_out")
out <<= pyrtl.corecircuits.mux(control, *mux_ins, default=pyrtl.Const(default_val))
true_result = [vals[i] for i in testctrl]
mux_result = utils.sim_and_ret_out(out, (control,), (testctrl,))
self.assertEqual(mux_result, true_result)