def test_function_RomBlock(self):
def rom_data_function(add):
return int((add + 5) / 2)
pyrtl.reset_working_block()
self.bitwidth = 4
self.addrwidth = 4
self.output1 = pyrtl.Output(self.bitwidth, "o1")
self.output2 = pyrtl.Output(self.bitwidth, "o2")
self.read_addr1 = pyrtl.Input(self.addrwidth)
self.read_addr2 = pyrtl.Input(self.addrwidth)
self.rom = pyrtl.RomBlock(bitwidth=self.bitwidth,
addrwidth=self.addrwidth,
name='rom',
romdata=rom_data_function)
self.output1 <<= self.rom[self.read_addr1]
self.output2 <<= self.rom[self.read_addr2]
# build the actual simulation environment
self.sim_trace = pyrtl.SimulationTrace()
self.sim = pyrtl.FastSimulation(tracer=self.sim_trace)
input_signals = {}
for i in range(0, 5):
input_signals[i] = {self.read_addr1: i, self.read_addr2: 2 * i}
self.sim.step(input_signals[i])
exp_out = self.generate_expected_output(
(("o1", lambda x: rom_data_function(x)),
("o2", lambda x: rom_data_function(2 * x))), 6)
self.compareIO(self.sim_trace, exp_out)
def test_wallace_tree_1(self):
"""
Arithmatic tester version 2015.05
"""
# Creating the logic nets
a, b = pyrtl.Input(13, "a"), pyrtl.Input(14, "b")
product = pyrtl.Output(27, "product")
product <<= multipliers.tree_multiplier(a, b)
# creating the testing values and the correct results
xvals = [int(random.uniform(0, 2**13-1)) for i in range(20)]
yvals = [int(random.uniform(0, 2**14-1)) for i in range(20)]
true_result = [i * j for i, j in zip(xvals, yvals)]
# Setting up and running the tests
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
for cycle in range(len(xvals)):
sim.step({a: xvals[cycle], b: yvals[cycle]})
# Extracting the values and verifying correctness
multiplier_result = sim_trace.trace[product]
self.assertEqual(multiplier_result, true_result)
# now executing the same test using FastSim
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.FastSimulation(tracer=sim_trace)
for cycle in range(len(xvals)):
sim.step({a: xvals[cycle], b: yvals[cycle]})
multiplier_result = sim_trace.trace[product]
self.assertEqual(multiplier_result, true_result)
def check_trace(self, correct_string):
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.FastSimulation(tracer=sim_trace)
for i in range(8):
sim.step({})
output = io.StringIO()
sim_trace.print_trace(output)
self.assertEqual(output.getvalue(), correct_string)
def test_assert_fastsimulation(self):
i = pyrtl.Input(1)
o = pyrtl.rtl_assert(i, self.RTLSampleException('test assertion failed'))
sim = pyrtl.FastSimulation()
sim.step({i: 1})
self.assertEquals(sim.inspect(o), 1)
with self.assertRaises(self.RTLSampleException):
sim.step({i: 0})
def setUp(self):
pyrtl.reset_working_block()
bitwidth = 3
self.a = pyrtl.Input(bitwidth=bitwidth)
self.b = pyrtl.Input(bitwidth=bitwidth)
self.sel = pyrtl.Input(bitwidth=1)
self.muxout = pyrtl.Output(bitwidth=bitwidth, name='muxout')
self.muxout <<= generate_full_mux(self.a, self.b, self.sel)
# build the actual simulation environment
self.sim_trace = pyrtl.SimulationTrace()
self.sim = pyrtl.FastSimulation(tracer=self.sim_trace)
def test_vcd_output(self):
sim_trace = pyrtl.SimulationTrace()
on_reset = {} # signal states to be set when reset is asserted
# build the actual simulation environment
sim = pyrtl.FastSimulation(register_value_map=on_reset,
default_value=0,
tracer=sim_trace)
# step through 15 cycles
for i in range(15):
sim.step({})
test_output = io.StringIO()
sim_trace.print_vcd(test_output)
self.assertEqual(VCD_OUTPUT, test_output.getvalue())
def test_adder_simulation(self):
sim_trace = pyrtl.SimulationTrace()
on_reset = {} # signal states to be set when reset is asserted
# build the actual simulation environment
sim = pyrtl.FastSimulation(register_value_map=on_reset,
default_value=0,
tracer=sim_trace)
# step through 15 cycles
for i in range(15):
sim.step({})
output = io.StringIO()
sim_trace.print_trace(output)
self.assertEqual(output.getvalue(), 'r 012345670123456\n')
self.assertEqual(sim.inspect(self.r), 6)
def test_synth_simple_memblock(self):
synth_out = pyrtl.synthesize()
pyrtl.optimize()
self.sim_trace = pyrtl.SimulationTrace()
self.sim = pyrtl.FastSimulation(tracer=self.sim_trace)
input_signals = {
0: {
self.read_addr1: 0,
self.read_addr2: 1,
self.write_addr: 4,
self.write_data: 5
},
1: {
self.read_addr1: 4,
self.read_addr2: 1,
self.write_addr: 0,
self.write_data: 5
},
2: {
self.read_addr1: 0,
self.read_addr2: 4,
self.write_addr: 1,
self.write_data: 6
},
3: {
self.read_addr1: 1,
self.read_addr2: 1,
self.write_addr: 0,
self.write_data: 0
},
4: {
self.read_addr1: 6,
self.read_addr2: 0,
self.write_addr: 6,
self.write_data: 7
}
}
for i in range(5):
self.sim.step(input_signals[i])
output = io.StringIO()
self.sim_trace.print_trace(output)
self.assertEqual(output.getvalue(), 'o1 05560\no2 00560\n')
def test_simple_memblock(self):
self.sim = pyrtl.FastSimulation(tracer=self.sim_trace)
input_signals = {}
input_signals[0] = {
self.read_addr1: 0,
self.read_addr2: 1,
self.write_addr: 4,
self.write_data: 5
}
input_signals[1] = {
self.read_addr1: 4,
self.read_addr2: 1,
self.write_addr: 0,
self.write_data: 5
}
input_signals[2] = {
self.read_addr1: 0,
self.read_addr2: 4,
self.write_addr: 1,
self.write_data: 6
}
input_signals[3] = {
self.read_addr1: 1,
self.read_addr2: 1,
self.write_addr: 0,
self.write_data: 0
}
input_signals[4] = {
self.read_addr1: 6,
self.read_addr2: 0,
self.write_addr: 6,
self.write_data: 7
}
for i in range(5):
self.sim.step(input_signals[i])
output = io.StringIO()
self.sim_trace.print_trace(output)
self.assertEqual(output.getvalue(), 'o1 05560\no2 00560\n')
def test_super_stress_test(self):
allin = [pyrtl.Input(1, n) for n in 'abxyijkmzcd']
a, b, x, y, i, j, k, m, z, c, d = allin
allout = [pyrtl.Output(4, 'var' + str(index)) for index in range(5)]
var0, var1, var2, var3, var4 = allout
"""
1 with a: # a
2 with b: # not(a) and b
3 with x: # not(a) and b and x
4 with otherwise: # not(a) and b and not(x)
5 with y: # not(a) and b and y; check(3,4)
6 with i: # not(a) and b and y and i; check(3,4)
7 with j: # not(a) and b and y and not(i) and j; check(3,4)
8 with otherwise: # not(a) and b and y and not(i) and not(j): check(3,4)
9 with k: # not(a) and b and y and k; check(3,4,6,7,8)
8 with otherwise: # not(a) and b and y and not(k): check(?)
10 with m: # not(a) and b and y and m; check(?)
11 with otherwise: #not(a) and not(b)
12 with z: #not(a) and not(b) and z
13 with c: #c; check(1,2,3,4,5,6,7,8,9,10,11,12)
14 with d: #not(c) and d; check(1,2,3,4,5,6,7,8,9,10,11,12)
"""
with pyrtl.conditional_assignment:
with a:
var0 |= 1
with b:
with x:
var0 |= 2
with pyrtl.otherwise:
var0 |= 3
with y:
with i:
var1 |= 1
with j:
var1 |= 2
with pyrtl.otherwise:
var1 |= 3
with k:
var2 |= 1
with pyrtl.otherwise:
var2 |= 2
with m:
var3 |= 3
with pyrtl.otherwise:
with z:
var0 |= 4
with c:
var4 |= 1
with d:
var4 |= 2
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.FastSimulation(tracer=sim_trace)
for cycle in range(2**len(allin)):
inputs = {v: 0x1 & (cycle >> i) for i, v in enumerate(allin[::-1])}
sim.step(inputs)
for cycle in range(len(sim_trace)):
t0, t1, t2, t3, t4 = 0, 0, 0, 0, 0
def v(var):
return sim_trace.trace[var][cycle]
if v(a):
t0 = 1
elif v(b):
if v(x):
t0 = 2
else:
t0 = 3
if v(y):
if v(i):
t1 = 1
elif v(j):
t1 = 2
else:
t1 = 3
if v(k):
t2 = 1
else:
t2 = 2
if v(m):
t3 = 3
else:
if v(z):
t0 = 4
if v(c):
t4 = 1
elif v(d):
t4 = 2
self.assertEqual(v(var0), t0)
self.assertEqual(v(var1), t1)
self.assertEqual(v(var2), t2)
self.assertEqual(v(var3), t3)
self.assertEqual(v(var4), t4)
PHT_inc <<= PHT_m[PHT_ind] + pyrtl.Const(1)
PHT_dec = pyrtl.WireVector(bitwidth=2, name='PHT_dec')
PHT_dec <<= PHT_m[PHT_ind] - pyrtl.Const(1)
with pyrtl.conditional_assignment:
with prediction_int == BBS_m[BBS_ind]:
with PHT_m[PHT_ind] < pyrtl.Const(3):
PHT_m[PHT_ind] |= PHT_inc
with pyrtl.Const(0) < PHT_m[PHT_ind]:
PHT_m[PHT_ind] |= PHT_dec
BBS_m[BBS_ind] <<= ~outcome_i
# Simulation
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.FastSimulation(tracer=sim_trace)
# stimuli
f = open('serv1.trace', 'r')
predictor = AgreePredictor(PHT_size, BBS_size)
correct_predictions = 0
total_predictions = 0
moving_correct_predictions = 0
window_size = 200
_ = f.readline() # throw away first line
i = 0
predicts = []
moving_rate = []
line = f.readline()
while line:
DATA_WIDTH = 8
ADDR_WIDTH = 8
RAM_DEPTH = 1 << 8
address = pyrtl.Input(ADDR_WIDTH, "address")
cs = pyrtl.Input(1, "cs")
we = pyrtl.Input(1, "we")
oe = pyrtl.Input(1, "oe")
data_in = pyrtl.Input(DATA_WIDTH, "data_in")
data_out = pyrtl.Output(DATA_WIDTH, "data_out")
mem = pyrtl.memory.MemBlock(RAM_DEPTH, ADDR_WIDTH,
name="mem", asynchronous=True)
mem[address] <<= pyrtl.MemBlock.EnabledWrite(data_in, we & cs)
data_out_wire = pyrtl.wire.WireVector(DATA_WIDTH, "DATA_WIDTH")
with pyrtl.conditional_assignment:
with cs:
with we:
pass
with pyrtl.otherwise:
with oe:
data_out_wire |= mem[address]
data_out <<= data_out_wire
# Setup the simulation
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.FastSimulation(tracer=sim_trace, memory_value_map={mem: {0: 0}})
