def sample_roms():
def rom_func(address):
return (2 * address + 1) % 8
rom = pyrtl.RomBlock(3, 3, [2, 4, 7, 1])
romf = pyrtl.RomBlock(3, 3, rom_func)
return rom, romf
def test_rom_val_map(self):
def rom_data_function(add):
return int((add + 5) / 2)
dummy_in = pyrtl.Input(1, "dummy")
self.bitwidth = 4
self.addrwidth = 4
self.rom1 = pyrtl.RomBlock(bitwidth=self.bitwidth,
addrwidth=self.addrwidth,
name='rom1',
romdata=rom_data_function)
self.rom2 = pyrtl.RomBlock(bitwidth=self.bitwidth,
addrwidth=self.addrwidth,
name='rom2',
romdata=rom_data_function)
mem_val_map = {
self.rom1: {
0: 0,
1: 1,
2: 2,
3: 3
},
self.rom2: {
0: 4,
1: 5,
2: 6,
3: 7
}
}
self.sim_trace = pyrtl.SimulationTrace()
with self.assertRaises(pyrtl.PyrtlError):
sim = self.sim(tracer=self.sim_trace, memory_value_map=mem_val_map)
def test_value_out_of_range(self):
def rom_func(address):
return 2 * (8 - address) + 1
rom1 = pyrtl.RomBlock(3, 3, [15, 8, 7, 1])
romf1 = pyrtl.RomBlock(3, 3, rom_func)
for rom in (rom1, romf1):
self.invalid_rom_read(rom, 0)
self.invalid_rom_read(rom, 1)
def test_invalid_value_function(self):
def bad_func(address):
return str(address)
def bad_func_2(address):
return pyrtl.Const(address)
rom1 = pyrtl.RomBlock(5, 5, ['test', ()])
rom2 = pyrtl.RomBlock(5, 5, [pyrtl.Const(0), bad_func])
romf1 = pyrtl.RomBlock(5, 5, bad_func)
romf2 = pyrtl.RomBlock(5, 5, bad_func_2)
for rom in (rom1, rom2, romf1, romf2):
self.invalid_rom_read(rom, 0)
self.invalid_rom_read(rom, 1)
def test_function_RomBlock(self):
def rom_data_function(add):
return int((add + 5) / 2)
pyrtl.reset_working_block()
self.bitwidth = 4
self.addrwidth = 4
self.output1 = pyrtl.Output(self.bitwidth, "o1")
self.output2 = pyrtl.Output(self.bitwidth, "o2")
self.read_addr1 = pyrtl.Input(self.addrwidth)
self.read_addr2 = pyrtl.Input(self.addrwidth)
self.rom = pyrtl.RomBlock(bitwidth=self.bitwidth,
addrwidth=self.addrwidth,
name='rom',
romdata=rom_data_function)
self.output1 <<= self.rom[self.read_addr1]
self.output2 <<= self.rom[self.read_addr2]
# build the actual simulation environment
self.sim_trace = pyrtl.SimulationTrace()
self.sim = pyrtl.FastSimulation(tracer=self.sim_trace)
input_signals = {}
for i in range(0, 5):
input_signals[i] = {self.read_addr1: i, self.read_addr2: 2 * i}
self.sim.step(input_signals[i])
exp_out = self.generate_expected_output(
(("o1", lambda x: rom_data_function(x)),
("o2", lambda x: rom_data_function(2 * x))), 6)
self.compareIO(self.sim_trace, exp_out)
def test_area_est_unchanged_with_rom(self):
a = pyrtl.Const(2, 8)
b = pyrtl.Const(85, 8)
zero = pyrtl.Const(0, 1)
reg = pyrtl.Register(8)
mem = pyrtl.RomBlock(8, 8, romdata=list(range(0, 256)))
out = pyrtl.Output(8)
nota, aLSB, athenb, aORb, aANDb, aNANDb, \
aXORb, aequalsb, altb, agtb, aselectb, \
aplusb, bminusa, atimesb, memread = [pyrtl.Output() for i in range(15)]
out <<= zero
nota <<= ~a
aLSB <<= a[0]
athenb <<= pyrtl.concat(a, b)
aORb <<= a | b
aANDb <<= a & b
aNANDb <<= a.nand(b)
aXORb <<= a ^ b
aequalsb <<= a == b
altb <<= a < b
agtb <<= a > b
aselectb <<= pyrtl.select(zero, a, b)
reg.next <<= a
aplusb <<= a + b
bminusa <<= a - b
atimesb <<= a * b
memread <<= mem[reg]
self.assertEqual(pyrtl.area_estimation(), (0.00734386752, 0.001879779717361501))
def setUp(self):
pyrtl.reset_working_block()
self.bitwidth = 3
self.addrwidth = 5
self.output1 = pyrtl.Output(self.bitwidth, "output1")
self.in1 = pyrtl.Input(self.addrwidth, name='mem_write_address')
self.in2 = pyrtl.Input(self.addrwidth, name='mem_write_address')
self.memory = pyrtl.RomBlock(bitwidth=self.bitwidth, addrwidth=self.addrwidth,
name='self.memory', romdata=self.data, max_read_ports=None)
def test_romblock_does_not_throw_error(self):
a = pyrtl.Input(bitwidth=3, name='a')
b = pyrtl.Input(bitwidth=3, name='b')
o = pyrtl.Output(bitwidth=3, name='o')
sum, co = generate_full_adder(a, b)
rdat = {0: 1, 1: 2, 2: 5, 5: 0}
mixtable = pyrtl.RomBlock(addrwidth=3, bitwidth=3, romdata=rdat)
o <<= mixtable[sum]
with io.StringIO() as testbuffer:
pyrtl.output_to_verilog(testbuffer)
def test_over_max_read_ports(self):
width = 6
rom = pyrtl.RomBlock(width, width, [2, 4, 7, 1])
for i in range(rom.max_read_ports):
rom_read_address = pyrtl.Input(width)
rom_out = pyrtl.Output(width)
rom_out <<= rom[rom_read_address]
rom_read_address = pyrtl.Input(width)
rom_out = pyrtl.Output(width)
with self.assertRaises(pyrtl.PyrtlError):
rom_out <<= rom[rom_read_address]
def test_romblock_does_not_throw_error(self):
from pyrtl.corecircuits import _basic_add
a = pyrtl.Input(bitwidth=3, name='a')
b = pyrtl.Input(bitwidth=3, name='b')
o = pyrtl.Output(bitwidth=3, name='o')
res = _basic_add(a,b)
rdat = {0: 1, 1: 2, 2: 5, 5: 0}
mixtable = pyrtl.RomBlock(addrwidth=3, bitwidth=3, pad_with_zeros=True, romdata=rdat)
o <<= mixtable[res[:-1]]
with io.StringIO() as testbuffer:
pyrtl.output_to_verilog(testbuffer)
def test_rom_out_of_range_error(self):
rom_data_array = [15, 13, 11, 9, 7, 5, 3]
rom1 = pyrtl.RomBlock(bitwidth=4, addrwidth=3, romdata=rom_data_array)
rom_add_1 = pyrtl.Input(3, "rom_in")
rom_out_1 = pyrtl.Output(4, "rom_out_1")
rom_out_1 <<= rom1[rom_add_1]
sim_trace = pyrtl.SimulationTrace()
sim = self.sim(tracer=sim_trace)
sim.step({rom_add_1: 3})
with self.assertRaises(pyrtl.PyrtlError):
sim.step({rom_add_1: 7})
def test_build_new_roms(self):
width = 6
rom = pyrtl.RomBlock(6, 6, [2, 4, 7, 1], build_new_roms=True)
for i in range(width):
rom_read_address = pyrtl.Input(width)
rom_out = pyrtl.Output(width)
rom_out <<= rom[rom_read_address]
roms = set()
for romNet in pyrtl.working_block().logic_subset('m'):
curr_rom = romNet.op_param[1]
roms.add(curr_rom)
self.assertEqual(len(roms), 3)
def test_rom_out_of_range_error(self):
rom_data_array = [15, 13, 11, 9, 7, 5, 3]
rom1 = pyrtl.RomBlock(bitwidth=4, addrwidth=3, romdata=rom_data_array)
rom_add_1 = pyrtl.Input(3, "rom_in")
rom_out_1 = pyrtl.Output(4, "rom_out_1")
rom_out_1 <<= rom1[rom_add_1]
sim_trace = pyrtl.SimulationTrace()
with self.assertRaises(pyrtl.PyrtlError) as ex:
self.sim(tracer=sim_trace)
self.assertEqual(
str(ex.exception),
"RomBlock index is invalid, consider using pad_with_zeros=True for defaults"
)
import pyrtl
# instatiate a memory block that has our sample instructions stored in it
sample_instructions = [201326592, 286326786, 4202528, 2366177284]
mem = pyrtl.RomBlock(bitwidth=32,
addrwidth=2,
romdata=sample_instructions,
max_read_ports=1)
# variable counter will serve as an address in this example
counter = pyrtl.Register(bitwidth=2)
counter.next <<= counter + 1
# read data stored in rom
data = pyrtl.WireVector(bitwidth=32, name='data')
data <<= mem[counter]
# output data
op = pyrtl.Output(bitwidth=6, name='op')
rs = pyrtl.Output(bitwidth=5, name='rs')
rt = pyrtl.Output(bitwidth=5, name='rt')
rd = pyrtl.Output(bitwidth=5, name='rd')
sh = pyrtl.Output(bitwidth=5, name='sh')
func = pyrtl.Output(bitwidth=6, name='func')
imm = pyrtl.Output(bitwidth=16, name='imm')
addr = pyrtl.Output(bitwidth=26, name='addr')
### ADD YOUR INSTRUCTION DECODE LOGIC HERE ###
op <<= data[26:32]
rs <<= data[21:26]
rt <<= data[16:21]
0c 01 16 1b 38 35 22 2f 64 69 7e 73 50 5d 4a 47 dc d1 c6 cb e8 e5 f2 ff b4 b9 ae a3 80 8d 9a 97
''')
gm14_data = strlib.str_to_int_array('''
00 0e 1c 12 38 36 24 2a 70 7e 6c 62 48 46 54 5a e0 ee fc f2 d8 d6 c4 ca 90 9e 8c 82 a8 a6 b4 ba
db d5 c7 c9 e3 ed ff f1 ab a5 b7 b9 93 9d 8f 81 3b 35 27 29 03 0d 1f 11 4b 45 57 59 73 7d 6f 61
ad a3 b1 bf 95 9b 89 87 dd d3 c1 cf e5 eb f9 f7 4d 43 51 5f 75 7b 69 67 3d 33 21 2f 05 0b 19 17
76 78 6a 64 4e 40 52 5c 06 08 1a 14 3e 30 22 2c 96 98 8a 84 ae a0 b2 bc e6 e8 fa f4 de d0 c2 cc
41 4f 5d 53 79 77 65 6b 31 3f 2d 23 09 07 15 1b a1 af bd b3 99 97 85 8b d1 df cd c3 e9 e7 f5 fb
9a 94 86 88 a2 ac be b0 ea e4 f6 f8 d2 dc ce c0 7a 74 66 68 42 4c 5e 50 0a 04 16 18 32 3c 2e 20
ec e2 f0 fe d4 da c8 c6 9c 92 80 8e a4 aa b8 b6 0c 02 10 1e 34 3a 28 26 7c 72 60 6e 44 4a 58 56
37 39 2b 25 0f 01 13 1d 47 49 5b 55 7f 71 63 6d d7 d9 cb c5 ef e1 f3 fd a7 a9 bb b5 9f 91 83 8d
''')
sbox = pyrtl.RomBlock(bitwidth=8,
addrwidth=8,
romdata=sbox_data,
asynchronous=True)
inv_sbox = pyrtl.RomBlock(bitwidth=8,
addrwidth=8,
romdata=inv_sbox_data,
asynchronous=True)
rcon = pyrtl.RomBlock(bitwidth=8,
addrwidth=8,
romdata=rcon_data,
asynchronous=True)
GM9 = pyrtl.RomBlock(bitwidth=8,
addrwidth=8,
romdata=gm9_data,
asynchronous=True)
GM11 = pyrtl.RomBlock(bitwidth=8,
addrwidth=8,
def build_mem(data):
return pyrtl.RomBlock(bitwidth=8,
addrwidth=8,
romdata=data,
build_new_roms=True,
asynchronous=True)